EGR 278
Digital Logic Lab
File: N278L11A
Lab # 11
Sequential Circuit Design using PLDs
A.
Objective
The objective of this laboratory is to introduce the student to the use of sequential circuit design
using Programmable Logic Devices (PLDs). Sequential circuits will be designed by the student
using state equations and D flip-flops and the circuits will be implemented and tested using a
PLD.
B.
Materials
Breadboard
5V Power Supply
ALL-07 Universal Programmer
PLDShell 5.0 Software
C.
GAL22V10 Programmable Logic Device (PLD)
Common-anode 7-segment display
7447 BCD-to-7-segment decoder/driver
Seven 220 or 330 ohm resistors
Reference
Handouts - “PLDShell Example: GAL3.PDS”
“Loading PLDShell 5.0”
“Instructions for using PLDShell 5.0”
PLDShell 5.0 Manual
GAL22V10 Data Sheet
“Using the ALL-07 Universal Programmer & Tester”
D.
Introduction
Sequential circuit design considerations
An important topic to consider when designing sequential circuits is the method to be used.
There are several possible methods, including the “excitation table method” and design by state
equations. Another important considerations is which type of flip-flop to use in the design: SR,
JK, D, or T. The JK flip-flop is the most versatile and typically yields the simplest circuit to
implement.
If a sequential circuit design is to be implemented using PLDs where the number of gates required
and the type of flip-flop to be used is not of great concern, it may be advantageous to simply use
the simplest design method rather than the most efficient. The simplest design method is in many
cases to use state equations with D flip-flops. The general form of the state equation for a D flipflop is:
Q(t + 1) = D
So the input for each D flip-flop is simply determined by finding an expression for the next state
for that flip-flop. An example using this method is shown on the following pages. Furthermore,
the example has been implemented using PLDShell 5.0 and is shown in the handout to be
provided by the instructor entitled GAL3.PDS.
Page 2
Example: Design a 4-bit counter using D flip-flops.
A 4-bit counter, also called a modulo-16 counter, counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15 and repeats. The state diagram is shown in Figure 1 below.
0
15
1
14
2
13
3
12
4
5
11
6
10
7
9
8
Figure 1: State diagram for a 4-bit counter
The corresponding state table is shown in Figure 2 below. Note that the state is shown in decimal
form in the state diagram, whereas it is shown in binary form in the state table with bit D as the
MSB.
Present State
Next State
D
C
B
A
D
C
B
A
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
Figure 2: State table for a 4-bit counter
Page 3
The characteristic equation for a D flip-flop is very simple: Q(t + 1) = D.
So the expression for the next state is simply connected to the D input on the flip-flop.
Expressions for the next state for each of the four flip-flops is determined using Karnaugh maps
shown in Figure 3 below.
D(t + 1)
BA
DC 00
00 0
01
0
11
0
01 0
0
11 1
10 1
C(t + 1)
10
0
BA
DC 00
00 0
01
0
11
1
1
0
01 1
1
1
0
1
11 1
1
1
1
10 0
B(t + 1)
10
0
BA
DC 00
00 0
01
1
11
0
0
1
01 0
1
1
0
1
11 0
0
1
0
10 0
A(t + 1)
10
1
BA
DC 00
00 1
01
0
11
0
10
1
0
1
01 1
0
0
1
1
0
1
11 1
0
0
1
1
0
1
10 1
0
0
1
Figure 3: Karnaugh maps for the state equations for the 4-bit counter
Minimal SOP expressions for each output yield the state equations shown below in Figure 4:
D(t + 1) = D • C + D • B + D • A + D • C • B • A
C(t + 1) = C • B + C • A + C • B • A
B(t + 1) = B • A + B • A
A(t + 1) = A
Figure 4: State equations for the 4-bit counter
The state equations above are implemented in the circuit shown below in Figure 5.
D
C
D
B
D
A
D(t + 1)
DD QD
D (MSB)
D
C
B
QD
A
D
C
B
C
C(t + 1)
A
DC QC
C
C
B
QC
A
C
Count
(DCBA)
B
A
B(t + 1)
DD QB
B
B
A
QB
A(t + 1)
A
B
DA QA
QA
A
A
Clock
Figure 5: Logic Diagram for the 4-bit counter
Page 4
Implementing the 4-bit counter using PLDShell
The logic diagram in Figure 5 requires 16 gates or flip-flops. It can be easily implemented using a
single PLD. The state equations in Figure 4 can be rewritten in the appropriate format for
PLDShell. Also note that each term is ANDed with CLR, and active-HIGH clear signal. The
counter will be cleared to 0000 when CLR is LOW and the counter will count normally when
CLR is HIGH. The state equations for the 4-bit counter as shown previously in Figure 4 are
repeated below in order to compare them to the form of the state equations used in PLDShell as
shown in Figure 6 below.
D(t + 1) = D • C + D • B + D • A + D • C • B • A
C(t + 1) = C • B + C • A + C • B • A
B(t + 1) = B • A + B • A
A(t + 1) = A
Figure 4: State equations for the 4-bit counter (shown for a second time)
QD := CLR ∗ (QD ∗ / QC + QD ∗ / QB + QD ∗ / QA + /QD ∗ QC ∗ QB ∗ QA)
QC := CLR ∗ (QC ∗ / QB + QC ∗ / QA + /QC ∗ QB ∗ QA)
QB := CLR ∗ (QB ∗ / QA + /QB ∗ QA)
QA := CLR ∗ / QA
Figure 6: State equations for the 4-bit counter in PLDShell format
Page 5
E. Preliminary Work
1. Each student (no teams) should design a counter that will count out each of the unique digits of
his or her SSN in the order in which they occur, followed by the all digits from 0 to 9 that do
not occur in the SSN from highest to lowest. Note that all counting sequences will have all ten
digits. In order to make the counter "self-starting", let all unused counts (10 - 15) go to the first
count in your sequence. An example is shown below.
Example: SSN = 144-86-8443
Counting sequence = 1, 4, 8, 6, 3, 9, 7, 5, 2, 0
digits in your
SSN in the
order in which
they occur
digits from 0 to 9
that are not in
your SSN from
highest to lowest
Your design should include the following:
• a state diagram (be sure to include all 16 counts)
• a state table
• the K-maps used to generate the state equations
• the state equations
• the .PDS file used to implement the counter using PLDShell 5.0 using an GAL22V10 PLD.
The PDS file should be well documented. Include a SIMULATION section that initiates
the counter to count 0 and cycles the counter through 2 full cycles (20 counts) ) and also
tests the CLR signal for resetting the counter.
• the corresponding .RPT file
• the corresponding .HST file (waveform file) with a vector COUNT displaying the count and
showing proper operation of the clear signal for resetting the counter
• the corresponding JEDEC file (.JED) on a floppy disk ready to download into the PLD
programmer at the beginning of the lab. You do not need to print this file.
2. If the counter were to be implemented using D flip-flops, 2-input AND gates, 2-input OR gates,
and INVERTERS, draw the logic diagram. Include the input clock. Label the output count.
What is the total number of gates required? Note that only one PLD will be used to replace this
circuit.
3. Generate complete circuit documentation for the counter to be implemented. The
documentation should include the connection of the 4 outputs on the PLD to a 7-segment
display via a 7447 BCD-to-7-segment decoder/driver and the input clock connection from a 1
Hz clock signal produced by either a 555 timer or the Leader 1300 signal generator. If a 555
timer is used, show the calculations used to determine the resistor and capacitor values.
555 Timer
(1 Hz clock)
GAL22V10
PLD
7447
BCD-to-7 sement
decoder/driver
Page 6
F. Laboratory Work
Program the PLD using the JED file generated in the Preliminary Work. Construct the circuit
used to test the PLD according to the wire-list generated in step 3 of the Preliminary Work. Use a
1 Hz clock generator to clock the circuit (using either a 555 timer or the Leader 1300 signal
generator). The output should count through the appropriate sequence and be displayed on the 7segment display. Demonstrate the circuit to the instructor.