ECE 271 HW #4 (Due Wednesday, February 22nd)
1. Design a modulo-6 counter and give the excitation equations for all FFs.
2. Design a synchronous counter with a count sequence of 0, 3, 1, 5. Treat all
unused counter states (outputs) not in the sequence as don’t care states.
Make sure your circuit will come up in one of the count sequence values
when power is applied.
3. Design a synchronous counter with a count sequence of all prime numbers
between 3 and 15. Give the excitation equations. Map any unused counter
states into the state whose output is the largest prime number output by this
counter.q