1st Sessional Solution
Computer Organization
Subject Name
Roll No. of Student
Subject Code
Max Marks
Max Time
ECS -401
30 Marks
1 Hr. 30 Mins.
SECTION A
Answer No. 1
(i)
(ii)
(iii)
(iv)
(943.125)10 = (1110101111.001)2
(6B.28)16 = (1101011.00101000)2
(A72E)16 = (123456)8
(101.01)10 = (5.2)8
Answer No. 2
Computer Buses

The collection of paths connecting components is called the interconnection structure.

When a word of data transferred between modules, all its bits are transferred in parallel.

These bits are transferred simultaneously over different wire.

A group of wires that connects several devices is called a Bus.

In addition to the wires that carry data, the computer must have some lines for addressing and
control purposes.
Single-Bus Structure
The simplest way to interconnect functional units of a computer is to use a single system bus. System bus consist
of:

Data bus

Address bus

Control bus
This bus is time shared. Because the bus can be used for only one transfer at a time, only two units can
communicate at any given instant.
Data bus

The data lines provide a path for moving data between system modules. These lines, collectively are
called the data bus.

The data bus are bi-directional so that data can be send or received by the processor.
Address bus

Every device connected to bus has an address. A memory unit is given a block of address, depending on
the number of words in it.

For example, if the CPU wishes to read a word of the data from memory, it puts the address of the desired
word on the address line.
Control bus

Control lines are used to control the various units like memory and I/O, processor uses control signals to
control various modules.

Control signals transmit both command and timing information. Control signals specify operation to be
performed. Typical control signals include:

Memory read

Memory write

I/O read

I/O write

Bus request
Multiple Bus Hierarchy:
Answer No. 3
MIPS: Million Instructions Per Second
MIPS
= Instruction Count / Time * 10^6
= Clock Rate / CPI * 10^6
•
machines with different instruction sets ?
•
programs with different instruction mixes ?
•
•
dynamic frequency of instructions
uncorrelated with performance
MFLOP/S
= FP Operations / Time * 10^6
•
machine dependent
•
often not where time is spent
Answer No. 4
Types of Errors
Single-bit error
Single bit errors are the least likely type of errors in serial data transmission because the noise must
have a very short duration which is very rare. However this kind of errors can happen in parallel
transmission.
Example:
 If data is sent at 1Mbps then each bit lasts only 1/1,000,000 sec. or 1 μs.
 For a single-bit error to occur, the noise must have a duration of only 1 μs, which is very rare.
Burst error
The term burst error means that two or more bits in the data unit have changed from 1 to 0 or from 0 to
1. Burst errors does not necessarily mean that the errors occur in consecutive bits, the length of the
burst is measured from the first corrupted bit to the last corrupted bit. Some bits in between may not
have been corrupted.
 Burst error is most likely to happen in serial transmission since the duration of noise is normally
longer than the duration of a bit.
 The number of bits affected depends on the data rate and duration of noise.
Example:
 If data is sent at rate = 1Kbps then a noise of 1/100 sec can affect 10 bits.(1/100*1000)
 If same data is sent at rate = 1Mbps then a noise of 1/100 sec can affect 10,000 bits.(1/100*106)
Error detection
Error detection means to decide whether the received data is correct or not without having a copy of
the original message.
Error detection uses the concept of redundancy, which means adding extra bits for detecting
errors at the destination.
Single-bit error correction
To correct an error, the receiver reverses the value of the altered bit. To do so, it must know which bit is
in error.
Number of redundancy bits needed
•
Let data bits = m
•
Redundancy bits = r
Total message sent = m+r
The value of r must satisfy the following relation:
2r ≥ m+r+1
Hamming Code
Example of Hamming Code
Single-bit error
Answer No. 5
CISC(Complex Instruction Set Computer)
•
•
These computers with many instructions and addressing modes came to be known as Complex
Instruction Set Computers (CISC)
One goal for CISC machines was to have a machine language instruction to match each highlevel language statement type.
Criticisms on CISC
-Complex Instruction
→ Format, Length, Addressing Modes
→ Complicated instruction cycle control due to the complex decoding HW
and decoding process
- Multiple memory cycle instructions
→ Operations on memory data
→ Multiple memory accesses/instruction
- Microprogrammed control is necessity
→ Microprogram control storage takes substantial portion of CPU chip area
→ Semantic Gap is large between machine instruction and microinstruction
- General purpose instruction set includes all the features required by
individually different applications
→ When any one application is running, all the features required by
the other applications are extra burden to the application
RISC
In the late ‘70s - early ‘80s, there was a reaction to the shortcomings of the CISC style of processors
– Reduced Instruction Set Computers (RISC) were proposed as an
alternative
• The underlying idea behind RISC processors is to simplify the instruction set and reduce instruction
execution time
Note : In RISC type of instructions , we cant access the memory operands directly .
Evaluate X = (A + B) * (C + D) :
MOV
R1, A
/* R1 ← M[A] */
MOV
R2, B
/* R2 ← M[B] */
ADD
R1,R1,R2
/* R1 ← R1 + R2
MOV
MOV
R2, C
/* R2 ← M[C] */
R3, D
/* R3 ← M[D] */
ADD
R2,R2, R3
/* R2 ← R2 + R2 */
MUL
R1,R1, R2
/* R1 ← R1 * R2 */
MOV
X, R1
/* M[X] ← R1 */
• RISC processors often feature:
– Few instructions
– Few addressing modes
– Only load and store instructions access memory
– All other operations are done using on-processor registers
– Fixed length instructions
– Single cycle execution of instructions
– The control unit is hardwired, not microprogrammed
Since all (but the load and store instructions) use only registers for operands,
– only a few addressing modes are needed
• By having all instructions the same length :
– reading them in is easy and fast
• The fetch and decode stages are simple, looking much more like Mano’s BC
than a CISC machine
– The instruction and address formats are designed to be easy to decode
– (Unlike the variable length CISC instructions,) the opcode and register
fields of RISC instructions can be decoded simultaneously
• The control logic of a RISC processor is designed to be simple and fast :
– The control logic is simple because of the small number of instructions and
the simple addressing modes
– The control logic is hardwired, rather than microprogrammed, because
hardwired control is faster
ADVANTAGES OF RISC
VLSI Realization
- Control area is considerably reduced
⇒ RISC chips allow a large number of registers on the chip
- Enhancement of performance and HLL support
- Higher regularization factor and lower VLSI design cost
• Computing Speed
- Simpler, smaller control unit ⇒ faster
- Simpler instruction set; addressing modes; instruction format
⇒ faster decoding
- Register operation ⇒ faster than memory operation
- Register window ⇒ enhances the overall speed of execution
- Identical instruction length, One cycle instruction execution
⇒ suitable for pipelining ⇒ faster
Design Costs and Reliability
- Shorter time to design
⇒ reduction in the overall design cost and reduces the problem that the end product will be
obsolete by the time the design is completed
- Simpler, smaller control unit
⇒ higher reliability
- Simple instruction format (of fixed length)
⇒ ease of virtual memory management
• High Level Language Support
- A single choice of instruction ⇒ shorter, simpler compiler
- A large number of CPU registers ⇒ more efficient code
- Register window ⇒ Direct support of HLL
- Reduced burden on compiler writer
RISC VS CISC
•
•
•
•
The CISC Approach
Thus, the entire task of multiplying two numbers can be completed with one instruction:
– MULT 2:3, 5:2
One of the primary advantages of this system is that the compiler has to do very little work to
translate a high-level language statement into assembly. Because the length of the code is
relatively short, very little RAM is required to store instructions. The emphasis is put on building
complex instructions directly into the hardware.
The RISC Approach
In order to perform the exact series of steps described in the CISC approach, a programmer
would need to code four lines of assembly:
• LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3,
A At first, this may seem like a much less efficient way of completing the operation. Because
there are more lines of code, more RAM is needed to store the assembly level instructions. The
compiler must also perform more work to convert a high-level language.
•
RISC vs CISC
Emphasis on hardware
Transistors used for storing
complex instructions
Emphasis on software
Spends more transistors
on memory registers
Includes multi-clock
complex instructions,
Single-clock reduced instruction only
Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions
Register to register:
"LOAD" and "STORE"
are independent instructions
Small code sizes
large code sizes
High cycles per second
Low cycles per second
Answer No. 6
•
Instruction set
– Data Transfer Instructions
o Typical Data Transfer Instructions
o Data Transfer Instructions with Different Addressing Modes
– Data Manipulation Instructions
o Arithmetic instructions
o Logical and bit manipulation instructions
o Shift instructions
– Program Control Instructions
o Conditional Branch Instructions
o Subroutine Call & Return
DATA TRANSFER INSTRUCTIONS
These are the type of instructions used only for the transfer of data from registers to
registers, registers to memory operands and other memory components. There is no
manipulation done on the data values.
•
Typical Data Transfer Instructions
Name
Mnemonic
Load
Store
LD
ST
Move
MOV
Exchange
XCH
Input
IN
Output
OUT
Push
PUSH
Pop
POP
These are the type of instructions in which there is no usage of various addressing modes.
We have a direct transfer between the various registers and memory components.
 Like Load and store we used for the transfer of data to and from the accumulator.
 LD 20
 ST D
 Move and Exchange are used for the data transfer between various general
purpose registers.
 MOV R1,R2
 MOV R1,X
 XCH R1,R2
 Input and Output are used for the data transfer between memory and I/O
devices.
 Push and Pop operations are used for information flow between stack and
memory.

Data Transfer Instructions with Different Addressing Modes
Assembly
Register Transfer
Mode
Convention
Direct address
AC M[ADR]
LD ADR
Indirect address
LD @ADR
AC  M[M[ADR]]
Relative address
LD $ADR
AC  M[PC + ADR]
AC  NBR
Immediate operand LD #NBR
Index addressing
Register
Register indirect
Autoincrement
Autodecrement
AC  M[ADR + XR]
LD ADR(X)
AC  R1
LD R1
LD (R1)
LD (R1)+
LD -(R1)
AC  M[R1]
AC  M[R1], R1  R1 + 1
R1  R1 - 1, AC  M[R1]
Table 3.2
In these type of data transfers we use different addressing for loading the operand value in the
accumulator register.
DATA MANIPULATION INSTRUCTIONS


Three Basic Types:
 Arithmetic instructions
 Logical and bit manipulation instructions
 Shift instructions
Arithmetic Instructions : These are the type of instructions used for arithmetical calculations like
addition , subtraction , increment etc.
Name
Mnemonic
Increment
INC
Decrement
DEC
Add
ADD
Subtract
SUB
Multiply
MUL
Divide
DIV
Add with Carry

ADDC
Subtract with Borrow
SUBB
Negate(2’s Complement)
NEG
Logical and Bit Manipulation Instructions
These are the type of instructions in which are operations are computed on string of bits. These
bits are treated as individual and thus the operation can be done on individual or a group of bits
ignoring the whole value and even new bits insertion is possible.
For example:
CLR R1 will make all the bits as 0.
COM R1 will invert all the bits.
AND , OR and XOR will produce the result on 2 individual bits
of each operand.
E.g.: AND of 0011 and 1100 will result to:
0000.
AND instruction is also known as mask instruction as if we have to mask some values of
operand we can AND that value with 0s giving other inputs as 1(high).
E.g.: Suppose we have to mask register with value 11000110
On 1st , 3rd and 7th bit. Then we will have to AND it with value 01011101.
CLRC, SETC and COMC will work only on 1 bit of the operand i.e. Carry.
Similarly in case of EI and DI we work only on 1 bit interrupt flip flop to enable it.
Name
Mnemonic
Clear
Complement
CLR
COM
AND
AND
OR
OR
Exclusive-OR
XOR
Clear carry
CLRC
Set carry
SETC
Complement carry
COMC
Enable interrupt
Disable interrupt
EI
DI
Shift Instructions : These are the type of instructions which modify the whole value of operand but by
shifting the bits on left or right side.

Say R1 has value 11001100
o SHR inserts 0 at the left most position.
 Result 01100110
o SHL inserts 0 at the right most position.
 Result 10011000
o SHRA : In case of SHRA the sign bit remains same else every bit shift left or right
accordingly.
 Result 11100110
o SHLA is same as that of SHL inserting 0 in the end.
 Result 10011000
o In ROR , all the bits are shifted towards right and the rightmost one moves to leftmost
position.
 Result : 01100110
o In ROL , all the bits are shifted towards left and the leftmost one moves to rightmost
position.
 Result : 10011001
o In case of RORC , suppose we have a carry bit as 0 with register R1. In this all the bits of
the register will be right shifted and the value of carry will be moved to leftmost position
and the rightmost position will be moved to carry.
o
 Result : 01100110 with carry as 0
Similarly in case of ROLC , we will get all the bits of the register left shifted and the
value of carry moved to rightmost position and the leftmost position will be moved to
carry.
 Result : 10011000 with carry as 1.
Name
Mnemonic
Logical shift right
SHR
Logical shift left
SHL
Arithmetic shift right
SHRA
Arithmetic shift left
SHLA
Rotate right
ROR
Rotate left
ROL
Rotate right thru carry
RORC
PROGRAM CONTROL INSTRUCTIONS:
Rotate left thru carry
ROLC
Before starting with program control instructions, lets study the concept of PC i.e. Program counter.
Program counter is the register which tells us the address of the next instruction to be executed. When
we fetch the instruction pointed by PC from memory it changes it value giving us the address of the next
instruction to be fetched. In case of sequential instructions it simply increments itself and in case of
branching or modular programs it gives us the address of the first instruction of the called program.
After the execution of the called program , the program counter points back to the instruction next to
the instruction from which the subprogram was called. In case of go to kind of instructions the program
counter simply changes the value of program counter with out keeping any reference of the previous
instruction..
+1
PC
In-Line Sequencing (Next instruction is fetched from
the next adjacent location in the memory)
Address from other source; Current Instruction, Stack,
Program Control Instructions: These
instructions
are used for
the transfer
of control etc.
to other
etc; Branch,
Conditional
Branch,
Subroutine,
instructions. That is these instructions are used in case we have to execute the next instruction from
some other location instead of sequential manner.
The conditions can be :
Calling a sub program
Returning to the main program
Jumping onto some other instruction or location
Skip the instructions in case of break and exit or in case the condition you check is false
and so on
Name
Mnemonic
Branch
BR
Jump
JMP
Skip
SKP
Call
CALL
Return
RTN
Compare(by
 )their results of CMP
*CMP and TST instructions
do not retain
operation (- and AND, respectively).They only
set or clear certain flags.
Test(by AND)
TST
Conditional Branch Instructions: These are the instructions in which we test some conditions and
depending on the result we go either for branching or sequential way.
Mnemonic
Branch condition
Tested condition
BZ
Branch if zero
Z=1
BNZ
Branch if not zero
Z=0
BC
Branch if carry
C=1
BNC
Branch if no carry
C=0
BP
Branch if plus
S=0
BM
Branch if minus
S=1
BV
Unsigned compare
Branch ifconditions
overflow (A - B)
V=1
BHI
BNV
Branch if higher
Branch if no overflow
BHE
Branch if higher or equal
BLO
Branch if lower
A<B
BLOE
Branch if lower or equal
AB
BE
A>B
V=0
AB
Branch if equal
Signed compare conditions (A - B)
A=B
A
A
>B
B
BNE
BGT
Branch
equal
Branch if
if not
greater
than
BGE
Branch if greater or equal A  B
BLT
Branch if less than
A<B
BLE
Branch if less or equal
AB
BE
Branch if equal
A=B
Branch if not equal
AB
BNEReturn:
Subroutine Call and
Subroutine Call: Call Subroutine
Jump to Subroutine
Branch to Subroutine
Branch & save return address
Two most important operations are implied:
*Branch to the beginning of the Subroutine
-Same as the branch or conditional branch
*Save the return address to get the address of the location of the calling program
upon exit from the subroutine.

Location of storing return address:
 Fixed Location in the subroutine (Memory)



Fixed Location in memory
In a processor Register
In memory stack
-most efficient way
CALL
SP  SP - 1
 PC
M[SP]
PC  EA
RTN
PC  M[SP]
SP  SP + 1
Answer No. 7
Booth’s algorithm is depicted in Figure 10.12 and can be described as follows.
As before, the multiplier and multiplicand are placed in the Q and M registers,
respectively. There is also a 1-bit register placed logically to the right of the least
significant bit (Q0) of the Q register and designated Q-1 its use is explained shortly.
The results of the multiplication will appear in the A and Q registers. A and Q-1
are initialized to 0. As before, control logic scans the bits of the multiplier one at a
time. Now, as each bit is examined, the bit to its right is also examined. If the two
bits are the same (1–1 or 0–0), then all of the bits of the A, Q, and Q-1 registers are
shifted to the right 1 bit. If the two bits differ, then the multiplicand is added to or
subtracted from the A register, depending on whether the two bits are 0–1 or 1–0.
Following the addition or subtraction, the right shift occurs. In either case, the right
shift is such that the leftmost bit of A, namely, An-1not only is shifted into An-2,
but also remains in An-1. This is required to preserve the sign of the number in A
and Q. It is known as an arithmetic shift, because it preserves the sign bit.
Answer No. 8
Division is somewhat more complex than multiplication but is based on the same
general principles. As before, the basis for the algorithm is the paper-and-pencil
approach, and the operation involves repetitive shifting and addition or subtraction.
Figure 10.15 shows an example of the long division of unsigned binary integers.
It is instructive to describe the process in detail. First, the bits of the dividend
are examined from left to right, until the set of bits examined represents a number
greater than or equal to the divisor; this is referred to as the divisor being able to
divide the number. Until this event occurs, 0s are placed in the quotient from left
to right. When the event occurs, a 1 is placed in the quotient and the divisor is subtracted
from the partial dividend. The result is referred to as a partial remainder.
From this point on, the division follows a cyclic pattern. At each cycle, additional
bits from the dividend are appended to the partial remainder until the result is
greater than or equal to the divisor. As before, the divisor is subtracted from this
number to produce a new partial remainder. The process continues until all the bits
of the dividend are exhausted.
Answer No. 9
•
Addressing modes
– Implied Mode
– Immediate Mode
– Register Mode
– Register Indirect Mode
– Autoincrement or Autodecrement Mode
– Direct Addressing Mode
– Indirect Addressing Mode
– Relative addressing Mode
In the last lecture we studied the instruction formats, now we study how the instructions use the
addressing modes of different types.
Addressing Modes
Addressing Modes
* Specifies a rule for interpreting or modifying the address field of the instruction (before the
operand is actually referenced)
* Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the instruction efficiently
In simple words we can say the addressing modes is the way to fetch operands (or Data) from memory.
TYPES OF ADDRESSING MODES
• Implied Mode
: Address of the operands are specified implicitly in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]
- Examples from BC : CLA, CME, INP
• Immediate Mode
: Instead of specifying the address of the operand,operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- (-)Sometimes, require more bits than the address
- (+) Fast to acquire an operand
- Useful for initializing registers to a constant value
• Register Mode
: Address specified in the instruction is the register address
- Designated operand need to be in a register
- (+) Shorter address than the memory address
-- Saving address field in the instruction
- (+) Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
• Register Indirect Mode
: Instruction specifies a register which contains the memory address of the operand
- (+) Saving instruction bits since register address is shorter than the memory address
- (-) Slower to acquire an operand than both the register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)
• Autoincrement or Autodecrement Mode
- Similar to the register indirect mode except :
When the address in the register is used to access memory, the value in the register is
incremented or decremented by 1 automatically
• Direct Address Mode
: Instruction specifies the memory address which can be used directly to access the memory
- (+) Faster than the other memory addressing modes
- (-) Too many bits are needed to specify the address for a large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)
- E.g., the address field in a branch-type instr
• Indirect Addressing Mode
: The address field of an instruction specifies the address of a memory location that contains the
address of the operand
- (-) Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]
• Relative Addressing Modes
: The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated
register to calculate the address of the operand
--> Effective addr = addr part of the instr + content of a special register
- (+) Large physical memory can be accessed with a small number of
address bits
- EA = f(IR(address), R), R is sometimes implied
--> Typically EA = IR(address) + R
- 3 different Relative Addressing Modes depending on R
* (PC) Relative Addressing Mode (R = PC)
* Indexed Addressing Mode (R = IX, where IX: Index Register)
* Base Register Addressing Mode (R = BAR(Base Addr Register))
* Indexed addressing mode vs. Base register addressing mode
- IR(address) (addr field of instr) : base address vs. displacement
- R (index/base register) : displacement vs. base address
- Difference: the way they are used (NOT the way they are computed)
* indexed addressing mode : processing many operands in an array using the same instr
* base register addressing mode : facilitate the relocation of programs in memory in multiprogramming
systems
Addressing Modes: Examples