International Electron Devices Meeting
2010
Summary and Outlook
Walter Snoeys – PH ESE ME – 2011
1
Some numbers





~1470 participants (about same level as 2009)
210 regular papers in 33 sessions over 3 days (somewhat less
in number)
555 papers submitted Paper acceptance rate = 35%
(acceptance of university papers low)
Growing areas: design-device, packaging/3D, power devices,
energy solar…, bio
2 short courses:
 15nm CMOS technology
 Reliability and Yield of advanced integrated technologies


Luncheon address J. Clifford (Qualcomm) : Evolution and
Directions for Mobile Wireless Devices
Evening Panel Sessions: integration + power crunch
Walter Snoeys – PH ESE ME – 2011
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OUTLINE

CMOS

Lithography

Special devices

Metallization

Memories

Displays, Sensors and MEMS
Walter Snoeys – PH ESE ME – 2011
3
CMOS in N-well technology
B
S
G D
P+
N+
N+
D
S
P+
P+
N+
P-substrate
N-well
NMOS
D
PMOS
S B
D
or G
G
S
B
G
S
S B
G
B
Walter Snoeys – PH ESE ME – 2011
D
D
4
The ‘real thing’

Mukesh Khare IBM
Walter Snoeys – PH ESE ME – 2011
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The
real
thing
Walter Snoeys – PH ESE ME – 2011
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The MOS transistor: operation principle
S
Linear region (low Vds)
G
D
n+
-
n+
-
-
-
Electrons are attracted to SiO2Si interface => conductive layer
(channel) is created. (Psubstrate gets inverted locally).
The channel which links source
and drain and forms a resistor
between the two. Current
increases significantly with
increasing VDS
Walter Snoeys – PH ESE ME – 2011
7
The MOS transistor: operation principle
S
G
n+
Depletion layer
Saturation region (high Vds)
D
n+
Significant current flow and
resistive drop in the channel.
Electrons near the drain are
insufficiently attracted by the
gate, and the channel gets
pinched off. Beyond that point
increasing VDS does not
change current significantly.
Note: before inversion layer is formed already current flow = weak inversion
Walter Snoeys – PH ESE ME – 2011
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Some examples of MOS characteristics
Id=f(Vd)
Id=f(Vg) Linear scale
3.00E-05
1.60E-03
1.40E-03
1.20E-03
1.00E-03
8.00E-04
6.00E-04
4.00E-04
2.00E-04
0.00E+00
2.50E-05
2.00E-05
1.50E-05
1.00E-05
2.30
2.00
1.70
1.40
1.10
0.80
0.50
0.20
-0.10
-0.40
5.00E-06
Log(Id)=f(Vg) (Logarithmic scale)
0.00E+00
0.00 0.35 0.70 1.05 1.40 1.75 2.10 2.45
gm=f(Vg) (in linear regime)
1.00E-01
1.20E-04
1.00E-03
1.00E-04
1.00E-05
8.00E-05
1.00E-07
6.00E-05
1.00E-09
4.00E-05
1.00E-11
2.00E-05
1.00E-13
-0.40 0.05
0.50
0.95
1.40
1.85
2.30
0.00E+00
-0.35 0.10
Walter Snoeys – PH ESE ME – 2011
0.55
1.00
1.45
1.90
2.35
9
The Boltzmann tyranny
Log(Id)=f(Vg) (Logarithmic scale)
1.00E-01
1.00E-03
Exp(
Vgs
)
nkT/q
Ion
Strong
inversion
1.00E-05
1.00E-07
Weak
inversion
1.00E-09
1.00E-11
Ioff
1.00E-13
-0.40 0.05
0.50
0.95
1.40
1.85
2.30
Weak inversion slope ~ 60 mV/decade, Ion/Ioff=10e6 => 360 mV
Walter Snoeys – PH ESE ME – 2011
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Steep-slope devices (see session 16)



Tunneling (only over limited range)
still really in development
Floating body (hysteresis ! Potential in memories)
Polarization in gate dielectric stack
Walter Snoeys – PH ESE ME – 2011
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‘The number of transistors per integrated
circuit increases exponentially with time
(doubling roughly every two years)’
Walter Snoeys – PH ESE ME – 2011
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More Moore and More Than Moore
Walter Snoeys – PH ESE ME – 2011
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More Moore and More Than Moore
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How has Moore’s law been possible ?
How has Moore’s law been possible ?
K. De Meyer
K. De Meyer
Mobility enhancement (K. Kuhn)
 New materials (III-V) and Ge
 High mobility but not in all valleys of the band, need to confine carriers
to high mobility valley
 Low Eg materials (eg Ge) can have higher Ioff due to band-to-band
tunneling
 Technological challenge: lattice mismatch and defect-free material
growth on Si
 Different orientations (no strain)
 On (100) PMOS best <100>, NMOS isotropic
 On (110) NMOS best <100>, PMOS best <110>
 Overall best : NMOS (100)<110>, PMOS (110) <110>
 Hetero Orientation Transistors (HOT)
 Stress and Strain : apply strain to channel to change the energy band shape
 Reduce scattering
 Enhance mobility, reduce effective mass
 Pushing carriers in valleys with low effective mass,
 Confinement
2008 Krishnamohan et al (session 36.5) PMOS
IEDM 2008 P. Packan et al. (Intel) Session 3.4
Stress improves PMOS and NMOS, but orientation change degrades NMOS
Confinement limits this degradation -> Modeling ???
IEDM 2008 P. Packan et al. (Intel) Session 3.4
Lg = 160 nm
Reduction 40 %
Lg = 35 nm
Reduction 13 %
Confinement limits NMOS degradation -> Modeling ???
Note: also dependence on W…
‘Planar’ transistors (K. Kuhn)
Advanced spacerWalter
engineering
forMECfringe:
low k or removal
Snoeys – PH ESE
– 2011
23
Going to 15 nm…
M. Khare
Walter Snoeys – PH ESE ME – 2011
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Running out of steam in Bulk
M. Khare
Walter Snoeys – PH ESE ME – 2011
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Reality more difficult than ITRS predictions
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Reality more difficult than ITRS predictions
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Orthogonal change in roadmap (T. Skotnicki)
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2009 ITRS Roadmap adjustments (T. Skotnicki)

Gate length scaling will be less aggressive than past roadmap
predictions. Already included in 2008 with 3-5 year slow-down.
Added another year in 2009.

Ring oscillator delay added to CV/I as more realistic metric (!)

Addition of PMOS saturation current

Subthreshold source-drain leakage currents are held constant

Criterion for source/drain parasitic resistance is set for 33%
degradation vs ideal zero series resistance case
Walter Snoeys – PH ESE ME – 2011
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Transistor performance metrics (T. Skotnicki)
Walter Snoeys – PH ESE ME – 2011
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Importance of Drain Induced Barrier Lowering
Walter Snoeys – PH ESE ME – 2011
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DIBL: new performance driver
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Walter Snoeys – PH ESE ME – 2011
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Who does better than bulk ? (T. Skotnicki)
Walter Snoeys – PH ESE ME – 2011
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SOI: Why thin buried oxide ?
Avoid drain-to-channel coupling to reduce Short Channel
Effects and Drain
Induced Barrier Lowering
Walter Snoeys – PH ESE ME – 2011
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Ultra Thin Body and Buried Oxide (UTBB)
+ Body bias for tuning
Can tune to system need !!
Walter Snoeys – PH ESE ME – 2011
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Less mismatch in SOI
Walter Snoeys – PH ESE ME – 2011
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Mismatch and SRAM
Walter Snoeys – PH ESE ME – 2011
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CMOS

Ultrathin Body and Buried oxide quite some attention (ex
Leti/ST, paper 3.4.4):

Process papers on contact resistance, silicides, etc…
Walter Snoeys – PH ESE ME – 2011
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ALTERNATIVE : FIN FET
Significant
challenges in
manufacturing
Parasitics
Body bias
more difficult
Walter Snoeys – PH ESE ME – 2011
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CMOS & Process Technology sessions


CMOS
 3: Ultra-thin Body Transistors and Device Variability
 10: CMOS Performance Enhancing and Novel Devices
 27: Advanced High-k metal Gate SOC and High
Performance CMOS Platforms
 34: Advanced FINFETs and Nanowire FETs
Process Technology
 2: Advanced 3D Integration
 11: Channel Engineering and High-k Technology
 18: Advanced Technologies for Ge MOSFETs and New
Concept Devices
 26: Advanced Source/Drain and Channel Engineering
 33: Novel Process Technologies

Walter Snoeys – PH ESE ME – 2011
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Modeling and Reliability sessions

Modeling and Simulation
 8: High-Frequency and Multi-Gate Device Modeling
 15: Challenges in Advanced Device Performance and
Variation Modeling
 22: Simulation of Memory Devices
 26: Simulation of Non-Silicon Materials and Devices

Characterization, Reliability and Yield
 4: Front End of Line (FEOL) Reliability
 28: RTN and Memory
 35: Back-end SRAM and ESD Reliability
Walter Snoeys – PH ESE ME – 2011
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Special session: technology and design
17: Special Session – Confluence of Technology and Design –
Challenges for Non-Conventional Devices and 3D LSIs
 Through-chip interface as alternative
to
Through Silicon Via (see below)
 Liquid cooling (EPFL) with regulation
 Transistors (see above): electrostatics & DIBL, parasitic
capacitance (corner + gate to contact capacitance), design
with novel devices (Stanford)
 May the fourth (terminal) be with you – circuit design beyond
FinFET (AIST Japan), resistive connection to back gate
 Variability and self feedback devices (Arizona)
 Circuits to interface with cells and molecules (Michigan)
Walter Snoeys – PH ESE ME – 2011
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OUTLINE

CMOS

Lithography

Special devices

Metallization

Memories

Displays, Sensors and MEMS
Walter Snoeys – PH ESE ME – 2011
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Lithography (Sivakumar Intel)
Walter Snoeys – PH ESE ME – 2011
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Rayleigh’s Equation
Re solution  k1

NA

Walter Snoeys – PH ESE ME – 2011
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Lithography (Sivakumar Intel)
“should maintain k1 above or equal to 0.3 for manufacturability”
Walter Snoeys – PH ESE ME – 2011
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Lithography
Sivakumar Intel
Now defect
density on par
with dry litho
Walter Snoeys – PH ESE ME – 2011
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Going to lower k1
Walter Snoeys – PH ESE ME – 2011
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Going to lower k1
Walter Snoeys – PH ESE ME – 2011
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Going to lower k1
Walter Snoeys – PH ESE ME – 2011
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Going to lower k1
Walter Snoeys – PH ESE ME – 2011
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Going to lower k1
Walter Snoeys – PH ESE ME – 2011
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Dual pattern, pitch doubling etc…
Walter Snoeys – PH ESE ME – 2011
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Changing λ -> Extended UV

Steppers only becoming available
now

Need special reflective masks, and
need improvement on defect
densities

Need at least 2x in light intensity to
reach production grade volume

Immature photoresist
Walter Snoeys – PH ESE ME – 2011
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Sivakumar Intel
Walter Snoeys – PH ESE ME – 2011
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Ultimately determined by cost
Walter Snoeys – PH ESE ME – 2011
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OUTLINE

CMOS

Lithography

Special devices : emerging technologies

Metallization

Memories

Displays, Sensors and MEMS
Walter Snoeys – PH ESE ME – 2011
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Special devices sessions

Quantum, Power and Compound Semiconductor Devices
 6: Next Generation Digital Devices
 30: Ultra High Speed Transistors

Solid-State and Nanoelectronic Devices
 9: CNT, MTJ Devices and Nanowire Photodiodes
 16: Low-Power and Steep Slope Switching Devices
 23: Graphene Devices

13: Emerging Technologies: Next Generation Power devices
and Technology
Walter Snoeys – PH ESE ME – 2011
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Emerging technologies: AlGaN
Several
papers
Example:
(30.1)
Record fT
HRL
&
JPL
laboratories
Walter Snoeys – PH ESE ME – 2011
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Emerging technologies: AlGaN
Issue is substrate
availability,
compatibility with
Si if possible is
huge advantage
Samsung
GaN epitaxial
films on 4” and 8”
Si substrates
Walter Snoeys – PH ESE ME – 2011
62
Emerging technologies: Ge & III-V

Several papers (like the previous one) on III-V structures and
on strained Ge. Contact resistance issue for Ge NMOS

Several papers have been presented on Si substrate. Is an
area which receives quite a bit of attention to improve
standard CMOS
Example 7.4: intel
Walter Snoeys – PH ESE ME – 2011
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Emerging technologies : GRAPHENE



Example:
(23.1)
IBM
Graphene is a 2D system, a single layer of
carbon atoms.
Extreme electron mobility (200 000 cm2/Vs)
Large hole mobility (~ 1500 cm2/Vs)

Interesting (early development) for fast
electronics and fast photo detection

Contact resistance issue

Photon detection: need to create bandgap
to reduce leakage, but excellent absorption
and carrier transport (examining multilayers)
Walter Snoeys – PH ESE ME – 2011
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POWER DEVICES



13: Emerging Technologies:
Next Generation Power devices
and Technology
Significant production in Si
Some special applications
requiring higher performance
 SiC
 GaN
 Not clear yet which one will
win or whether both will stay
around
Walter Snoeys – PH ESE ME – 2011
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Emerging technologies: Integrated photonics
Towards laser Strained Ge on Si
Dartmouth College & MIT
Optically pumped laser
and LED
Walter Snoeys – PH ESE ME – 2011
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OUTLINE

CMOS

Lithography

Special devices : emerging technologies

Metallization

Memories

Displays, Sensors and MEMS
Walter Snoeys – PH ESE ME – 2011
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Metallization towards smaller pitches =>
need work on parasitics !!!
Walter Snoeys – PH ESE ME – 2011
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Other metallization issues





Dimension reduction
 Minimize sidewall/barrier/line edge roughness
 Intersection of pores with sidewall
 Patterning, cleaning and filling at nanodimensions
Seed layers
New materials/structures -> integr. complexity
Increased number of layers
 Thermo-mechanical issues
 Chemical Mechanical Polishing (CMP)
 Yield
Reliability
 Electromigration
Example (session 33.3): leakage
 Stress induced voids
between MIMcaps due to metal
 Time Dependent Breakdown
penetration in pores
Walter Snoeys – PH ESE ME – 2011
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Walter Snoeys – PH ESE ME – 2011
70
3D (session 2)





TSMC : Nice demonstration of
technology development, but
date of full production unclear
IMEC+Japan: stress around
via => keep-out zone for
transistors
Chinese with IBM
Chip fabrication where die
can be individually detached
(DE)
CEA – Leti – Minatec :
various substrates starting
from original SOITEC
technology, combined with
TSV
71
Walter Snoeys – PH ESE ME – 2011
Walter Snoeys – PH ESE ME – 2011
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Walter Snoeys – PH ESE ME – 2011
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OUTLINE

CMOS

Lithography

Special devices : emerging technologies

Metallization

Memories

Displays, Sensors and MEMS
Walter Snoeys – PH ESE ME – 2011
74
Memories and Sensors sessions


Memory Technology
 5: Flash Memory
 12: IT Magnetic RAM
 19: Resistive RAMs
 29: Phase Change Memory and 3-Dimensional Memory
Session 5: example Intel-Micron 64 Gb
Walter Snoeys – PH ESE ME – 2011
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Flash NAND structures
HYNIX
Toshiba 2008


Work on vertical structures
Scaling below 30nm requires significant work on the
transistors
Walter Snoeys – PH ESE ME – 2011
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Non-Volatile Memories







Already in 2007 more NAND and NOR flash memories shipped than
DRAM in its entire history (1.9e18)
NVM now ~60 B$ market
80 000 $/GByte in 1987 (256kB unit) to 1.5 $/Gbyte (16Gbyte unit) in 2007
40% price drop per year (ahead of Moore’s learning curve of 30 % per
year)
Litho, self-aligning, nand for less space, wafer size increase…
Some ‘Partial’ 3D
Now new possibility : cross-point memory
Walter Snoeys – PH ESE ME – 2011
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Cross-point memory
 Phase Change Memory:
heating and then quenching,
can be very small, can use
Multi-level Cell (need PNV)
and Multi-Layer Stacking.
Ultimate question is cost.
 RRAM: based on simple or
more complex oxides which
change conductive state, need
more work on reliability and
understanding of mechanism
IEEE Spectrum dec 2008
 Programmable Metallization
Cell
 Normally in combination with
switch, although recently
some without
Walter Snoeys – PH ESE ME – 2011
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Cross-point memory
 Spin Torque Transfer RAM infinite
endurance and high speed
HYNIX
 Work to reduce cell size but there are
good perspectives (HYNIX 54 nm,
Samsung perspectives for 30nm)
 Increase cell transistor drive current
and reduce magnetic tunnel junction
switching current
IBM : yields ok for 64 Mb
Walter Snoeys – PH ESE ME – 2011
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OUTLINE

CMOS

Lithography

Special devices

Metallization

Memories

Displays, Sensors and MEMS
Walter Snoeys – PH ESE ME – 2011
80
DISPLAYS, SENSORS and MEMS

7: MEMS Resonators: used as frequency references
UC Berkeley
Panasonic/IMEC
Q>200 000 @ 20 MHz
Walter Snoeys – PH ESE ME – 2011
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DISPLAYS, SENSORS and MEMS

14: Image sensors
14.3. Single
Photon Avalanche
Diode with no
afterpulses
(Toyota)



21: Thin Film transistors
31: PV (solar cells) and Energy Harvesting (vibration and
photovoltaic)
36: Biosensors and MEMS
Walter Snoeys – PH ESE ME – 2011
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CONCLUSIONS

CMOS : according to some (!)
 Bulk running out of steam (many tricks already done and
now DIBL)
 Ultra Thin Body and Buried oxide is good alternative for
some time to come

Lithography
 For 15 nm need advancement on EUV or need to work
with double pattern (in combination with computational
lithography). Ultimately a question of cost.

Special devices
 Intensive work to prepare improvement of MOS, some
things (Ge) already included

Metallization :
Walter Snoeys – PH ESE ME – 2011
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CONCLUSIONS

Metallization
 need reduced parasitics but porous low k is a challenge
 3D : Some nice examples but timeline for full production
not clear. Some alternatives using capacitive or inductive
coupling.

Memories
 DRAM and NAND in nonvolatile
 NAND multilevel and vertical structures
 Crosspoint memory: Phase Change Ram, ReRam,
STTRam as most likely successors

Displays, Sensors and MEMS
Walter Snoeys – PH ESE ME – 2011
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Intel: 22 nm in full production this summer
full RF implemented in 0.32 nm
1/f noise improves (Cox
dependence)
Walter Snoeys – PH ESE ME – 2011
85
Semiconductor
companies
Foundries
excluded
Significant growth
in 2010
Walter Snoeys
PH ESE ME – 2011
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Foundries: operating fabrication plants
Source: wikipedia
Walter Snoeys
PH ESE ME – 2011
87
More Moore and More Than Moore
Walter Snoeys – PH ESE ME – 2011
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THANK YOU
Walter Snoeys – PH ESE ME – 2011
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