Chapter 4
Field-Effect Transistors
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
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Chap4-1
Chapter Goals
• Describe operation of MOSFETs and JFETs.
• Define FET characteristics in operation regions of cutoff, triode and
saturation.
• Develop mathematical models for i-v characteristics of MOSFETs and
JFETs.
• Introduce graphical representations for output and transfer
characteristic descriptions of electron devices.
• Define and contrast characteristics of enhancement-mode and
depletion-mode FETs.
• Define symbols to represent FETs in circuit schematics.
• Investigate circuits that bias transistors into different operating regions.
• Learn basic structure and mask layout for MOS transistors and circuits.
• Explore MOS device scaling
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Chap1-2
Chapter Goals (contd.)
• Contrast 3 and 4 terminal device behavior.
• Descibe sources of capacitance in MOSFETs and JFETs.
• Explore FET modeling in SPICE.
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Chap1-3
Moore’s Law
Intel co-founder Gordon
Moore is a visionary. In
1965, his prediction,
popularly known as
Moore's Law, states that
the number of transistors on
a chip will double about
every two years.
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Moore’s Law (cont.)
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Moore’s Law (cont.)
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Moore’s Law (cont.)
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Moore’s Law (cont.)
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Moore’s Law (cont.)
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Transistor History
• Nobel prize for transistor (William Shockley) – link
• History of transistors - link
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Types of Field-Effect Transistors
• MOSFET (Metal-Oxide Semiconductor Field-Effect
Transistor)
– Primary component in high-density VLSI chips such as
memories and microprocessors
• JFET (Junction Field-Effect Transistor)
– Finds application especially in analog and RF circuit
design
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Chap1-11
MOS Capacitor Structure
• First electrode- Gate :
Consists of low-resistivity
material such as
polycrystalline silicon
• Second electrode- Substrate
or Body: n- or p-type
semiconductor
• Dielectric-Silicon
dioxide:stable high-quality
electrical insulator between
gate and substrate.
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Chap1-12
Substrate Conditions for Different Biases
• Accumulation
– VG<<VTN
• Depletion
– VG<VTN
• Inversion
– VG>VTN
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Chap1-13
Low-frequency C-V Characteristics for MOS
Capacitor on P-type Substrate
• MOS capacitance is nonlinear function of voltage.
• Total capacitance in any
region dictated by the
separation between capacitor
plates.
• Total capacitance modeled as
series combination of fixed
oxide capacitance and
voltage-dependent depletion
layer capacitance.
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Chap1-14
NMOS Transistor: Structure
• 4 device terminals:
Gate(G), Drain(D),
Source(S) and Body(B).
• Source and drain
regions form pn
junctions with substrate.
• vSB, vDS and vGS always
positive during normal
operation.
• vSB always < vDS and vGS
to reverse bias pn
junctions
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Chap1-15
NMOS Transistor: Qualitative I-V
Behavior
• VGS<<VTN : Only small leakage
current flows.
• VGS<VTN: Depletion region formed
under gate merges with source and
drain depletion regions. No current
flows between source and drain.
• VGS>VTN: Channel formed between
source and drain. If vDS>0,, finite iD
flows from drain to source.
• iB=0 and iG=0.
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Chap1-16
NMOS Transistor: Triode Region
Characteristics
for vGS VTN  vDS  0
where, Kn= Kn’W/L
iD 
Kn’=μnCox’’ (A/V2)
Cox’’=εox/Tox
εox=oxide permittivity
v 
i  Kn  v V  DS v
D
GS TN
2  DS
L 
(F/cm)
W 
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Tox=oxide thickness (cm)
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Chap1-17
NMOS Transistor: Triode Region
Characteristics (contd.)
• Output characteristics
appear to be linear.
• FET behaves like a
gate-source voltagecontrolled resistor
between source and
drain with
Ron 
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1
Kn 'W V V 
L  GS TN 
Chap1-18
MOSFET as Voltage-Controlled Resistor
Example 1: Voltage-Controlled Attenuator
vo
Ron
1


vs Ron  R 1 K RV

n  GG VTN 
If Kn=500μA/V2, VTN=1V, R=2kΩ and
VGG=1.5V, then,
vo
1

 0.667
vs
μA 
1 500
 2000 1.5 1V


2
V
To maintain triode region operation,
v  v V
or vo VGG VTN
DS GS TN
0.667v  (1.5 1)V
S
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or
v  0.750V
S
Chap1-19
MOSFET as Voltage-Controlled Resistor
(contd.)
Example 2: Voltage-Controlled High-Pass Filter
Vo s


T
s

 s s
Voltage Transfer function,
Vs s
o
where, cut-off frequency
o 
1
RonC

K n (V
V
)
TN
GS
C
If Kn=500μA/V2, VTN=1V, C=0.02μF and
VGG=1.5V, then,
μA 
1.5 1V

2
V
1.99kHz
2 (0.02μF)
500
fo 
To maintain triode region operation,
vs V
V  0.5V
GG TN
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Chap1-20
NMOS Transistor: Saturation Region
•
•
•
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If vDS increases above triode region limit,
channel region disappears, also said to be
pinched-off.
Current saturates at constant value,
independent of vDS.
Saturation region operation mostly used for
analog amplification.
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Chap1-21
NMOS Transistor: Saturation Region
(contd.)
i 
D
Kn W 
2 L


v V
GS TN
v
 v V
DSAT GS TN
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


2
for
v  v V
DS GS TN
is also called saturation or pinch-off
voltage
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Chap1-22
State of the Art – 32 nm
• Intel – power of smaller - link
• 32nm high k metal gate transistor - link
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Transconductance of a MOS Device
• Transconductance relates the change in drain current to a
change in gate-source voltage
di
gm  D
dv
GS Q pt
• Taking derivative of the expression for the drain current in
saturation region,
2I
W
D
gm  Kn ' (V V ) 
L GS TN V V
GS TN
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Chap1-24
Channel-Length Modulation
• As vDS increases above vDSAT,
length of depleted channel
beyond pinch-off point, DL,
increases and actual L decreases.
• iD increases slightly with vDS
instead of being constant.
i 
D
Kn W 
2 L


v V
GS TN



2
1 v


DS




 channel length modulation
parameter
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Chap1-25
Depletion-Mode MOSFETS
• NMOS transistors with VTN  0
• Ion implantation process used to form a built-in n-type
channel in device to connect source and drain by a resistive
channel
• Non-zero drain current for vGS=0, negative vGS required to
turn device off.
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Chap1-26
Transfer Characteristics of MOSFETS
• Plots drain current versus gate-source voltage for a fixed
drain-source voltage
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Chap1-27
Body Effect or Substrate Sensitivity
• Non-zero vSB changes threshold
voltage, causing substrate
sensitivity modeled by
V V  g  v  2  2 
TN TO  SB
F
F
where
VTO= zero substrate bias for VTN (V)
g body-effect parameter  V 
2FF= surface potential parameter (V)
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Chap1-28
Enhancement-Mode PMOS Transistors:
Structure
• P-type source and drain regions
in n-type substrate.
• vGS<0 required to create p-type
inversion layer in channel
region
• For current flow, vGS< vTP
• To maintain reverse bias on
source-substrate and drainsubstrate junctions, vSB <0 and
vDB <0
• Positive bulk-source potential
causes VTP to become more
negative
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Chap1-29
Enhancement-Mode PMOS Transistors:
Output Characteristics
• For VGS VTP , transistor is
off.
• For more negative vGS, drain
current increases in
magnitude.
• PMOS is in triode region for
small values of VDS and in
saturation for larger values.
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Chap1-30
MOSFET Circuit Symbols
• (g) and(i) are the
most commonly
used symbols in
VLSI logic design.
• MOS devices are
symmetric.
• In NMOS, n+
region at higher
voltage is the drain.
• In PMOS p+ region
at lower voltage is
the drain
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Chap1-31
40 years of Moore’s Law and CPU
•
•
•
•
The history of microprocessor- link
The history of intel CPU – link
What did you do 40 years ago? - link
45nm : biggest change to transistor in 40 years - link
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Process-defining Factors
• Minimum Feature Size, F : Width of smallest line or space that
can be reliably transferred to wafer surface using given generation
of lithographic manufacturing tools
• Alignment Tolerance, T: Maximum misalignment that can occur
between two mask levels during fabrication
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Chap1-33
Mask Sequence for a Polysilicon-Gate
Transistor
• Mask 1: Defines active area or thin
oxide region of transistor
• Mask 2: Defines polysilicon gate
of transistor, aligns to mask 1
• Mask 3: Delineates the contact
window, aligns to mask 2.
• Mask 4: Delineates the metal
pattern, aligns to mask 3.
• Channel region of transistor
formed by intersection of first two
mask layers. Source and Drain
regions formed wherever mask 1 is
not covered by mask 2
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Chap1-34
Basic Ground Rules for Layout
• F=2Λ
• T=F/2=L, L
could be 1, 0.5,
0.25 mm, etc.
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Chap1-35
Internal Capacitances in Electronic
Devices
• Limit high-frequency performance of the electronic device
they are associated with.
• Limit switching speed of circuits in logic applications
• Limit frequency at which useful amplification can be
obtained in amplifiers.
• MOSFET capacitances depend on operation region and are
non-linear functions of voltages at device terminals.
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Chap1-36
NMOS Transistor Capacitances: Triode
Region
C
C  GC  C
W  Cox"WL  C
W
GS
GSO
GSO
2
2
C
C
 GC  C
W  Cox"WL  C
W
GD
GSO
GSO
2
2
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Cox” =Gate-channel
capacitance per unit
area(F/m2).
CGC =Total gate channel
capacitance.
CGS = Gate-source
capacitance.
CGD =Gate-drain
capacitance.
CGSO and CGDO = overlap
capacitances (F/m).
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Chap1-37
NMOS Transistor Capacitances: Triode
Region (contd.)
CSB CJ AS CJSW PS
C
C A C
P
DB J D JSW D
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CSB = Source-bulk capacitance.
CDB = Drain-bulk capacitance.
AS and AD = Junction bottom area
capacitance of the source and
drain regions.
PS and PD = Perimeter of the
source and drain junction
regions.
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Chap1-38
NMOS Transistor Capacitances:
Saturation Region
• Drain no longer connected to channel
C  2C
C
W
GS 3 GC GSO
C
C
W
GD GDO
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Chap1-39
NMOS Transistor Capacitances: Cutoff
Region
• Conducting channel
region completely
gone.
C C
W
GS GSO
C
C
W
GD GDO
C C
W
GB GBO
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CGB = Gate-bulk
capacitance
CGBO = gate-bulk
capacitance per unit
width.
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Chap1-40
SPICE Model for NMOS Transistor
Typical default values used by SPICE:
Kn or Kp = 20 mA/V2
g=0
=0
VTO = 1 V
mn or mp = 600 cm2/V.s
2FF = 0.6 V
CGDO=CGSO=CGBO=CJSW= 0
Tox= 100 nm
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Chap1-41
Bias Analysis Approach
• Assume an operation region (generally the saturation
region)
• Use circuit analysis to find VGS
• Use VGS to calculate ID, and ID to find VDS
• Check validity of operation region assumptions
• Change assumptions and analyze again if required.
NOTE :An enhancement-mode device with VDS = VGS is
always in saturation
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Chap1-42
Constant Gate-Source MOSFET Bias Circuit
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Simplified MOSFET Bias Circuit
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Loadline Analysis
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Four-Resistor and Two-Resistor Biasing
• Provide excellent bias for transistors in discrete circuits.
• Stabilize bias point with respect to device parameter and
temperature variations using negative feedback.
• Use single voltage source to supply both gate-bias voltage
and drain current.
• Generally used to bias transistors in saturation region.
• Two-resistor biasing uses lesser components that fourresistor biasing and also isolates drain and gate terminals
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Chap1-46
Bias Analysis: Example 1 (Four-Resistor
Biasing)
Assumption: Transistor is saturated,
IG=IB=0
Analysis: First, simplify circuit, split
VDD into two equal-valued sources and
apply Thevenin transformation to find
VEQ and REQ for gate-bias voltage
Problem: Find Q-pt (ID, VDS)
Approach: Assume operation
region, find Q-point, check to see if
result is consistent with operation
region
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Chap1-47
Bias Analysis: Example 1 (Four-Resistor
Biasing) (contd.)
V 2  0.05V  7.21  0
GS
GS
V  2.71V,2.66V
GS
Since VGS<VTN for VGS= -2.71 V
and MOSFET will be cut-off,
Since IG=0,
V
EQ
V  I R
GS D S
Kn R 
2
S V V 
V
V 


EQ GS
2  GS TN 



 25 10 6  3.9 104 

4 V  
GS
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

2
V  2.66V and ID= 34.4 mA
GS
Also, VDD  I D ( RD  RS ) VDS

 V

 GS
V
1

2
DS
 6.08V
VDS>VGS-VTN. Hence
saturation region assumption is
correct.
Q-pt: (34.4 mA, 6.08 V) with
VGS= 2.66 V
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Chap1-48
Bias Analysis: Example 2 (Four-Resistor
Biasing)
Analysis with body effect using
same assumptions as in example 1:
V V
 I R  6 22,000I
D
GS
EQ D S
V  I R  22,000I
D
SB D S
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V V  g ( V  2  2 )
TN TO
F
F
SB
V  1 0.5( V  0.6  0.6 )
TN
SB


 25 10 6 
2



 V

I ' 

V

D
TN 
 GS
2
Iterative solution can be found by
following steps:
• Estimate value of ID and use it
to find VGS and VSB
• Use VSB to calculate VTN
• Find ID’ using above 2 steps
• If ID’ is not same as original ID
estimate, start again.
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Chap1-49
Bias Analysis: Example 2 (Four-Resistor
Biasing) (contd.)
The iteration sequence leads to ID= 88.0 mA
V
DS
V
DD
 I ( R  R )  10  40,000I  6.48V
D D S
D
VDS>VGS-VTN. Hence saturation region assumption is correct.
Q-pt: (88.0 mA, 6.48 V)
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Chap1-50
R
R
D
EQ
G
60 k 
DS
+
S
-
+
S
V
GS
EQ
4V
IG
R
39 k 
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+
V
V
V
75 k 
D
S
-
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IDS
VDD
10 V
Four Transistor Bias Summary
VEQ = VGS + IDS RS
(4.48)
VDD = IDS RD + VDS + IDS RS (4.50)
IDS   VGS   IDS 
VDS   IDS   VGS   IDS   VDS 
Assume that the transistor is operating in the saturation
region with
IDS = Kn/2 (VGS – VTN)2
(4.47)
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VEQ=VGS+ RsKn/2 (VGS – VTN)2 (4.49)
Solve VGS and check to make sure transistor is not cutoff.
Use (4.53) to compute IDS, (4.52) to get VDS
Verify that transistor is in saturation mode because VDS ≥
VGS-VTN
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Bias Analysis: Example 3 (Two-Resistor
Biasing)
Kn R 
2
D V V 
V V



GS DD
2  GS TN 



 2.6 10  4 104 
V
GS

 3.3  


2

 V

 GS
1

V  0.769V,2.00V
GS
Since VGS<VTN for VGS= -0.769 V
and MOSFET will be cut-off,
Assumption: IG=IB=0, transistor is
saturated (since VDS= VGS)
Analysis:
V
DS
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V
DD
I R
D D
V  2.00V and ID= 130 mA
GS
VDS>VGS-VTN. Hence saturation
region assumption is correct.
Q-pt: (130 mA, 2.00 V)
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Chap1-54
2
Bias Analysis: Example 4 ( Biasing in
Triode Region)
Also
 I ( R ) V
DD D D
DS
4  1600 I V
D DS
V
 2.19V
DS
V
But VDS<VGS-VTN. Hence, saturation
region assumption is incorrect
Using triode region equation,
Assumption: IG=IB=0, transistor
is saturated (since VDS= VGS)
Analysis: VGS=VDD=4 V
V
DS
 2.3V and ID=1.06 mA
VDS<VGS-VTN, transistor is in triode region
I  250 μA (4 1)2  1.13mA
D 2 V2
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V
μA
250
4 V
 1600
(4 1 DS )V
DS
DS
2 V2
2
Q-pt:(1.06 mA, 2.3 V)
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Chap1-55
Bias Analysis: Example 5 (Two-Resistor
biasing for PMOS Transistor)
Also 15V  (220kΩ) I D VDS  0
2
15V  (220kΩ) 50 μA V  2  V  0
GS
2 V2  GS 
V  0.369V,3.45V
GS
Since VGS= -0.369 V is less than VTP= -2
V, VGS = -3.45 V
Assumption: IG=IB=0, transistor
is saturated (since VDS= VGS)
Analysis:
V  (470kΩ) I V
0
GS
G DS
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7/1/03
ID = 52.5 mA and VGS = -3.45 V
V
DS
V
GS
V
TP
Hence saturation assumption is correct.
Q-pt: (52.5 mA, -3.45 V)
Microelectronic Circuit Design
McGraw-Hill
Chap1-56
Feedback Analysis
• Negative Feedback is used to stabilize the operating point.
• ID   -VDS   -VGS   ID 
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MOSFET as Current Source
• Ideal current source
gives fixed output
current regardless of
voltage across it.
• MOSFET behaves as
as an ideal current
source if biased in the
pinch-off region
(output current
depends on terminal
voltage).
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Microelectronic Circuit Design
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Chap1-58
NMOS Current Mirror
K W
2


I
 n V
V  1 V

REF
TN  
 GS1
DS1

2 L
K W
2


I  n V
V  1 V

TN  
O
 GS2
DS2

2 L
But VGS2=VGS1
Assumption: M1 and M2
have identical VTN, Kn’, 
and W/L and are in
saturation.
Jaeger/Blalock
7/1/03
1 V


DS2
I  I
I
REF
O REF
1


V
 DS1
Thus, output current mirrors reference
current if VDS1=VDS2.
Microelectronic Circuit Design
McGraw-Hill
Chap1-59
NMOS Current Mirror: Example
Given data: IREF= 50 mA, VO= 12 V, VTN= 1 V, Kn= 150 mA/V2, =
0.0133 V-1
Determine: VGS, VDS1, IO
2I
Analysis:
REF
V
DS1
V 1 V 
TN
GS
Kn (1 V
)
DS1
2(50μA)
Using trial-and-error, VDS1  1V 
μA
0.0133
150
(1
V
)
DS1
V2
V
Hence, VDS1 =1.81 V. Also, VDS2=12 V


1  0.0133 (12V) 


V


I  (50μA)
 56.6μA
O


1  0.0133 (1.81V) 


V


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Chap1-60
MOS Current Mirror Ratio
1 V



W / L2 1 VDS2 
DS2
I I
 5I
O REF W / L
1 1 V
 REF 1 V 
DS1
DS1
I  5I
REF
O


 Kn ' W   2Kn '
n1
 L 1


K  Kn '  W   10Kn '
n2
 L 2
K
Jaeger/Blalock
7/1/03
Thus, ratio between IO and IREF can
be modified by changing W/L ratios
of the current mirror transistors
(ignoring differences due to VDS
mismatch)
Microelectronic Circuit Design
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Chap1-61
MOS Current Mirror Output Resistance
• Output current changes with vDS due to channel length
modulation.
• Output resistance is given by 1








i

R  O

O v
O Q pt 
• In the current mirror, vO = vDS2
Kn W 
2

1 v 
 v
i 
V
O
GS2 TN 
O 
2 L



 1 1 V
I

O 1
R   O  
O
1 V 
I
I
O
O
O





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Chap1-62
Current Mirror Layout
Two possible layouts of a current mirror
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Chap1-63
Design of Multiple Current Mirrors:
Example
I
I
I
D2
D3
D5
I
W / L2  50μA
REF W / L1
I
I
W / L3  125μA
REF W / L1
W / L5  25μA
REF W / L4
Choose R to set IREF= 25 mA
10 V
V
GSP
GSN
R
I
REF
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Chap1-64
Design of Multiple Current Mirrors
(contd).
2I
D  1.71V
V
V 
GSP TP
Kp
and
V
V 
GSN TN
2I
D  1.45V
Kn
V
R  10 1.71  1.45
 274kΩ
25
μA
R can be replaced by transistor M6 for better integration.
We know that VGS6 = -6.84 V and ID = 25 mA and M6 is
in saturation
I
D

2
K p '  W 


V

V
2  L  GS TP 


1
W  
 L  13.6
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Chap1-65
MOS Transistor Scaling
• Drain current:


Kn*  mn ox W /  mn ox W  Kn
Tox L
Tox / L /
v
v
v
v
i


 DS
W
/

GS
TN
DS
ox
D
*
i  mn






D
Tox / L /  

2 
• Gate Capacitance:
ox W / CGC
*
*
*
*
C
 (Cox") W L 

GC
Tox / L /

* C
D
V
DV /  t
t* C *
 GC
 i / 
GC i *
D
D
wheret is the circuit delay in a logic circuit.
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Chap1-66
MOS Transistor Scaling (contd.)
• Circuit and Power Densities:
V
i
*i *  DD D  P
 
DD D
2
P*
P*
P / 2
P
P




A* W *L* (W / )( L / ) W L A
P* V
• Power-Delay Product:
t  PDP
PDP*  P*t *  P 
2
3
• Cutoff Frequency:
g
f  1 m  1
T 2 C
2
GC
mn 
V V 
L2 GS TN 


fT improves with square of channel length reduction
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Chap1-67
MOS Transistor Scaling (contd.)
• High Field Limitations:
– High electric fields arise if technology is scaled down
with supply voltage constant.
– Cause reduction in mobility of MOS transistor,
breakdown of linear relationship between mobility and
electric field and carrier velocity saturation.
– Ultimately results in reduced long-term reliability and
breakdown of gate oxide or pn junction.
– Drain current in saturation region is linearised to
C "W
i  ox (v  v )v
D
GS TN SAT
2
Jaeger/Blalock
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where, vSAT is carrier
saturation velocity
Microelectronic Circuit Design
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Chap1-68
MOS Transistor Scaling (contd.)
• Sub-threshold Conduction:
– ID decreases exponentially for
VGS<VTN.
– Reciprocal of the slope in
mV/decade gives the turn off
rate for the MOSFET.
– VTN should be reduced if
dimensions are scaled down,
but curve in sub-threshold
region shifts horizontally
instead of scaling with VTN..
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Chap1-69
MOS Scaling
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SIA MOS Technology Roadmap
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Worldwide Semiconductor Sales Trend
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Technology Cross-over
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Linear Technology Shrink
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MOS Technology Scaling Ratio
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Linear Shrink
• Cost Per Function : 40% reduction
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Re-Design Scale Factors
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Intel CPU Scaling
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Wafer Diameter Increase
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Dies on a Wafer
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Gross Die Per Wafer
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Gate Cost
• Die Size too small – I/O overhead
• Die Size too big - Complexity
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Gate Cost
• Pentium 4 has 14M Gates – Near Optimum
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Junction Field-Effect Transistor (JFET)
Structure
• Much lower input current and
much higher input impedance than
BJT.
• In triode region, JFET is a voltagecontrolled resistor,
R
r L
CH
tW
r = resistivity of channel
• N-type semiconductor block that
houses the channel region in nchannel JFET.
• Two pn junctions to form the gate.
• Current enters channel at drain
and exits at source.
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L = channel length
W = channel width between pn
junction depletion regions
t = channel depth
• Inherently a depletion-mode device
Microelectronic Circuit Design
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Chap1-98
JFET with Gate-Source Bias
• vGS =0, gate isolated from channel.
• VP < vGS <0, W’<W, channel
resistance increases, gate-source
junction reverse-biased, iG almost 0.
• vGS = VP <0, channel region pinchedoff, channel resistance infinite.
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Chap1-99
JFET Channel with Drain-Source Bias
• With constant vGS, depletion region
near drain increases with vDS.
• At vDSP = vGS - VP,channel is totally
pinched-off, iD is saturated.
• JFET also suffers from channel
length modulation like MOSFET at
larger values of vDS.
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Chap1-100
N-Channel JFET: i-v Characteristics
Transfer Characteristics
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Output Characteristics
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Chap1-101
N-Channel JFET: i-v Characteristics
(contd.)
• For all regions : iG=0 for vGS  0
• In cutoff region: iD =0 for vGS VP (VP <0).
• In Triode region:
2I
v





i  DSS v V  DS
D V 2 GS P
2
P





2
v
DS
for vGS VP and vGS VP  vDS  0
• In pinch-off region:







v
i I
1 GS
D DSS
V
P
Jaeger/Blalock
7/1/03
2











1 v




v  v V  0
DS for DS GS P
Microelectronic Circuit Design
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Chap1-102
P-Channel JFET
• Polarities of n- and p-type regions of n-channel JFET
are reversed to get the p-Channel JFET.
• Channel current direction and operating bias voltages
are also reversed.
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Chap1-103
JFET Circuit Symbols
• JFET structures are symmetric like MOSFET.
• Source and drain determined by circuit voltages.
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Chap1-104
JFET Capacitances and SPICE Modeling
• CGD and CGS are determined by depletionlayer capacitances of reverse-biased pn
junctions forming gate and are bias
dependent.
• Typical default values used by SPICE:
Vp = -2 V
 = CGD = CGD =0
Transconductance parameter= BETA
=IDSS/VP2= 100 mA/V2
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Chap1-105
Biasing JFET and Depletion-Mode
MOSFET: Example
N-channel JFET
Depletion-mode MOSFET
• Assumptions: JFET is pinched-off, gate-channel junction is reverse-biased,
reverse leakage current of gate, IG = 0
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Chap1-106
Biasing JFET and Depletion-Mode
MOSFET: Example (contd.)
• Analysis: Since IS = ID , VGS   I D RS
V
GS

V

 I
R 1 GS
DSS S
V

P

2






2

V 




3
  510 A  1000 1 GS 



 5V 



V  1.91V,13.1V
GS
Since VGS= -13.1 V is less than VP= -5 V, VGS = -1.91 V and, ID = IS =
1.91 mA. Also,
V
DS
V
DD
 I ( R  R )  12  (1.91mA)(3kΩ)  6.27V
D D S
VDS>VGS-VP. Hence pinch-off region assumption is correct and gatesource junction is reverse-biased by 1.91V.
Q-pt: (1.91 mA, 6.27 V)
Jaeger/Blalock
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Chap1-107
Homework
•
•
•
•
•
4.22
4.81
4.85(a)
4.103(b)
4.145
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