Chapter 10
Analog Systems
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap10 - 1
Chapter Goals
• Develop understanding of linear amplification concepts such as:
–
–
–
–
–
–
–
–
–
–
–
Voltage gain, current gain, and power gain,
Gain conversion to decibel representation,
Input and output resistances,
Transfer functions and Bode plots,
Cutoff frequencies and bandwidth,
Low-pass, high-pass, band-pass, and band-reject amplifiers,
Biasing for linear amplification,
Distortion in amplifiers,
Two-port representations of amplifiers,
g-, h-, y-, and z-parameters,
Use of transfer function analysis in SPICE.
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
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Chap10 - 2
Example of Analog Electronic System:
FM Stereo Receiver
• Linear functions: Radio and audio frequency amplification, frequency
selection (tuning), impedance matching(75-W input, tailoring audio
frequency response, local oscillator
• Nonlinear functions: DC power supply(rectification), frequency
conversion (mixing), detection/demodulation
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
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Chap10 - 3
Amplification: Introduction
A complex periodic signal can be represented as the sum of many
individual sine waves. We consider only one component with
amplitude VS =1 mV and frequency wS with 0 phase (signal is used
as reference):
v V sin w t
s
s
s
Amplifier output is sinusoidal with same frequency but different
amplitude VO and phase θ:
vo Vo (sin wst  )
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
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Chap10 - 4
Amplification: Introduction (contd.)
Vo 2 1
Amplifier output power is: Po 

2  R
L
Here, PO = 100 W and RL=8 W Vo  2PoRL  2 1008  40V





Output power also requires output current which is:
io  Io (sin wst  )
V
Io  o  40V  5A
R
8W
L
Input current is given by
Is 
-3
Vs
 10 V 1.8210 8A
Rs  R
in 5kW  50kW
phase is zero because circuit is purely resistive.
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap10 - 5
Amplification: Gain
• Voltage Gain:
v V  Vo
Av  vo  o
 
Vs
V

0
s
s
Magnitude and phase of voltage gain are given by
V
Av  o and Av  
Vs
Vo 40V
A

For our example, v V   3  4 104
s 10 V
• Current Gain: A  io  Io  Io 
i is I s0 I s
Magnitude of current gain is given by
I
5A
A  o
 2.75108
i I s 1.8210-8A
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap10 - 6
Amplification: Gain (contd.)
• Power Gain:
Vo
P
A  o 2
P Ps V
s
2
For our example,
A 
P
Io
2  Vo Io  A A
v i
Is V I
s s
2
405
10 3 1.8210 8
1.101013
On decibel scale, i.e. in dB APdB 10log AP
A
 20log Av
vdB
A  20log A
idB
i
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap10 - 7
Amplifier Biasing for Linear Operation
v V  v
I I i
VI = dc value of vI,
vi = time-varying component
For linear amplification- vI must be biased in desired region of output
characteristic by VI.
v V  vo
O O
If slope of output characteristic is positive, input and output are in
phase (amplifier is non-inverting).
If slope of output characteristic is negative, input and output signals
are 1800 out of phase (amplifier is inverting).
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap10 - 8
Amplifier Biasing for Linear Operation
(contd.)
Av 
vo
v
I v V
I
I
Voltage gain depends on bias
point.
Eg: if amplifier is biased at VI =
0.5 V, voltage gain will be +40
for input signals satisfying
v  0.1V If input exceeds this
i
value, output is distorted due to
change in amplifier slope.
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap10 - 9
Amplifier Biasing for Linear Operation
(contd.)
Output signals for 1 kHZ sinusoidal
input signal of amplitude 50 mV
biased at VI= 0.3 V and 0.5V:
For VI =0.3V:
v  (0.3 0.05sin 2000t)V
IA
v  (4 1sin 2000t)V
OA
Gain is 20, output varies
about dc level of 4 V.
For VI =0.5V:
v  (0.5  0.05sin 2000t)V
IB
v  (10  2sin 2000t)V
OB
Gain is 40, output varies
about dc level of 10 V.
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap10 - 10
Distortion in Amplifiers
• Different gains for positive and negative values of input cause
distortion in output.
• Total Harmonic Distortion (THD) is a measure of signal distortion
that compares undesired harmonic content of a signal to the desired
component.
Jaeger/Blalock
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Microelectronic Circuit Design
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Chap10 - 11
Total Harmonic Distortion
v(t) Vo V (sinwot  ) V (2sinwot  ) V (3sinwot  )  ...
1
1
2
2
3
3
dc
desired
2nd harmonic 3rd harmonic
output
distortion
distortion

2
Vn
THD  100% 
2
V
1
Numerator= sum of rms amplitudes of distortion terms,
Denominator= desired component
Jaeger/Blalock
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Chap10 - 12
Two-port Models for Amplifiers
• Simplifies amplifier-behavior modeling in complex systems.
• Two-port models are linear network models, valid only under
small-signal conditions.
• Represented by g-, h-, y- and z-parameters.
• (v1, i1) and (v2, i2) represent signal components of voltages and
currents at the network ports.
Jaeger/Blalock
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Chap10 - 13
g-parameters
i g v g i
1 11 1 12 2
v g v g i
2 21 1 22 2
Jaeger/Blalock
7/1/03
Using open-circuit (i=0) and shortcircuit (v=0) termination
conditions,
i
Open-circuit input
g  v1
11 1
i 0 conductance
2
i
Reverse short-circuit
g  1
12 i
2 v 0 current gain
1
v
Forward open-circuit
g  v2
21 1
i 0 voltage gain
2
v
g  2
Short-circuit output
22 i
2 v 0 resistance
1
Microelectronic Circuit Design
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Chap10 - 14
g-parameters:Example
i
g  v1
11 1
Problem:Find g-parameters.
Approach: Apply specified boundary
conditions for each g-parameter, use
circuit analysis.
For g11 and g21: apply voltage v1 to
input port and open circuit output port.
For g12 and g22: apply current i2 to
output port and short circuit input port.
Jaeger/Blalock
7/1/03

1
4
i 0 2 10 W  51(200kW)
2
 9.7910 8S
v
g  v2
 g (51)(200kW)  0.998
21 1
11
i 0
2
i
1
g  1

 391W
12 i
1
51

2 v 0
1
200kW 20kW
v
391W
g  2

 0.0196
22 i
20kW
2 v 0
1
i  9.7910 8v 1.9610 2i
1
1
2
v  0.998v  3.91102i
2
1
2
Microelectronic Circuit Design
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Chap10 - 15
Hybrid or h-parameters
v h i h v
1 11 1 12 2
i h i h v
2 21 1 22 2
Jaeger/Blalock
7/1/03
Using open-circuit (i=0) and shortcircuit (v=0) termination
conditions,
v
Short-circuit input
h  1
11 i
1 v 0 resistance
2
v
h  v1
Reverse open-circuit
12 2
i 0 voltage gain
1
i
h  2
21 i
1 v 0
2
i
h  v2
22 2
i 0
1
Microelectronic Circuit Design
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Forward short-circuit
current gain
Open-circuit output
conductance
Chap10 - 16
h-parameters:Example
Problem:Find h-parameters for the
same network (used in g-parameters
example).
Approach: Apply specified boundary
conditions for each h-parameter, use
circuit analysis.
For h11 and h21: apply current i1 to input
port and short circuit output port.
For h12 and h22: apply voltage v2 to
output port and open circuit input port.
v
h  1
 2 104W
11 i
1 v 0
2
i
h  2
 51
21 i
1 v 0
2
v
h  v1
1
12 2
i 0
1
i
1
h  v2

 510 6S
22 2
i 0 200kW
1
v  2 104i  v
1
1 2
i  51i  510 6 v
2
1
2
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Chap10 - 17
Admittance or y-parameters
i y v y v
1 11 1 12 2
i y v y v
2 21 1 22 2
Jaeger/Blalock
7/1/03
Using open-circuit (i=0) and shortcircuit (v=0) termination
conditions,
i
y  v1
Short-circuit input
11 1
v 0 conductance
2
i
y  v1
Reverse short-circuit
12 2
v 0 transconductance
1
i
Forward short-circuit
y  v2
21 1
v 0 transconductance
2
i
Short-circuit output
y  v2
22 2
v 0 conductance
1
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Chap10 - 18
y-parameters:Example
i
1
y  v1

 510 5S
11 1
v 0 20kW
2
i
51
y  v2

 2.5510 3S
21 1
20kW
v 0
2
i
1
y  v1

 510 5S
12 2
20kW
v 0
For y11 and y21: apply voltage v1 to input
1
port and short circuit output port.
i
1
 3S
1
y



2
.
56

10
For y12 and y22: apply voltage v2 to
22 v2
i 0 391W
output port and short circuit input port.
1
Problem:Find y-parameters for the
same network (used in g-parameters
example).
Approach: Apply specified boundary
conditions for each y-parameter, use
circuit analysis.
i  510 5v  510 5v
1
1
2
i  2.5510 3v  2.5610 3v
2
1
2
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Chap10 - 19
Impedance or z-parameters
v z i z i
1 11 1 12 2
v z i z i
2 21 1 22 2
Jaeger/Blalock
7/1/03
Using open-circuit (i=0) and shortcircuit (v=0) termination
conditions,
v
z  1
Open-circuit input
11 i
1 i 0 resistance
2
v
z  1
Reverse open-circuit
12 i
2 i 0 transresistance
1
v
Forward open-circuit
z  2
21 i
1 i 0 transresistance
2
v
Open-circuit output
z  2
22 i
2 i 0 resistance
1
Microelectronic Circuit Design
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Chap10 - 20
z-parameters:Example
Problem:Find z-parameters for the
same network (used in g-parameters
example).
Approach: Apply specified
boundary conditions for each zparameter, use circuit analysis.
For z11 and z21: apply current i1 to
input port and open circuit output
port. For z12 and z22: apply current i2
to output port and open circuit input
port.
Jaeger/Blalock
7/1/03
v
z  1
 20kW  51(200kW)  10.2MW
11 i
1 i 0
2
v
z  2
 10.2MW
21 i
1 i 0
2
v
z  1
 200kW
12 i
2 i 0
1
v
z  2
 200kW
22 i
2 i 0
1
v  1.02107i  2.00105i
1
1
2
v  1.02107i  2.00105i
2
1
2
Microelectronic Circuit Design
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Chap10 - 21
Mismatched Source and Load
Resistances: Voltage Amplifier
g-parameter representation (g12=0) with Thevenin equivalent of input source:
If Rin >> Rs and Rout<< RL,
Av  A
R
L
vo Av
1R
R
out
L
R
in
v  vs
1
Rs  R
in
R
R
Vo
in
L
 Av   A
Vs
Rs  R R
R
in out
L
Jaeger/Blalock
7/1/03
In an ideal voltage amplifier, Rin  
and Rout =0
Vo
Io
A  
i I
1
R
L
Vs
Rs  R
in
Rs  R
in
 A  Av
R
i
L
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Vo Rs  Rin

Vs R
L
Chap10 - 22
Mismatched Source and Load
Resistances: Current Amplifier
h-parameter representation (h12=0) with Norton equivalent of input source:
If Rs >> Rin and Rout>> RL,
R
out
io   i
1R
R
out
L
Rs
i  is
1
Rs  R
in
R
Io
Rs
out
A   
i I
Rs  R R
R
s
in out
L
Jaeger/Blalock
7/1/03
A 
i
In an ideal current amplifier, Rout  
and Rin=0
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Chap10 - 23
Amplifier Transfer Functions
Vo  s
Av s 
Vs  s
Av(s)=Frequency-dependent voltage gain
Vo(s) and Vs(s) = Laplace Transforms of input and output voltages of
amplifier, s    jw
s  z s  z ...s  zm 
1
2
Av s  K
(In factorized form)
s  p s  p ... s  p
1
2
3
(-z1, -z2,…-zm)=zeros (frequencies for which transfer function is zero)
(-p1, -p2,…-pm)=poles (frequencies for which transfer function is infinite)
  
   
Av  jw   Av  jw Av  jw 

(In polar form)
Bode plots display magnitude of the transfer function in dB and the
phase in degrees (or radians) on a logarithmic frequency scale..
Jaeger/Blalock
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Chap10 - 24
Low-pass Amplifier: Description
• Amplifies signals over a range of frequencies including dc.
• Most operational amplifiers are designed as low pass amplifiers.
• Simplest (single-pole) low-pass amplifier is described by
Aow
Ao
H
Av s  

s
s w
1
H
w
H
Ao = low-frequency gain or mid-band gain
wH = upper cutoff frequency or upper half-power point of amplifier.
Jaeger/Blalock
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Chap10 - 25
Low-pass Amplifier: Magnitude Response
Aow
Aow
H
H
Av  jw  

jw  w
w 2 w 2
H
H
Av  jw   20log Aow  20log w 2  w 2
H
H
dB
For w<<wH :
Av  jw   Ao  (20log Ao)dB
For w>>wH :




Aow
w


H
Av  jw  
  20log Ao  20log
dB

w
w 


H

For wwH :
A
Av  jw   o   (20log Ao )  3dB
2
• Gain is unity (0 dB) at wAowH , called gain-bandwidth product
• Bandwidth (frequency range with constant amplification )= wH (rad/s)
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Chap10 - 26
Low-pass Amplifier: Phase Response


Ao
 w 

1
Av  jw   
 Ao  tan  w 
w


1 j
 H 
w
H
If Ao positive: phase angle = 00
If Ao negative: phase angle = 1800
At wC: phase =450
One decade below wC: phase =5.70
One decade above wC: phase =84.30
Two decades below wC: phase =00
Two decades above wC: phase =900
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Chap10 - 27
RC Low-pass Filter
R / sC
2
R 1/ sC
2
Vo Vs
R / sC
R  2
1 R 1/ sC
2
Problem: Find voltage transfer
function
Approach: Impedance of the
capacitor is 1/sC, use voltage
division
Jaeger/Blalock
7/1/03












Vo  R2
1
 
Vs  R  R 1 s
2
 1
w
H
where w
Microelectronic Circuit Design
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H











1





R R C
1 2
Chap10 - 28
High-pass Amplifier: Description
• True high-pass characteristic impossible to obtain as it requires
infinite bandwidth.
• Combines a single pole with a zero at origin.
• Simplest high-pass amplifier is described by
Av s  
Ao s
s w
L
wH = lower cutoff frequency or lower half-power point of amplifier.
Jaeger/Blalock
7/1/03
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Chap10 - 29
High-pass Amplifier: Magnitude and
Phase Response
A jw
Aow
Av  jw   o

jw  w
w 2 w 2
L
L
For w>>wL :
Av  jw   Ao  (20log Ao)dB
For w<<wL :



Aow 
w

Av  jw  
  20log Ao  20log
dB

w
w 
L 
L
For wwL :
•
•
A
Av  jw   o   (20log Ao )  3dB
2
Bandwidth (frequency range with constant amplification ) is infinite
Phase response is given by A  jw    Ao jw  A  900  tan1 w 
v
o
w 
jw  jw
 L
L
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Chap10 - 30
RC High-pass Filter
Problem: Find voltage transfer
function
Approach: Impedance of the
capacitor is 1/sC, use voltage
division
Jaeger/Blalock
7/1/03
R
2
Vo Vs
1
R 
R
1 sC
2



Vo  R2  s 
 


Vs  R  R  s  w 
L
2 
 1
1
where w 
L  R  R C

2 
 1
Microelectronic Circuit Design
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Chap10 - 31
Band-pass Amplifier: Description
• Band-pass characteristic obtained by combining highpass and
low-pass characteristics.
• Transfer function of a band-pass amplifier is given by
Ao sw
s
1
H
Av s  
 Ao

(s  w )  s

(s  w )(s  w )
L

1


L
H
w

 H

• Ac-coupled amplifier has a band-pass characteristic:
– Capacitors added to circuit cause low frequency roll-off
– Inherent frequency limitations of solid-state devices cause
high-frequency roll-off.
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
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Chap10 - 32
Band-pass Amplifier: Magnitude and
Phase Response
• The frequency response shows a wide band of operation.
• Mid-band range of frequencies given by w  w  w , where Av ( jw )  Ao
L
H
Ao jww
Aoww
H
H
Av  jw  

( jw  w )( jw  w )
(w 2  w 2 )(w 2  w 2 )
L
H
L
H
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap10 - 33
Band-pass Amplifier: Magnitude and
Phase Response (contd.)
At both wH and wL, assuming wL<<wH,
 


A
Av jw  Av jw  o   (20log Ao )  3dB
L
H
2
Bandwidth = wH - wL.
The phase response is given by




Ao jw
 w 
 w 
0

1

1
Av  jw   
 Ao  90  tan  w   tan  w 




jw  jw
 L
 H 
L
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap10 - 34
Narrow-band or High-Q Band-pass
Amplifiers
• Gain maximum at center frequency wo and
decreases rapidly by 3 dB at wH and wL.
• Bandwidth defined as wH - wL, is a small
fraction of wo with width determined by:
wo
fo
f
Q

 o
w w
f f
BW
H
L
H L
• For high Q, poles will be complex and
wo
s
Q
Av s   Ao
wo
2
s  s  wo2
Q
• Phase response is given by:


1
ww
o 
Av  jw   Ao  900  tan1
Q

wo2 w 2 

Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap10 - 35
Band-Rejection Amplifier or Notch
Filter
• Gain maximum at frequencies far from wo
and exhibits a sharp null at wo.
• To achieve sharp null, transfer function has
a pair of zeros on jw axis at notch frequency
wo , and poles are complex.
s2  wo2
Av s  Ao
w
s2  s o  wo2
Q
• Phase response is given by:




wwo 
Av  jw   Ao   wo2 w 2   tan1 1
Q

wo2 w 2 






Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap10 - 36
All-pass Function
• Uniform magnitude response at all frequencies.
• Can be used to tailor phase characteristics of a signal
• Transfer function is given by:
s  wo
Av s   Ao
s  wo
• For positive Ao,
Av  jw   Ao


Av  jw   2 tan1 ww 
 o
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap10 - 37
Complex Transfer Functions




Ks s  w
  




2




 s  w  s  w  s  w   s  w 

5 
1 
3 
4 

A
s s  w 
2
mid 
Av s  





















Amplifier has 2 frequency ranges with
constant gain. Midband region is
always defined as region of highest
gain and cutoff frequencies are
defined in terms of midband gain.
A
Av jw  Av jw  mid
L
H
2








Since wH = w4 and wL = w3,
w w
BW  f  f  4 3
4 3
2
s
s
s  w  s  w
1
1
1 
3 w
w
5
4
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chap10 - 38
Bandwidth Shrinkage
• If critical frequencies aren’t widely spaced, the poles and zeros
interact and cutoff frequency determination becomes
complicated.
Aow 2 for which , A (0) = A
• Example :
v
o
1
Av s  
(s  w )2
1

Upper cutoff frequency is defined by A jw
v

A
 o or
H
2
Ao








w 
1 wH 
1 
Solving for wH yields wH =0.644w1.The cutoff frequency of
two-pole function is only 64% that of a single-pole function.
This is known as bandwidth shrinkage.
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill





 Ao
2
2
2







Chap10 - 39