Chapter10 Operational Amplifier Applications Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Chapter Goals • Continue study of methods to determine transfer functions of circuits containing op amps. • Introduction to active filters and switched capacitor circuits • Explore digital-to-analog converter specifications and basic circuit implementations. • Study analog-to-digital converter specifications and implementations. • Explore applications of op amps in nonlinear circuits, such as precision rectifiers. • Provide examples of multivibrator circuits employing positive feedback. • Demonstrate use of ac analysis capability of SPICE. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: Low-pass (Transfer Function) The transfer function is: G G 1 2 CC Vo(s) 1 2 A ( s) LP Vs(s) 2 G G G G s s 1 2 1 2 C CC 1 1 2 In standard form, s2 A ( s) LP • Op amp is voltage follower with s2 s o o2 Q unity gain over a wide range of C RR 1 o 1 2 frequencies. Q 1 RR CC R R C 1 2 1 2 • Uses positive feedback through C1 at 2 1 2 frequencies above dc to realize complex poles without inductors. • Feedback network provides dc path for amplifier’s input bias currents. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Often, circuits are designed with C1 = C2 = C. Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: Low-pass (Frequency Response) For Q=0.71,magnitude response is maximally flat (Butterworth Filter: Maximum bandwidth without peaking) For Q>0.71, response shows undesired peaking. For Q<0.71: Filter’s bandwidth capability is wasted. At <<o, filter has unity gain. At >>o,response exhibits twopole roll-off at 40dB/decade. At =o, gain of filter =Q. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Sensitivity, S represents fractional change in parameter, P due to a given fractional change in value of Z. Sensitivity of with respect to R and C is: S S 1 R C 2 Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: Low-pass (Example) • Problem: Design second-order low-pass filter with maximally flat response. • Given data: fH = 5 kHZ • Analysis:C1 = 2C2 = 2C and R1 = R2 = R. Q 1 2 2oC 1/oC is the reactance of C at o, R is 30% smaller than this value. Thus impedance level of filter is set by C. If impedance level is too low, op amp will not be able to supply current required to drive feedback network. 1 At 5 kHz, for a 0.01 mF capacitor, 1 3180W oC 104 (10 8 ) 3180W R 2250W 2 Final values: = R1 = R2 = 2.26kW, C1 = 0.02 mF, C2 = 0.01 mF R 1 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: High-pass with Gain (Transfer Function) The transfer function is: 1 s2 A ( s) o HP RC s2 s o o2 Q 1 R C C R C Q 1 1 2 (1 K ) 2 2 R CC R C 2 1 2 1 1 • • Voltage follower in low-pass filter replaced by non-inverting amplifier with gain K, which gives an added degree of freedom in design. dc paths for both op amp input bias currents through R2 and feedback resistors. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock For R1 = R2 = R and C1 = C2 = C, 1 o 1 Q RC 3 K For K=3, Q is infinite, poles are on j axis causing sinusoidal oscillations. K>3 causes instability due to right-half plane poles. 1 K 3 Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: High-pass with Gain (Frequency Response) • For Q=0.71,magnitude response is maximally flat (Butterworth Filter response). • Amplifier gain is constant at >o, the lower cutoff frequency of the filter. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: Band-pass (Transfer Function) Uses inverting op amp and its full loop gain (ideally infinite). V ( s) sC V (s) o 2 1 R 2 G V sC C G V (s) sC Vo(s) 1 th th 1 2 th 1 R RC Vo(s) so 3 2 2 A ( s) BP R R R C s2 s o 2 V ( s) 1 3 1 1 th o Q o 1 R CC 1 2 2 R R C C Q th 2 1 2 R C1 C2 th For C1 = C2 = C, R 1 2 BW 2 o Q C R R R R C th 2 th 2 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: Band-pass (Frequency Response) • Response peaks at o and gain at center frequency is 2Q2. • At <<o or >>o, filter response corresponds to single-pole high-pass or low-pass filter changing at a rate of 20dB/decade. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: Tow-Thomas Biquad General biquadratic transfer function to represent low-pass, high-pass, band-pass, all-pass and notch filters: a s2 a s a 0 T ( s) 2 1 s2 s o o2 Q In Tow-Thomas biquad, first op amp is a multi-input integrator and third op amp is simply an inverter. 1 1 1 V ( s) Vs ( s) V ( s ) V ( s) bp bp lp sR C sR C sRC 1 2 1 V ( s) V ( s) lp sRC bp so A ( s) K bp s2 s o o2 Q R R BW 1 1 K o Q 2 R C R R RC 2 1 o 2 A ( s) K lp s2 s o o2 Q Thus, center frequency, Q and gain can each be adjusted independently. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: Complete Tow-Thomas Biquad • The Tow-Thomas Biquad can achieve all filter functions with addition of extra passive components as shown. C R s 1 1 2 s 1 3 RR C 2 RR C C R Vo(s) 5 1 4 Av (s) Vs(s) 1 2 R 1 s s 2C 2 R RC R 2 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Active Filters: Tow-Thomas Biquad (Example) • • • • Problem: Design band-pass filter using Tow-Thomas circuit Given data: fo = 5 kHZ, BW = 200 Hz, midband gain =20 Unknowns: R, R1, R2, R3, C Analysis: Q fo 10 BW Input resistance to the filter is set by R1.At the center frequency, X 1 R 2R C oC 1 Also, first op amp must supply ac signal current to parallel combination of R, R2, C, second op amp must drive parallel combination of R3, C third must drive R3 in parallel with R. If we choose C = 2700 pF, R R 1 R 2 14.7kW R 10R 294kW R 29.4kW 1 20 2 2 4000C R3 can be chosen arbitrarily as long as it doesn’t load down second and third op amps. R3 =49.9 kW 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Magnitude Scaling • Magnitude of filter impedances may all be increased or decreased by a magnitude scaling factor KM, without changing o or Q of the filter. • To scale the magnitude of the impedance of the filter elements: R' K M C C' R K M 1 Z ' K Z M C C C ' Applying magnitude scaling to low-pass filter: 1 o ' K R K M 1 M Q' C 1 K M C 2 K M 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock C C 1 2 K M M R 2K 1 o RR CC 1 2 1 2 R K R C RR M 1 M 2 1 2 Q 1 K R K R R C 1 R2 M 1 M 2 2 K Copyright © 2005 – The McGraw-Hill Companies srl Frequency Scaling • Cutoff or center frequencies of filter may be scaled by a frequency scaling factor KF, without changing Q of the filter if each capacitor value is divided by KF and resistor values areR' left C R unchanged. C' K F Applying frequency scaling to low-pass filter: K 1 F o ' K o F C C RR CC 1 2 1 2 RR 1 2 1 2K K F F 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Q' C 1 C K R R2 RR 1 1 2 Q F 1 R R R C C 1 R2 2 1 2 2 K F Copyright © 2005 – The McGraw-Hill Companies srl Switched-Capacitor Circuits • Switched-capacitor (SC) circuits eliminate resistors in filters by replacing them with capacitors and switches. • Resulting filters are discrete-time or sampled-data equivalents of continuous-time filters discussed so far. • Provide additional flexibility not readily available in continuous-time form, such as inversion of signal polarity without using an amplifier. • SC circuits are compatible with high density MOS IC processes. • SC circuits provide low-pass filters and CMOS Ics for signal processing and communications applications. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl SC Integrator In phase 1, input voltage is sampled and output is constant.In phase 2, output changes to reflect sampled information in phase 1. Charge stored in phase 1 is: Q1 C1Vs V s vs n 1T Voltage stored on C1 at end of sampling interval Q C vo Change in charge stored 2 2 on C2 in phase 2. C vo 1 Vs C 2 Output voltage at end of nth clock cycle is: C vo nT vo (n 1)T 1 vs (n 1)T C 2 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Equivalence Between SC Integrator and Continuous Time Integrator Consider total charge Qs flowing from source vs through resistor R during clock period T. Vs Qs IT T R Equating this charge to charge stored on C1 Vs T C Vs 1 R R T 1 C f C 1 C 1 fC is clock frequency. For a capacitance of 1 pF and switching frequency of 100 kHz, equivalent resistance is 10 MW which is too large for IC realization. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Noninverting SC Integrator In phase 1, input voltage is sampled and output is constant. In phase 2, output changes to reflect sampled information in phase 1. C vo 1 Vs C 2 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Stray-Insensitive SC Circuits In phase 1, source is connected to summing junction of op amp, charge C1Vs is delivered to C2.Node 1 is driven by and node 2 is kept at zero. v C1 V o C s 2 In phase 2, source is disconnected, output is constant and C1 is totally discharged. Any stray capacitances at nodes 1 or 2 don’t introduce errors into charge transfer process. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Switched-Capacitor Band-Pass Filter R T R T th C 2 C 3 4 C C 1 C3C4 o fc 3 4 T CC CC 1 2 1 2 C CC 3 1 2 Q C C C 4 1 2 Center frequency is tunable just by changing clock frequency, Q is independent of frequency.But, SC filters are sampled-data systems, hence, f f c due to sampling theorem. 2 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Switched-Capacitor Tow-Thomas Biquad • Ability of SC circuits to change polarities without an amplifier eliminate one op amp in the SC implementation. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Digital-to-Analog (D/A) Converters: Fundamentals • In a DAC, an n-bit binary input word (b1,b2,…bn) is combined with reference voltage VREF to give output of the DAC. b 1,0 i vo V (b 21 b 2 2 ... bn 2 n ) V FS 1 2 OS • Full-scale voltage VFS is related to VREF of the converter V by KV REF FS where K determines converter gain commonly set to 1. • VOS, the offset voltage of the converter characterizes the DAC output when the digital input code is zero.Offset voltage is normally adjusted to zero. • The smallest voltage change at DAC output occurs when the LSB bn in the digital word changes from a 0 to 1 is also called resolution. V 2 nV LSB FS • b1, the MSB has a weight of one-half VFS. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl D/A Converter Specifications: Offset and Gain Errors • Maximum output of ideal converter is • • • • 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock always 1 LSB smaller than VFS. For shown ideal DAC characteristic, 0.875 VFS corresponds to maximum output code of 111. Gain error of converter represents deviation of slope of converter transfer function from that of corresponding ideal DAC. Shown ideal DAC has been calibrated so that VOS =0 and 1 LSB is VFS /8. Offset voltage is output of converter for zero binary input code. Copyright © 2005 – The McGraw-Hill Companies srl D/A Converter Specifications: Linearity Errors • Overall linearity error is magnitude of largest error that occurs.Good converter has linearity error<0.5 LSB • Differential linearity error is magnitude of maximum difference between each output step of converter and ideal step size of 1 LSB. • Integral linearity error or • Integral linearity error for a linearity error measures given binary input is the sum deviation of actual converter (integral) of differential output from straight line fitted to linearity errors for inputs up converter output voltages, through the given input. specified as a fraction of LSB. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl D/A Converter Specifications: Monotonicity • If the output of the DAC does not increase in a monotonic manner if the input code is increased, the DAC is said to be nonmonotonic. • It is possible for a monotonic converter to have a differential linearity error >1 LSB but, a nonmonotonic converter always has a differential linearity error > 1 LSB 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Weighted-Resistor DAC Drawbacks: • Need to have accurate resistor ratios over a wide range of resistor values. • Switches in series with resistors require zero offset voltage and low onBinary input data controls the switches. resistance. Successive resistors are progressively • Current drawn form weighted by a factor of 2 producing: reference varies with input vo V (b 21 b 2 2 ... bn 2 n ) pattern causing change in REF 1 2 voltage drop in Thevenin Linearity errors arise due to improper equivalent source resistance resistor ratios, op amp offset voltage adds of reference leading to datato VOS of converter. dependent errors called superposition errors. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl R-2R Ladder • • Avoids weighted-resistor DAC problem of wide range of resistor values. • Well-suited to IC realization as it requires matching of only two resistor values, R and 2R. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock The contribution of each bit is reduced by a factor of 2 going from MSB to LSB Drawbacks: • Requires switches with low on-resistance and zero offset voltage. • Current drawn from reference varies depending on input data pattern. Copyright © 2005 – The McGraw-Hill Companies srl Inverted R-2R Ladder • Currents in ladder and reference are independent of digital input. • Complementary currents are available at output of inverted ladder. • Switches still need to have low on-resistance to minimise errors. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Inherently Monotonic DAC • Analog switch tree connects desired tap to input of an op amp operating as a voltage follower. • Each tap on resistor network is forced to produce voltage grater than or equal to the taps below it , forcing the output to increase monotonically as the digital input code increases. • An 8-bit version requires 256 equal-valued resistors, 510 switches and additional decoding logic. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Switched-Capacitor DACs • Since circuits consist only of capacitors and switches, static power dissipation occurs only in the op amps. • Dynamic switching losses occur. • When switch changes state, current impulses charge/discharge network capacitos, changing voltage on feedback capacitor by an amount corresponding to bit weight of switch that changed state. • Circuits represent direct SC analogs of weighted-resistor and R-2R ladder DACs.Consume very less power. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl DACs in Bipolar Technology Bipolar transistors aren’t good voltage switches due to their inherent offset voltage in saturation, but, are very good current sources and switches. • Currents switched into summing junction, supplied through RF, determine output voltage of DAC. • VBE of current-source transistors must be same for proper weighting of current sources, requiring equal current densities in the transistors. Thus, area of each transistor is raised by factor of 2 from LSB to MSB. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl DACs in Bipolar Technology (contd.) Several methods can be used to overcome problems due to unmanageable transistor and resistor ratios in bipolar implementations of DACs- splitting current sources into groups with proper ladder termination, using R-2R ladder to generate weighted current sources, driving R-2R ladder by equal-value current sources. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Reference Current Circuitry for Bipolar Implementations of DACs An op amp is used to set the current in the reference transistor. Bipolar transistor and resistor ratio matching determine currents in rest of current-source network. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Analog -to-Digital (A/D) Converters: Fundamentals • ADC takes unknown continuous analog input signal, mostly voltage vX and converts it into n-bit binary number, which is a binary fraction representing ratio between unknown input voltageVandfull-scale voltage KV REF FS • For given output code, we know that value of input voltage lies within a 1-LSB quantization interval. Quantization error occurs due to initial underestimation and then overestimation of input voltage by output code. Ideal ADC should pick values of bits in binary word to minimise magnitude of quantization error: v v (b 21 b 2 2 ... bn 2 n )V X 1 2 FS 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl A/D Converter Specifications: Offset and Gain Errors • Differential linearity error is • difference between actual code step width and ideal step size of 1 LSB. • ADC with differential linearity error< 1LSB has no missing codes. • Gain error is deviation of slope of converter transfer function from that of corresponding ideal ADC. • Shown ADC characteristic has offset Integral linearity error or error of 0.5LSB first transition linearity error is deviation of code occurs at a 0.5LSB higher voltage. transition points from their ideal • Good ADC is monotonic with positions. Integral linearity error is linearity error<0.5LSB and no sum of differential linearity errors missing codes over full temperature for individual steps. range. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl A/D Conversion Techniques • If vX > vREF, output voltage is high corresponding to logic 1. • If vX < vREF, output voltage is high corresponding to logic 0. vREF is time-dependent reference voltage, varied till unknown input is determined within quantization error of converter. Ideally ADC logic chooses bi so that n i V v 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock V b 2 X FS i 1 i FS 2n 1 Copyright © 2005 – The McGraw-Hill Companies srl Counting ADC n-bit DAC used to generate any one of 2n outputs by applying appropriate digital input word. vX determined by sequentially comparing it to each possible DAC output. • Maximum conversion time occurs for fullscale input signal requiring 2n clock periods. • Binary value in counter is smallest DAC voltage larger than unknown input, not the DAC output closest to unknown input. • If input varies, binary output is accurate representation of input signal value at the instant the comparator changes state. • Requires minimum amount of hardware, inexpensive to implement. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Successive Approximation ADC •Binary search used by SAL to determine vX. •n-bit conversion needs n clock periods. Speed limited by time taken by DAC output to settle within a fraction of an LSB of VFS and by comparator to respond to input signals differing by small amounts. •Slowly varying input signals not changing by more than 0.5 LSB (VFS /2n+1 ) during conversion time (TT = nTC) are acceptable. •For a sinusoidal input signal with p-p amplitude= VFS, fo fc 2n2n •To avoid this frequency limitation, high speed sampleand-hold circuit is used ahead of the successive approximation ADC. •Very popular ADC with fast conversion times, used in 8- to 16- bit converters 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Single-Ramp (Single-Slope) ADC •Reference voltage varies linearly with a welldefines slope from slightly below 0 to above VFS v N v KNT X n if K= VFS / 2nTC. X C V 2 FS •Maximum conversion time occurs for fullscale input signal requiring 2n clock periods. •Counter output is value of vX at the time endof-conversion signal occurs. •Ramp voltage can be generated using an integrator connected to a constant reference voltage. •Dependence of ramp’s slope on RC product which is susceptible to changes due to temperature variations or aging is a limitation of this ADC. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Dual-Ramp (Dual-Slope) ADC T 2nT 1 C T NT 2 C T T T 1 1 1 1 2 v x (t )dt VREF (t )dt RC 0 RC T 1 T vx N 2 n T 2 V REF 1 •Absolute values of R and C don’t affect operation. •Digital output word gives average value of vX during first integration phase. •Conversion time is given by: T (2n N )T 2n1T T C C •Can be used to get resolutions exceeding 20 bits but at lower conversion rates. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Dual-Ramp (Dual-Slope) ADC (contd.) • Integrator in dual-ramp ADC has the shown normalised transfer function. • Sinusoidal inputs with frequencies that are exact multiples of 1/T1, have integrals of zero and don’t appear at integrator output. This property is called normal-mode rejection. • Recent dual-slope ADCs include extra integration phases for automatic offset elimination. • Triple ramp ADC uses coarse and fine down ramps to improve speed by factor of 2n/2 for n-bit dual-ramp converter. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Parallel or Flash ADC • Unknown input simultaneously compared to 7 different reference voltages (3-bit converter). Logic network encodes comparator outputs into 3-bit binary output representing quantized value of input voltage. • Very fast speed ( up to 108-109 conversions/sec), limited only by delays of comparators and logic network. • Output continuously reflects input delayed by comparator and logic network. • Requires 2n-1 comparators and reference voltages for n-bit conversion. Used for resolutions up to 10 bits. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Delta Sigma ADCs Feedback loop attempts to force integrator output to zero. V V Called oversampled because internal ADC samples integrator output at 16 to 512 times Nyquist rate.Digital filter produces higher resolution. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock MT C X RC NT V C REF RC V (2m 2 N ) REF m X 2 (M V REF N )T C 0 RC If M=2m N/M is average value of binary bit stream at output.LSB is VREF= 2m Effective resolution is determined by the time for which the output is averaged. Converter operation is considerably complex for time-varying input signals. Copyright © 2005 – The McGraw-Hill Companies srl Delta Sigma ADCs: SC Implementation • Continuous-time integrator can be replaced by SC integrator for low-power operation. • Charge proportional to input is added to integrator output at each sample time and charge given by CVREF is added or subtracted at each sample depending on control sequence applied to switches. • Delta-Sigma ADCs are inherently linear due to the 1-bit DAC. • SC integrator suffers lesser from jitter than continuous-time integrator as long as the clock interval is long enough for complete charge transfer to finish 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Nonlinear Circuit Applications: Precision Half-Wave Rectifier • For vS >0, vO = vS, i>0, diode is forward• • • • vO is rectified replica of vS without loss of voltage drop as in diode rectifier circuit. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock biased and feedback loop is closed. Rectification is perfect even for small input voltages.. For vS <0,diode is cutoff, i=0, vO=0. Primary sources of error are gain error and offset error due to nonideal op amp. For negative input voltages, output voltage v1 is saturated at negative limit. Large negative voltages across input can destroy unprotected op amps. Response time of circuit is slowed down due to slow recovery of internal circuits from saturation. Copyright © 2005 – The McGraw-Hill Companies srl Nonlinear Circuit Applications: NonSaturating Precision Half-Wave Rectifier • For vS >0, v1 is negative (one diode-drop below zero), D2 is forward biased, current in R2 is zero, vO = 0, D1 is reverse biased. Feedback loop is closed through D2. • For vS <0, v1 is one diode-drop above output voltage, diode D1 turns on, D2 is off. Circuit behaves as inverting amplifier with gain - R2 / R1. Feedback loop is closed through D1 and R2. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Nonlinear Circuit Applications: AC Voltmeter For a sinusoidal input of amplitude VM and frequency o, output is a rectified sine wave given by its Fourier series. If cutoff frequency of low-pass filter c << o, output consists primarily of dc voltage component. R R V vo 4 2 M R R 3 1 Half-wave rectifier is combined with low-pass filter to form basic ac voltmeter. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Voltmeter range can be adjusted through the 4 resistors. Copyright © 2005 – The McGraw-Hill Companies srl Circuits with Positive Feedback: Comparator • For inputs>VREF,output saturates at VCC. • For inputs<VREF,output saturates at -VEE. • Amplifiers built for use as comparators can handle saturation at the voltage extremes without incurring excessive internal time delays. • For noisy inputs, multiple transitions may occur as input signal crosses reference level. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Schmitt Trigger • Schmitt trigger uses positive feedback and is bistable. • For positive output voltages,VREF=bVCC. For positive output voltages,VREF=-bVEE. Reference level changes when output changes state. • Voltage transfer characteristic exhibits hysteresis and doesn’t respond to noise voltage magnitude smaller than the difference between the 2 threshold levels set by the reference voltage Vn b V (V ) b (V V ) EE 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock CC EE CC Copyright © 2005 – The McGraw-Hill Companies srl Astable Multivibrator • Uses positive and negative feedback to generate rectangular output. • Output voltage switches periodically between VCC and -VEE. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock For symmetrical power supplies, output of circuit is square wave with period T 1 b T T T 2RC ln 1 2 1 b Copyright © 2005 – The McGraw-Hill Companies srl Astable Multivibrator (contd.) • Astable multivibrator can be used to generate square, triangular and sine wave outputs as shown at frequencies up to few MHz. • Frequency is varied by changing R3 or C3, C3 is changed in decade steps, R3 may be varied continuously using potentiometer. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Monostable Multivibrator or One Shot • Operates with one stable state, generates single pulse of known duration on application of trigger signal. • D1 couples trigger signal into circuit, clamping diode D2 limits negative voltage excursion on capacitor C. 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock Copyright © 2005 – The McGraw-Hill Companies srl Monostable Multivibrator (contd.) • Output of circuit consists of positive pulse with fixed duration T given by V 1 D V CC T RC ln 1 b • For well-defined pulse, circuit should not be triggered till voltages on all nodes return to their quiescent steady-state values. • Recovery time (return of circuit V CC 1 b to state before trigger pulse was V EE applied) is given by: Tr RC ln 1 2 Microelettronica – Circuiti integrati analogici 2/ed Richard C. Jaeger, Travis N. Blalock V V D EE Copyright © 2005 – The McGraw-Hill Companies srl