COMP541
Datapath &
Single-Cycle MIPS
Montek Singh
Mar 25, 2015
1
Topics
 Complete the datapath
 Add control to it
 Create a full single-cycle MIPS!
 Reading
 Chapter 7
 Review MIPS assembly language
 Chapter 6 of course textbook
 Or, Patterson Hennessy (inside front flap)
A MIPS CPU
reset
Instr
Memory
clk
clk
pc
memwrite
instr
dataaddr
writedata
readdata
MIPS CPU
Data
Memory
3
Top-Level: MIPS CPU + memories
Top-level module
Instr
Memory
reset
clk
reset
clk
clk
pc
memwrite
instr
dataaddr
writedata
readdata
MIPS CPU
Data
Memory
We will add I/O devices (display, keyboard, etc.) later
4
One level down: Inside MIPS
 Datapath: components that store or process data
 registers, ALU, multiplexors, sign-extension, etc.
 we will regard memories as outside the CPU, so not part of the core datapath
 Control: components that tell datapath what to do and when
 control logic (FSMs or combinational look-up tables)
MIPS CPU
clk
Control
reset
ALUFN,
regwrite,
regdst…
opcode,
func,
flagZ …
memwrite
clk
pc
Instr
Memory
instr
MIPS
Datapath
dataadr
writedata
readdata
Data
Memory
Review: MIPS instruction types
Three instruction formats:
 R-Type: register operands
 I-Type: immediate operand
 J-Type: for jumps
6
Review: Instruction Formats
R-Type
op
6 bits
rs
5 bits
rt
rd
shamt
funct
5 bits
5 bits
5 bits
6 bits
I-Type
op
6 bits
rs
5 bits
rt
imm
5 bits
16 bits
J-Type
op
addr
6 bits
26 bits
R-Type instructions
 Register-type
 3 register operands:
 rs, rt: source registers
 rd: destination register
 Other fields:
 op: the operation code or opcode (0 for R-type instructions)
 funct: the function
– together, op and funct tell the computer which operation to perform
 shamt: the shift amount for shift instructions, otherwise it is 0
R-Type
op
6 bits
rs
5 bits
rt
rd
shamt
funct
5 bits
5 bits
5 bits
6 bits
R-Type Examples
Field Values
Assembly Code
rs
op
rt
rd
shamt
funct
add $s0, $s1, $s2
0
17
18
16
0
32
sub $t0, $t3, $t5
0
11
13
8
0
34
5 bits
5 bits
5 bits
5 bits
6 bits
6 bits
Note the order of
registers in the assembly
code:
add rd, rs, rt
Machine Code
op
rs
rt
rd
shamt
funct
000000 10001 10010 10000 00000 100000 (0x02328020)
000000 01011 01101 01000 00000 100010 (0x016D4022)
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
I-Type instructions
 Immediate-type
 3 operands:
 op: the opcode
 rs, rt: register operands
 imm: 16-bit two’s complement immediate
I-Type
op
6 bits
rs
5 bits
rt
imm
5 bits
16 bits
I-Type Examples
Assembly Code
Field Values
rs
op
rt
imm
addi $s0, $s1, 5
8
17
16
5
addi $t0, $s3, -12
8
19
8
-12
lw
$t2, 32($0)
35
0
10
32
sw
$s1,
43
9
17
4
4($t1)
6 bits
Note the differing order of
registers in the assembly and
machine codes:
5 bits
5 bits
16 bits
Machine Code
op
rs
rt
imm
001000 10001 10000 0000 0000 0000 0101 (0x22300005)
addi rt, rs, imm
001000 10011 01000 1111 1111 1111 0100 (0x2268FFF4)
lw
rt, imm(rs)
100011 00000 01010 0000 0000 0010 0000 (0x8C0A0020)
sw
rt, imm(rs)
101011 01001 10001 0000 0000 0000 0100 (0xAD310004)
6 bits
5 bits
5 bits
16 bits
J-Type instructions
 Jump-type
 26-bit address operand (addr)
 Used for jump instructions (j)
J-Type
op
addr
6 bits
26 bits
Summary: Instruction Formats
R-Type
op
6 bits
rs
5 bits
rt
rd
shamt
funct
5 bits
5 bits
5 bits
6 bits
I-Type
op
6 bits
rs
5 bits
rt
imm
5 bits
16 bits
J-Type
op
addr
6 bits
26 bits
MIPS State Elements
CLK
CLK
PC'
PC
32
32
32
A
RD
Instruction
Memory
5
32
5
5
32
A1
A2
A3
WD3
CLK
WE3
RD1
RD2
Register
File
WE
32
32
32
32
A
RD
Data
Memory
WD
32
We will fill out the datapath and control logic for basic single cycle MIPS
• first the datapath
• then the control logic
14
MIPS Design from Comp411
We will not be implementing the textbook
version of MIPS in our labs.
Instead, we will implement the MIPS design
from Comp411, which has more features.
15
Design Approach
“Incremental Featurism”
 We will implement circuits for each type of instruction
individually, and merge them (using MUXes, etc).
Our Bag of Components:
Steps:





1.
2.
2.
3.
4.
3-Operand ALU instrs
ALU w/immediate instrs
Loads & Stores
Jumps & Branches
Exceptions (briefly)
Registers
A
B
ALU
RA1
WA
WE
WD
Muxes
1
0
ALU & adders
+
RA2
Register
File
(3-port)
WD
A
D
Instruction
Memory
A
RD
R/W
RD1
RD2
Memories
Data
Memory
Review: The MIPS ISA
OP
6
5
5
5
5
16
26
000000
R-type:
001XXX
I-type:
10X011
I-type:
10X011
I-type:
rs
rt
rd
shamt
6
func
ALU with Register operands
Reg[rd]  Reg[rs] op Reg[rt]
rs
rt
immediate
The MIPS
instruction set as
seen from a
Hardware
Perspective
ALU with constant operand
Reg[rt]  Reg[rs] op SEXT(immediate)
rs
rt
immediate
Load and Store
Reg[rt]  Mem[Reg[rs] + SEXT(immediate)]
Mem[Reg[rs] + SEXT(immediate)]  Reg[rt]
rs
rt
immediate
Branch Instructions
if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate)
if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate)
26-bit constant
00001X
J-type:
jump
PC  (PC & 0xf0000000) | 4*(immediate)
Instruction classes
distinguished by types:
1) 3-operand ALU
2) ALU w/immediate
3) Loads/Stores
4) Branches
5) Jumps
Fetching Sequential Instructions
32
4
32
P
C
32
Read
Address
32
+
Instruction
register
Instruction
Memory
We will talk about
branches and
jumps later.
Instruction Fetch/Decode
 Use a counter to FETCH the
next instruction:
 PROGRAM COUNTER (PC)
PC
 use PC as memory address
 add 4 to PC, load new value
at end of cycle
00
A Instruction
32
Memory
D
+4
 fetch instruction from
32
32
INSTRUCTION
WORD
FIELDS
OP[31:26], FUNC[5:0]
Control Logic
CONTROL SIGNALS
memory
 use some instruction fields
directly (register numbers,
16-bit constant)
 decode rest of the instruction
 use bits <31:26> and <5:0>
to generate controls
3-Operand ALU Data Path
rs
000000
PC
R-type:
00
A
rt
D
Rs: <25:21>
Rd: <15:11>
RA1
WA
RD1
Rt: <20:16>
Register
File
RA2
WD
RD2
32
WE
32
Control Logic
A
ALUFN
00000
ALU with Register operands
Reg[rd]  Reg[rs] op Reg[rt]
Instruction
Memory
+4
B
ALU
ALUFN
WERF!
rd
WERF
32
WERF
100XXX
Shift Instructions
rs
000000
PC
R-type:
00
A
D
Rt: <20:16>
Rs: <25:21>
Rd: <15:11>
RA1
WA
RD1
Register
File
RA2
WD
RD2
shamt:<10:6>
Control Logic
0
1
ASEL
A
ALUFN
ASEL!
B
ALU
ALUFN
WERF
ASEL
rd
shamt
000XXX
ALU with Register operands
sll: Reg[rd]  Reg[rt] (shift) shamt
sllv: Reg[rd]  Reg[rt] (shift) Reg[rs]
Instruction
Memory
+4
rt
32
WE
WERF
ALU with Immediate
rs
001XXX
PC
I-type:
00
A
rt
immediate
ALU with constant operand
Reg[rt]  Reg[rs] op SEXT(immediate)
Instruction
Memory
D
+4
Rt: <20:16>
Rs: <25:21>
BSEL
Rd:<15:11>
Rt:<20:16>
0
RA1
1
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
imm: <15:0>
Control Logic
BSEL
ALUFN
WERF
ASEL
SEXT
shamt:<10:6>
1
0
SEXT
BSEL!
SEXT
1
BSEL
ASEL
A
ALUFN
0
B
ALU
How do you
build SEXT?
• 1  pad with sign
• 0  pad with 0s
Load Instruction
rs
100011
I-type:
PC
+4
immediate
Load
Reg[rt]  Mem[Reg[rs] + SEXT(immediate)]
00
A
rt
Instruction
Memory
D
Rt: <20:16>
Rs: <25:21>
BSEL
Rd:<15:11>
Rt:<20:16>
0
RA1
1
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
SEXT
SEXT
shamt:<10:6>
Control Logic
0
SEXT
BSEL
WDSEL
ALUFN
Wr
ASEL
1
A
ALUFN
1
0
BSEL
B
ALU
WD
R/W
Data Memory
32
WERF
ASEL
32
0
1
2
WDSEL
Adr
RD
Wr
Store Instruction
rs
10X011
PC
I-type:
00
A
rt
immediate
Store
Mem[Reg[rs] + SEXT(immediate)]  Reg[rt]
Instruction
Memory
D
+4
Rt: <20:16>
Rs: <25:21>
BSEL
Rd:<15:11>
Rt:<20:16>
0
RA1
1
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
SEXT
SEXT
shamt:<10:6>
Control Logic
SEXT
BSEL
WDSEL
ALUFN
Wr
0
ASEL
1
A
ALUFN
1
0
BSEL
32
No WERF!
B
ALU
WD
R/W
Data Memory
Adr
WERF
ASEL
0
1
2
WDSEL
RD
Wr
JMP Instructions
PC<31:28>:J<25:0>:00
26-bit constant
00001X
PCSEL
3
2
PC
1
J-type:
j: PC  (PC & 0xf0000000) | 4*(immediate)
jal: PC  (PC & 0xf0000000) | 4*(immediate);
Reg[31]  PC + 4
0
00
Instruction
Memory
A
D
+4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
31
0
1
2
RA1
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
SEXT
SEXT
shamt:<10:6>
Control Logic
0
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
ASEL
1
A
1
0
BSEL
B
ALU
ALUFN
WD
R/W
Data Memory
Adr
WERF
ASEL
PC+4
32
0
1
2
WDSEL
RD
Wr
BEQ/BNE Instructions
PC<31:28>:J<25:0>:00
BT
PCSEL
3
2
PC
That “x4” unit is
trivial. I’ll just
wire the input
shifted over 2–
bit positions.
1
rs
10X011
0
R-type:
immediate
Branch Instructions
if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate)
if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate)
00
Instruction
Memory
A
rt
D
+4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
2
31
RA1
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
x4
Why add, another
adder? Couldn’t
we reuse the one
in the ALU?
Nope, it needs to
do a subtraction.
SEXT
SEXT
Z
shamt:<10:6>
+
Control Logic
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
0
ASEL
1
1
0
BSEL
BT
A
B
ALU
ALUFN
WD
R/W
Data Memory
Adr
Z
WERF
ASEL
PC+4
32
0
1
2
WDSEL
RD
Wr
Jump Indirect Instructions
PC<31:28>:J<25:0>:00
BT
JT
PCSEL
3
2
PC
1
rs
000000
0
R-type:
rd
00100X
00000
Jump Indirect, Jump and Link Indirect
jr:
PC  Reg[rs]
jalr: PC  Reg[rs], Reg[rd]  PC + 4
00
Instruction
Memory
A
rt
D
+4
Rt: <20:16>
Rs: <25:21>
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
RA1
0
1
2
31
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
JT
Z
x4
shamt:<10:6>
+
Control Logic
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
SEXT
SEXT
0
ASEL
1
1
0
BSEL
BT
A
B
ALU
ALUFN
WD
R/W
Data Memory
Adr
Z
WERF
ASEL
PC+4
32
0
1
2
WDSEL
RD
Wr
Comparisons
BT
JT
PCSEL
3
2
PC
1
rs
001XXX
PC<31:28>:J<25:0>:00
rt
immediate
I-type: set on less than & set on less than unsigned immediate
slti: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0
sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0
0
00
Instruction
Memory
A
D
+4
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
RA1
0
1
2
31
Rt: <20:16>
Rs:
<25:21>
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
JT
Z
x4
shamt:<10:6>
+
Control Logic
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
SEXT
SEXT
0
ASEL
1
1
0
BSEL
BT
A
B
ALU
ALUFN
WD
R/W
Data Memory
Adr
Z
WERF
ASEL
PC+4
32
0
1
2
WDSEL
RD
Wr
More comparisons
BT
JT
PCSEL
3
2
PC
1
rs
000000
PC<31:28>:J<25:0>:00
rt
rd
00000
10101X
R-type: set on less than & set on less than unsigned
slt: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0
sltu: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0
0
00
Instruction
Memory
A
D
+4
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
RA1
0
1
2
31
Rt: <20:16>
Rs:
<25:21>
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
JT
Z
x4
shamt:<10:6>
+
Control Logic
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
SEXT
SEXT
0
ASEL
1
1
0
BSEL
BT
A
B
ALU
ALUFN
WD
R/W
Data Memory
Adr
Z
WERF
ASEL
PC+4
32
0
1
2
WDSEL
RD
Wr
LUI
BT
JT
PCSEL
3
2
1
immediate
I-type: Load upper immediate
0
Reg[rt]  Immediate << 16
lui:
PC
rt
001XXX 00000
PC<31:28>:J<25:0>:00
00
A
Instruction
Memory
D
+4
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
RA1
0
1
2
31
Rt: <20:16>
Rs:
<25:21>
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
JT
Z
x4
shamt:<10:6>
+
Control Logic
“16”
ASEL
0 1 2
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
WERF
ASEL
SEXT
SEXT
1
0
BSEL
BT
A
B
ALU
ALUFN
WD
R/W
Data Memory
Adr
Z
PC+4
32
0
1
2
WDSEL
RD
Wr
Reset, Interrupts, and Exceptions
 Upon reset/reboot:
 Need to set PC to where boot code resides in memory
 Interrupts/Exceptions:
 any event that causes interruption in program flow
 FAULTS: e.g., nonexistent opcode, divide-by-zero
 TRAPS & system calls: e.g., read-a-character
 I/O events: e.g., key pressed
 How to handle?
 interrupt current running program
 invoke exception handler
 return to program to continue execution
 Registers $k0, $k1 ($26, $27)
 reserved for operating system (kernel), interrupt handlers
 any others used must be saved/restored
Exceptions
0x80000000
0x80000040
0x80000080
PCSEL
Reset:
PC  0x80000000
Bad Opcode: Reg[27]  PC+4; PC  0x80000040
IRQ:
Reg[27]  PC+4; PC  0x80000080
PC<31:28>:J<25:0>:00
BT
JT
6
5
4
3
2
PC
1
0
00
A
Instruction
Memory
D
+4
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
31
27
RA1
0
1
2
3
Rt: <20:16>
Rs:
<25:21>
RA2
Register
File
WA
WA
RD1
WD
RD2
WE
WERF
Imm: <15:0>
RESET
JT
IRQ Z
x4
shamt:<10:6>
+
Control Logic
“16”
ASEL
0 1 2
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
WERF
ASEL
SEXT
SEXT
1
0
BSEL
BT
A
B
ALU
ALUFN
WD
R/W
Data Memory
Adr
Z
PC+4
32
0
1
2
WDSEL
RD
Wr
Exceptions: Our Lab Version
 We will not implement exceptions
 But: hardwire a “Reset” input which sets PC to 0, so it starts over
PC<31:28>:J<25:0>:00
B
T
JT
PCSEL
3
2
PC
1
0
00
A
RESE
T
Reset: PC

Instruction
Memory
D
+4
0
J:<25:0>
Rd:<15:11>
Rt:<20:16>
RA1
WA
WA
0
1
2
31
Rt: <20:16>
Rs:
<25:21>
WASEL
Register
File
RD1
RA2
WD
RD2
WE
WERF
Imm: <15:0>
JT
Z
x4
shamt:<10:6>
+
Control Logic
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
WERF
ASEL
B
T
SEXT
SEXT
“16”
ASEL
0 1 2
A
1
0
BSEL
B
ALU
ALUFN
WD
R/W
Data Memory
Adr
Z
PC+4
32
0
1
2
WDSEL
RD
Wr
MIPS: Our Final Version
This is a complete 32-bit processor.
Although designed in “one” class lecture,
it executes the majority of the
MIPS R2000 instruction set.
PC<31:28>:J<25:0>:00
BT
PCSEL
3
2
1
0
newPC
pcPlus4
00
PC
pc
RESE
T
instr
A
Instruction
Memory
D
+4
WASEL
J:<25:0>
Rd:<15:11>
Rt:<20:16>
0
1
2
31
reg_writeaddr
JT
RA1
JT
shamt:<10:6>
“16”
ASEL
0 1 2
BT
1
BSEL
0
mem_writedata
aluB
aluA
A
B
ALU
ALUFN
WD
mem_addr
alu_result
mem_readdata
(PC+4)
32
0
1
2
WDSEL
mem_wr
R/W
Data Memory
Adr
Z
pcPlus4
WERF
signImm
+
PCSEL
WASEL
SEXT
BSEL
WDSEL
ALUFN
Wr
WERF
ASEL
RD2
WE
ReadData2
reg_writedata
SEXT
SEXT
<<2
Control Logic
WD
RD1
ReadData1
Imm: <15:0>
Z
RA2
Register
File
WA
WA
Executes one
instruction
per clock
Rt: <20:16>
Rs:
<25:21>
RD
Wr
MIPS Control
 The control unit can be built as a large look-up table/ROM
 or, a case statement in Verilog!
Instruction
add
sll
andi
lw
sw
beq
…
P
C
S
E
L
S
E
X
T
W
A
S
E
L
W
D
S
E
L
0
x
0
1
W
R
Sub Bool Shift Math
W
E
R
F
A
S
E
L
B
S
E
L
0
0 1 0
1
0
0
ALUFN
xx
Review: Our “full feature” ALU
 Our ALU from Lab 3 (with support for comparisons)
A
Sub
Bool
B
Boolean
<?
Shft
0
Math
Flags
N,V,C
Bidirectional
Shifter
Add/Sub
1
1
1
Bool0
0
0
Result
Z
Flag
5-bit ALUFN
Sub Bool Shft Math
0
XX
0
1
1
XX
0
1
1
X0
1
1
1
X1
1
1
X
00
1
0
X
10
1
0
X
11
1
0
X
00
0
0
X
01
0
0
X
10
0
0
X
11
0
0
OP
A+B
A-B
A LT B
A LTU B
B<<A
B>>A
B>>>A
A & B
A | B
A ^ B
A | B
36
Summary
 We learned about a complete MIPS CPU
 NOTE: Many details in textbook are different…
 … from what you will implement in the lab
 our lab MIPS has more features
 Next class:
 We will look at performance of single-cycle MIPS
 We will look at multi-cycle MIPS to improve performance
 Next lab:
 Implement single-cycle CPU!