Hardware-Software Partitioning and Co-Design - Ann Gordon-Ross
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Hardware-Software Partitioning EEL6935 2 / 52 Hardware Software Definition • Definition: Given an application, hw/sw partitioning maps each region of the application onto β« β« β« either a hardware (custom circuits) or a software (microprocessors), but not both • A partition is a mapping of each region to either HW or SW • Mapping is done to meet certain Design Goals with Constraints EEL6935 3 / 52 Design Constraints & Goals Yield EEL6935 4 / 52 You cannot get away with Everything ! EEL6935 Challenges • Exploration Space α ππ₯π# ππ πΆππππππππ‘π β« E.g. Configurations possible for 30 software components in an application which may be implemented as hardware = 230 = 1Billion • Each component for different tradeoffs may have β« Multiple software implementation β« Multiple hardware implementation 5 / 52 EEL6935 6 / 52 Application with the Multiple Hardware Software Options FIR() Process Hardware Implementation Options : Area and Execution Time 25s ACCUM() 15s 10s 5s 12s 10s 8s Sw Time: 50s Possible Solutions: SEARCH() 5s Sw Time: 20s Sw Time: 30s Use fastest implementations Use smallest implementations 25s 15s Area Budget Performance: 5s 5+30+20=55s Consider all “middle” implementations 10s 15s 10s 25+15+10=50s Acknowledgement: Modified from G. Stitt’s slides in EEL5721 10+15+20=45s Best Partition EEL6935 7 / 52 Mathematical Modeling to arrive at the Optimum H/W-S/W Partition • • • • • • • ππ = πβππ‘βππ πππππππππ‘ π ππππ ππ π»π? 1: 0 ππ = πβππ‘βππ πππππππππ‘ π ππππ ππ ππ? 1: 0 βππ‘π = Hardware execution time of ith component π ππ‘π = Software Execution Time of the ith component βππ = Hardware Power of the ith component π ππ = Software Power of the ith component ππ = π΄πππ ππ π‘βπ πππππππππ‘ ππ πππππππππ‘ππ ππ π»ππππ€πππ • πππ‘ππ πΈπ₯πππ’π‘πππ ππππ = ππ=1[ ππ ∗ βππ‘π + 1 − ππ ∗ π ππ‘π ] ≤ π·ππ πππ πΆπππ π‘πππππ‘ • πππ‘ππ πΈπ₯πππ’π‘πππ πππ€ππ = ππ=1[ ππ ∗ βππ + 1 − ππ ∗ π ππ ] ≤ π·ππ πππ πΆπππ π‘πππππ‘ • Any component is either implemented in Hardware of Software but not in both π (ππ + ππ ) = 1 π=1 Dynamic Hardware-Software Partitioning: A First Approach Greg Stitt, Roman Lysecky, Frank Vahid, University of California, Riverside DAC 2003, June 2-6,2003, Anaheim, California, USA EEL6935 10 / 52 Dynamic Hardware-Software Partitioning • Dynamically β« identify and re-implement ο critical software kernels, loops etc. to configurable fabric ο in order to achieve better performance, lower energy or meet other design goals EEL6935 11 / 52 EEL5935 Multiple Applications an Illustration EEL6935 12 / 52 EEL5935 Application Usage Profile: An Illustration Different users have different usage profiles User • While designing a product usage profile needs to be assumed to give best user experience. However Mr. Jazz β« Usage Profile (Application usage) may be User/code dependent ο E.g. MP3, Camera, Video Playback, Call etc. β« Usage Mr. Luigi profile may change over-time β« Generic product assuming a certain profile ο is optimum for the “assumed” profile but sub-optimal in terms of area or performance for other usage profiles Mr. MTB • Profiling in real time is key β« usage profile may identify critical kernels ο Critical components may be pushed to configurable area ο To boost the performance and reduce energy EEL6935 13 / 52 Dynamic HW/SW Partitioner Requirements 1. Detect critical code regions 2. Decompile and synthesize them to hardware 3. Place and Route the Hardware onto on-chip configurable logic 4. Update binary to communicate with the logic • All of the above with on-chip algorithms Wait ! Did you say onimplementable, very chip PnR ? You got to be kidding ! Right ? lean EEL6935 14 / 52 Binary Level Partitioning and Advantage • Partitioning at the binary level β« offline or online β« Steps 1. identify critical code sections, high loop sections 2. Consider assembly code and object code as HW candidates 3. Push these to configurable hardware • Advantage β« Works with any ο software compiler ο High level language The Paper uses Binary Level partitioning approach. Critical Loops identified and implemented in the Configurable logic EEL6935 15 / 52 Why Binary Level Partitioning instead of higher level optimizations ? • Dynamic Partitioning β« Needs to run on a small on-chip partitioning system β« Needs to be lean to be able to perform Place and Route etc. on-chip β« Higher Level Partitioning Methodologies may be good for offline analysis, but very difficult to implement due to the compute constrain. EEL6935 16 / 52 EEL5935 HW/SW Partitioning of Software Binary Acknowledgement: Figure taken from G. Stitt, F. Vahid HW/SW Partitioning of Software Binaries ICCAD Nov 2002 EEL6935 17 / 52 EEL5935 System Architecture (Top) Microprocessor and Memory for normal Software application 1. Detects Most Frequently Executed Software region 2. Re-implements (1) in the configurable logic Architecture Based on Triscend A7 (60MHz) On chip configurable module EEL6935 18 / 52 EEL5935 System Architecture (Sub Blocks) Detects Most Frequently executed applicationsoftware loops Direct Memory Access Controller to access memory Output Decompiles and synthesized selected binary regions for HW implementation Input 32-bit i/p – o/p register Partitioning Co-Processor Overhead: i. Not much : Very Lean compared to Main Processor ii. Platform with multiple Main Processors may share single Partitioning coprocessor, reducing the overhead further EEL6935 Simplified Configurable Logic Fabric • Simplified Fabric to just support inner loop implementation designed • Mapping, placing and routing a design to a general configurable logic fabric is time consuming 19 / 52 EEL6935 20 / 52 Architecture Limitations • No sequential Logic support in the Configurable logic (in the platform chosen) β« Constraint: ο Loops to be implemented must have single cycle implementable body • Number of loop iterations must be determined before the loop executes, in order to specify the DMA block size request. β« Number of iterations may be determined : ο Statically in case of constant bounds ο Dynamically ο requires extra instructions to configure the size of the DMA block request before HW execution starts • United States Patent 5,440,245 : Galbraith , et al. August 8, 1995 Logic module with configurable combinational and sequential blocks EEL6935 21 / 52 EEL5935 CLF Architecture Either side connect-ability (only at bottom) 4 channel: Given Channel to Given Channel EEL6935 22 / 52 EEL5935 Tool Flow : Loop Profiler 1. Detects critical SW regions that should be implemented in HW 2. Is Non intrusive 3. Monitors instruction addresses on the memory bus 4. Increments branch frequency in the cache for a given backward branch 5. Small cache with a dozen entries • Need to save area and power Reference: Ann Gordon-Ross et. al Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware IEEE TRANSACTIONS ON COMPUTERS, VOL. 54, NO. 10, OCTOBER 2005 EEL6935 23 / 52 Decompilation • Converts Software loops into higher level abstraction more suitable for synthesis β« Step 1 : Converts each assembly instruction to register transfer β« Step 2: Using Register Transfers Builds: ο CFG (Control Flow Graph) for software region ο DFG(Data Flow Graph) by parsing the Register transfers β« Step 3: Applies compiler optimizations to remove overhead due to assembly code and instruction set EEL6935 24 / 52 DMA Configuration Tool • Function: Maps the memory access of the decompiled loop onto the DMA Architecture β« Involves detection of ο Reads/ writes ο Increment and decrement address updates ο Single and block request modes • Remove following from Decompiled loop β« Loop counters and exit conditions β« Address calculations: As only sequential locations accessed • DMA functioning: β« DMA transfers data needed before the loop starts β« After HW initialization, HW starts a block request that fetches 1 memory location per cycle in case of a read or write EEL6935 Register Transfer Synthesis • Converts each o/p bit into Boolean expression β« By traversing the dataflow graphs of the software region • Limitation: β« Single cycle executable loopbodies only β« Multi cycle would need behavioral synthesis to schedule loop operations 25 / 52 EEL6935 26 / 52 Logic Synthesis ο Tech Mapping ο P&R • Converts Boolean equations into a netlist • Boolean equations transformed into DAG (directed acyclic Graph) of the Boolean Logic network β« Internal Nodes of DAG correspond to simple logic gates (AND/OR/INV, XOR) • Logic minimization β« Light weight suited for on-chip execution ο Applied at each node starting with the input nodes, while traversing through the network ο Uses single expand phase to achieve good optimization • Tech Mapping β« Traverses DAG starting from output nodes ο Combines nodes that may create 3 i/p 1 o/p LUT ο Further combine nodes (where possible ) to form 3 i/p 2 o/p LUTs EEL6935 LUT Placement Steps • Step 1: Determine relative placement of LUTs to one another β« by determining the critical path, and placing it on a horizontal row • Step 2 : For remaining non-placed nodes place as per dependency (i/p or o/p) w.r.t. placed β« Place above for inputs to Placed nodes β« Place below for outputs from Placed nodes • Step 3: Place in the Configurable Logic 27 / 52 EEL6935 28 / 52 Routing • Simple Greedy algorithm β« Routes wires in most direct fashion ο Route the wires between input nodes and LUTs ο Route wires from LUTs to outputs ο Route wires connecting LUTs together • Routing decisions at Switch Matrices for within conifugrable logic fabric EEL6935 Bitfile Creation • Combines β« the Placed and routed hardware description with the DMA configuration information into a single bit file • Bitfile can be used to initialize the configurable logic 29 / 52 EEL6935 30 / 52 Bitfile modification • Update software binaries to utilize HW for loops • Replace original software instruction for loop to a jump to HW initializing code β« Initializing code sends HW enable signal through Memory mapped register β« Code followed up with microprocessor power down trigger β« Upon finishing HW asserts completion signal causing a software interrupt ο Software interrupt wakes the microprocessor β« Jump instruction at the end of the hardware initialization code to the end of the original software loop EEL6935 31 / 52 EEL5935 Tool : Performance and Area overhead • Typical tools for De-compilation, synthesis, and Place and Route need huge LSF machines • Designed tool very light weight and geared towards partitioning coprocessor Data Size: Memory required for the tool execution Time : Execution time of each tool considering 60MHz clock and 1.5 cycle/Instruction EEL6935 Results Definitions: Loop Time Perc: Percentage of total software time, spent in the implemented loops Loop Size Perc: Percentage of the total instructions that the loop required Ideal Speedup: Speedup assuming HW implemented loops are executing in Zero time. Sw Loop Time: Time required by the loop if completely in software HW Loop Time: Time when loop implemented in HW 32 / 52 EEL6935 33 / 52 Conclusion • Dynamic HW/SW Partitioning offers advantages over traditional approach: β« Transparent i.e. Benefits of partitioning even with regular software flows β« Can adapt as per actual usage profile β« Upto 2.6 average speedup EEL6935 34 / 52 Areas of Improvement of Future Work • Power required by the partitioning module and the HW running specified as 10-20% of total power β« Power data for individual modules not presented • Realistic loops have sequential logic and may not be always single cycle β« Extend implementation on sequential logic compatible CLF β« Extend to include mutli cycle loops • Applications seem too biased especially “url”, with 80% loop time with just 0.1% loop area overhead • Place and Route, synthesis would have been difficult to do on single partitioning chip: β« Today as on 2013 it should be possible to interface the modules with the cloud computing. I would rather have a complex algorithm run to get best suited partition profile, on a cloud network than to try small tricks with the lean co-processors ο This would be application dependent A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning Roman Lysecky, Frank Vahid, University of California, Riverside Design, Automation and Test in Europe Conference and Exhibition (DATE’05) EEL6935 36 / 52 Motivation (1/2) • Hard-Processor β« Pros: Performance β« Cons: Flexibility • Soft-processors β« Pros: Flexibility β« Cons: Degraded Performance and Energy Consumption Can we leverage benefits of both using Warp Processing ? EEL6935 37 / 52 Motivation (2/2) • Warp Processing : Technique for β« optimizing a software application ο by dynamically and transparently re-implementing “critical software kernels” as custom circuits in onchip configurable logic • Study MicroBlaze based Warp processing System to β« Eliminate the performance and energy overhead of a soft-processor compared to a hard-processor EEL6935 38 / 52 FPGA single-chip Systems: Hard-core Vs Soft-core • Hard-core β« Excellent Packaging and communication with the FPGA β« Lower Power and Higher Performance than Soft-core β« E.g. : Triscend, Atmel, Altera’s Excalibur, Virtex* with PowerPCs • Soft-core β« Lower Part cost β« Extreme Flexibility during design process ο Adding custom instructions or including/ excluding particular data-path coprocessors ο Quickly integrate the processor within a FPGA ο Varying number of processors as per need β« E.g. NIOS, NIOS II …, Picoblaze, Microblaze Use Hardware / Software Partitioning Techniques to alleviate Power and Performance overhead of Soft Processors EEL6935 39 / 52 MicroBlaze Soft Processor Core Specify system Architecture and configure MicroBlaze Xilinx Platform Studio Tools Synthesizes design Bitstream MicroBlaze – 32bit softcore by Xilinx LMB – Local Memory Bus BRAM – Block RAM : User Defined Size OPB – On-Chip Peripheral Bus Application Compile Final System Bitstream Software Libraries EEL6935 40 / 52 Key features of MicroBlaze • User Configurable options β« Tailor processor’s functionality as per the design need β« Configurable Instructions and data caches β« Incorporate additional hardware: ο Hardware multiplier ( mul instructions) ο Hardware Divider ( div instructions ) ο Barrel Shifter (bs and bsi instructions) ο Hardware bit manipulations and absolute plus EEL6935 42 / 52 Applications analyzed • brev (Powerstone benchmark suite) β« Critical kernel performs bit reversal heavily relying on shift operations ο Software only Implementation (without mul or barrel shift) ο N-bit shift by using n-successive add operations ο Configurable Hardware implementation ο 2.1X speed up • “matmul” β« Critical Region : Matrix multiplication ο Hardware Multiplier provides 1.3X speedup EEL6935 43 / 52 MicroBlaze-based Warp Processor Identify Critical Kernels in execution time WCLA – Warp Configurable Logic Architecture Implement critical Kernels in WCLA as cutom HW EEL6935 44 / 52 Warp Configerable Logic Architecture for Dynamic HW/ SW Partitioning DADG: Data Address Generator • Used for any memory accesses to/for Configurable logic LCH: Loop Control Hardware • Handles loops and controls executions Reg 0, Reg 1 Reg 2: 1. i/p to CLF /or MAC (as per mapping) 2. Outputs from the configurable logic stored in Registers EEL6935 45 MicroBlaze Multi-processor warp processing system • Mutliple Soft-cores may be incorporated within a single FPGA β« Limited only by the FPGA Size • Multi-processor Warp Processing system may share a common DPM and WLCA and HW/SW partitioning may be done in round robin manner β« No Overhead due to additional DPMs • Partitioning tools may be implemented as software tasks running in one of the cores / 52 EEL6935 46 / 52 Experimental Setup • Execution Time and Power studied • Embedded systems applications chosen from Powerstone and EEMBC benchmark suites studies • MicroBlaze processor core implemented on Spartan3 FPGA β« Barrel Shifter and Multiplier configured in Hardware β« Note: MicroBlaze max frequency 85MHz; However FPGA circuits may run upto 250MHz EEL6935 47 / 52 Profiling Simulation Soft App 2 MicroBlaze Soft App 1 Soft App n Xilinx Microprocessor Debug Engine Inst Trace 1 Inst Trace 2 Simulate Onchip Profiler Behavior Critical Region Inst Trace n EEL6935 Energy Equations Total Energy Consumed = πΈπ‘ππ‘ππ Energy Consumed by HW in Configurable Logic = πΈπ»π Energy Consumed by Microblaze = πΈππ΅ 48 / 52 EEL6935 49 / 52 Performance / Power Simulation Execution Traces of critical regions Critical Regions Synopsys Design Compiler Synthesis UMC 0.18um Library VHDL Execute HW Circuits (VHDL model for WCLA) for each partitioned Critical Region Determine final application performance Configurable HW Power MicroBlaze and system Component (excluding WCLA) Xilinx XPower Dynamic Power Static Power MicroBlaze Power EEL6935 50 / 52 Results ARM execution determined using Simple Scalar EEL6935 51 / 52 Conclusion • Warp processors (with soft-core), by pushing critical software kernels to the CFG can provide β« Flexibility of the Soft-core ο Due to soft-core implementation β« Competitiveness of a Hard-core processors (as ARM) ο Performance of the order of the Hard-core ο By leveraging special Configured HW ο 5.8X (average) improvement (with MicroBlaze) ο Eliminates Energy Overhead ο By faster execution due to dedicated hardware and trimming down the soft-processor to perfectly fit design needs ο Average Energy reduction ~ 57% β« Opened Avenues for Soft-core processors which would not have been feasible previously due to energy/performance EEL6935 52 / 52 Areas of Improvement & Future Work • Real processing systems do not just do a execute just a single application at a time β« For realistic data, multiple applications should be run simultaneously β« Explore Parallel Processing architecture further • Power Estimation Data β« Estimation is good ο It would be good to see real data as well • Online Profiler has a dozen entries β« Number of entries should be configurable to avoid local maxima • Instead of simplified configurable logic fabric, how about using underlying FPGA physical fabric • Algorithm to come up with re-partitioning time interval should be worked up Questions EEL6935 54 / 52 EEL5935 Design Goals
