Built-In Self-Test
Outline
•
•
•
•
•
•
•
•
•
Motivation for BIST
Testing SoC with BIST
Test per Scan and Test per Clock
HW and SW based BIST
Hybrid BIST
Pseudorandom test generation with LFSR
Exhaustive and pseudoexhaustive test generation
Response compaction methods
Signature analyzers
Technical University Tallinn, ESTONIA
Testing Challenges: SoC Test
Cores have to be tested on chip
Source: Elcoteq
Source: Intel
Technical University Tallinn, ESTONIA
Self-Test in Complex Digital Systems
Test architecture components:
• Test pattern source & sink
• Test Access Mechanism
• Core test wrapper
SoC
SoC
SRAM
Test Access
Mechanism
Peripheral
Component
Interconnect
Wrapper
CPU
SRAM
ROM
Core
Under
Test
Source
Sink
Test Access
Mechanism
DRAM
MPEG
UDL
Solutions:
• Off-chip solution
– need for external ATE
• Combined solution
– mostly on-chip, ATE
needed for control
• On-chip solution
– BIST
Technical University Tallinn, ESTONIA
Self-Test in Complex Digital Systems
SoC
SoC
SRAM
Peripheral
Component
Interconnect
Wrapper
CPUSource
Core
Under
Test
SRAM
ROM
Sink
DRAM
MPEG
UDL
Test architecture components:
• Test pattern source & sink
• Test Access Mechanism
• Core test wrapper
Solutions:
• Off-chip solution
– need for external ATE
• Combined solution
– mostly on-chip, ATE
needed for control
• On-chip solution
– BIST
Technical University Tallinn, ESTONIA
What is BIST
• On circuit
– Test pattern generation
Test Pattern Generation (TPG)
– Response verification
• Random pattern
generation,
very long tests
• Response compression
BIST
Control Unit
IC
Circuitry Under Test
CUT
Test Response Analysis (TRA)
Technical University Tallinn, ESTONIA
SoC BIST
Optimization:
Embedded Tester
Core 1
Test
Controller
BIST
Test access
mechanism
-
testing time 
Core 2
memory cost 
power consumption 
BIST
hardware cost

test quality 
Tester
Memory
BIST
Core 3
BIST
Core 4
BIST
Core 5
System on Chip
Technical University Tallinn, ESTONIA
Built-In Self-Test
• Motivations for BIST:
–
–
–
–
–
–
–
Need for a cost-efficient testing (general motivation)
Doubts about the stuck-at fault model
Increasing difficulties with TPG (Test Pattern Generation)
Growing volume of test pattern data
Cost of ATE (Automatic Test Equipment)
Test application time
Gap between tester and UUT (Unit Under Test) speeds
• Drawbacks of BIST:
–
–
–
–
Additional pins and silicon area needed
Decreased reliability due to increased silicon area
Performance impact due to additional circuitry
Additional design time and cost
Technical University Tallinn, ESTONIA
BIST in Maintenance and Repair
• Useful for field test and diagnosis (less expensive
than a local automatic test equipment)
• Disadvantages of software tests for field test and
diagnosis (nonBIST):
– Low hardware fault coverage
– Low diagnostic resolution
– Slow to operate
• Hardware BIST benefits:
–
–
–
–
Lower system test effort
Improved system maintenance and repair
Improved component repair
Better diagnosis
Technical University Tallinn, ESTONIA
BIST Techniques
•
•
•
BIST techniques are classified:
– on-line BIST - includes concurrent and nonconcurrent techniques
– off-line BIST - includes functional and structural approaches
On-line BIST - testing occurs during normal functional operation
– Concurrent on-line BIST - testing occurs simultaneously with normal
operation mode, usually coding techniques or duplication and comparison
are used
– Nonconcurrent on-line BIST - testing is carried out while a system is in
an idle state, often by executing diagnostic software or firmware routines
Off-line BIST - system is not in its normal working mode, usually
– on-chip test generators and output response analyzers or microdiagnostic
routines
– Functional off-line BIST is based on a functional description of the
Component Under Test (CUT) and uses functional high-level fault models
– Structural off-line BIST is based on the structure of the CUT and uses
structural fault models (e.g. SAF)
Technical University Tallinn, ESTONIA
General Architecture of BIST
•
– Test pattern generator
(TPG)
– Test response
analyzer (TRA)
Test Pattern Generation (TPG)
•
BIST
Control Unit
Circuitry Under Test
CUT
•
Test Response Analysis (TRA)
BIST components:
TPG & TRA are usually
implemented as linear
feedback shift registers
(LFSR)
Two widespread
schemes:
– test-per-scan
– test-per-clock
Technical University Tallinn, ESTONIA
Detailed BIST Architecture
Source: VLSI Test: Bushnell-Agrawal
Technical University Tallinn, ESTONIA
BIST: Test Generation Methods
Universal test sets
1. Exhaustive test (trivial test)
2. Pseudo-exhaustive test
Properties of exhaustive tests
1. Advantages (concerning the stuck at fault model):
- test pattern generation is not needed
- fault simulation is not needed
- no need for a fault model
- redundancy problem is eliminated
- single and multiple stuck-at fault coverage is 100%
- easily generated on-line by hardware
2. Shortcomings:
- long test length (2n patterns are needed, n - is the number of inputs)
- CMOS stuck-open fault problem
Technical University Tallinn, ESTONIA
Exhaustive and Pseudo-Exhaustive Testing
Exhaustive combinational fault model:
- exhaustive test patterns
- pseudoexhaustive test
patterns
- exhaustive output line
oriented test patterns
- exhaustive module
oriented test patterns
Technical University Tallinn, ESTONIA
BIST: Pseudoexhaustive Testing
Pseudo-exhaustive test sets:
– Output function verification
Output function verification
• maximal parallel testability
• partial parallel testability
4
– Module function verification
4
4
Module function verification
4
Primitive
polynomials
216 = 65536 >> 4x16 = 64
1111
0011
0101
F
&
Exhaustive
test
> 16
PseudoPseudoexhaustive exhaustive
parallel
sequential
Technical University Tallinn, ESTONIA
Testing ripple-carry adder
Output function verification (maximum parallelity)
Exhaustive test generation for n-bit adder:
Bad news:
Good news:
Bit number n - arbitrary The method is correct
Test length - always 8 (!) only for ripple-carry adder
1
2
3
4
5
6
7
8
c0
0
0
0
0
1
1
1
1
a0
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
0-bit testing
c1
0
0
0
1
0
1
1
1
a1
0
0
1
0
1
0
1
1
b1
0
1
0
0
1
1
0
1
c2
0
0
0
0
1
1
1
1
a2
0
0
1
1
0
0
1
1
b2
0
1
0
1
0
1
0
1
c3
0
0
0
1
0
1
1
1
…
1-bit testing 2-bit testing 3-bit testing … etc
Technical University Tallinn, ESTONIA
Pseudoexhaustive Test Optimization
Output function verification (partial parallelity)
F1
0011- 0
0101 01
F3
F2
F4
F5
010110
00 01 11
x1
x2
F1(x1, x2)
F2(x1, x3)
x3
F3(x2, x3)
F4(x2, x4)
x4
F5(x1, x4)
F6(x3, x4)
Exhaustive testing - 16
Pseudo-exhaustive, full parallel – 4 (not possible)
Pseudo-exhaustive, partially parallel - 6
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Combined Pseudo-Exhaustive-Random Testing
K1
PseudoRandom Test
K2
PE2
K3
PE3
PE4
Segmented
LFSR
Combined PE-PR Test
K4
Circuit with 4
cones
Technical University Tallinn, ESTONIA
Problems: Transistor Level Stuck-off Faults
NOR gate
VDD
Stuck-off
(open)
VDD
x2
y
yd
0
0
1
1
0
1
0
0
x1
x1
1
0
0
Y’
x2
x2
1
1
0
0
Y
x1
x1
x2
Y
x1
VSS
x2
VSS
No conducting path from VDD to VSS for “10”
Test sequence
is needed:
00,10
Technical University Tallinn, ESTONIA
Problems: Bridging Fault Sequentiality
Paradox:
264 input patterns (!)
for 32-bit accumulator
will be not enough.
A short will change the circuit
into sequential one,
and you will need because of that
265 input patterns
Y = F(x1, x2, x3)
Bridging fault
0
y
x1
1
&
x2
State q
&
x3
Y = F(x1, x2, x3,q)
Technical University Tallinn, ESTONIA
Built-In Self-Test
Test pattern
generator
BIST
Control
Test response
analysator
Scan Path
Initial test set:
CUT
Scan Path
.
.
.
Scan Path
•
•
Test per Scan:
Assumes existing scan
architecture
Drawback:
T1: 1100
T2: 1010
T3: 0101
T4: 1001
Test application:
1100 T 1010 T 0101T 1001 T
Number of clocks = (4 x 4) + 4 = 20
– Long test application time
Technical University Tallinn, ESTONIA
Built-In Self-Test
Test per Clock:
Combinational Circuit
Under Test
Scan-Path Register
•
Initial test set:
•
•
•
•
T1: 1100
T2: 1010
T3: 0101
T4: 1001
•
Test application:
•
1 10 0 1 0 1 0 01 01 1001
T1 T4 T3
•
T2
Number of clocks = 8 < 20
Technical University Tallinn, ESTONIA
Pattern Generation
•
•
•
•
•
•
•
Store in ROM – too expensive
Exhaustive – too long
Pseudo-exhaustive
Pseudo-random (LFSR) – Preferred method
Binary counters – use more hardware than LFSR
Modified counters
Test pattern augmentation ( Hybrid BIST)
 LFSR combined with a few patterns in ROM
Technical University Tallinn, ESTONIA
LFSR Based Testing: Some Definitions
• Exhaustive testing – Apply all possible 2n patterns to a circuit with
n inputs
• Pseudo-exhaustive testing – Break circuit into small, overlapping
blocks and test each exhaustively
• Pseudo-random testing – Algorithmic pattern generator that
produces a subset of all possible tests with most of the properties of
randomly-generated patterns
• LFSR – Linear feedback shift register, hardware that generates
pseudo-random pattern sequence
• BILBO – Built-in logic block observer, extra hardware added to
flip-flops so they can be reconfigured as an LFSR pattern generator
or response compacter, a scan chain, or as flip-flops
Technical University Tallinn, ESTONIA
Pattern Generation
Pseudorandom test generation by LFSR:
...
Xo
– Test pattern generator
– Signature analyzer
hn
h1
ho
• Using special LFSR registers
X1
...
Xn
LFSR
CUT
LFSR
• Several proposals:
– BILBO
– CSTP
• Main characteristics of LFSR:
– polynomial
– initial state
– test length
Technical University Tallinn, ESTONIA
Pseudorandom Test Generation
LFSR – Linear Feedback Shift Register:
Standard LFSR
x
x2
x3
x4
Modular LFSR
x
x2
x3
x4
Polynomial: P(x) = x4 + x3 + 1
Technical University Tallinn, ESTONIA
Pseudorandom Test Generation
LFSR – Linear Feedback Shift Register:
Why modular LFSR is useful for BIST?
x
x2
x3
x4
Test
responses
UUT
Test patterns
Polynomial: P(x) = x4 + x3 + 1
Instead of BILBO we have now CSTP architecture
Technical University Tallinn, ESTONIA
Problems with BIST: Hard to Test Faults
The main motivations
of using random
patterns are:
- low generation cost
- high initial efeciency
Problem: Low fault coverage
Pseudorandom
test window:
Patterns from LFSR:
1
2n-1
Fault Coverage
Hard
to test
faults
Dream solution: Find LFSR such that:
2n-1
1
Time
Hard
to test
faults
Technical University Tallinn, ESTONIA
Pseudorandom Test Generation
Scan-based BIST
Bit-flipping
BIST
H.-J. Wunderlich, G. Kiefer. Bit flipping BIST. Proc. ICCAD, Nov. 1996, pp.337-343.
Technical University Tallinn, ESTONIA
Pseudorandom Test Generation
Bit-fixing BIST
N.A. Touba, E.J. McCluskey. Bit-fixing in pseudorandom sequences for scan BIST. IEEE
Trans. on CAD of IC and Systems, Vol.20, No.4, Apr.2001.
Technical University Tallinn, ESTONIA
BILBO BIST Architecture
Working modes:
B1 B2
0 0
0 1
1 0
1 1
B1
B2
Normal mode
Reset
Test mode
Scan mode
Testing modes:
CC1:
LFSR 1 - TPG
LFSR 2 - SA
CC2:
LFSR 2 - TPG
LFSR 1 - SA
LFSR 1
CC1
B1
B2
LFSR 2
CC2
Technical University Tallinn, ESTONIA
Reconfiguration of the LFSR
Unit Under Test
MUX
LFSR FEEDBACK
Normal
&
Reset
From
Ti-1
Ti
&
&
OR
Test
&
Scan
Signature
analyzer
mode
B1
B2
Ti+1
&
0 1 2 3
MUX
4 working
modes
Technical University Tallinn, ESTONIA
To
Ti+2
Matrix Equation for Standard LFSR
Xn (t + 1)
Xn-1 (t + 1)
.
.
.
X3 (t + 1)
X2 (t + 1)
X1 (t + 1)
=
0 1
0
0 0
1
. .
.
. .
.
. .
.
0 0
0
0 0
0
1 hn-1 hn-2
X (t + 1) = Ts X (t)
x
…
…
…
…
…
0
0
.
.
.
1
0
h2
0
0
.
.
.
0
1
h1
Xn (t)
Xn-1 (t)
.
.
.
X3 (t)
X2 (t)
X1 (t)
(Ts is companion matrix)
x2
xn-1
xn
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Pseudorandom Test Generation
x2
x
Polynomial: P(x) =
X4 (t + 1)
0 1
X3 (t + 1)
0 0
=
X2 (t + 1)
0 0
X1 (t + 1)
1 h3
0
1
0
h2
x4 +
0
0
1
h1
x3 + 1
X4 (t)
X3 (t)
X2 (t)
X1 (t)
x4
x3
t
x
x2
x3
x4
t
x
x2
x3
x4
1
0
0
0
1
9
0
1
0
1
2
1
0
0
0
10
1
0
1
0
3
0
1
0
0
11
1
1
0
1
4
0
0
1
0
12
1
1
1
0
5
1
0
0
1
13
1
1
1
1
6
1
1
0
0
14
0
1
1
1
7
0
1
1
0
15
0
0
1
1
8
1
0
1
1
16
0
0
0
1
1 0 0
Technical University Tallinn, ESTONIA
Theory of LFSR: Primitive Polynomials
Properties of Polynomials:
• Irreducible polynomial – cannot be factored, is divisible
only by itself
• Irreducible polynomial of degree n is characterized by:
– An odd number of terms including 1 term x 4  x 2  1
– Divisibility into 1 + xk, where k = 2n – 1
x7 + 1
• Any polynomial with all even exponents can be factored and
hence is reducible
• An irreducible polynomial of degree n is primitive if it
divides the polynomial 1+xk for k = 2n – 1, but not for any
smaller positive integer k
Technical University Tallinn, ESTONIA
Theory of LFSR: Examples
Polynomials of degree n=3 (examples): k = 2n – 1= 23 – 1=7
Primitive polynomials:
x3  x 2  1
The polynomials will divide evenly the polynomial
x3  x  1
but not any one of k<7, hence, they are primitive
x7 + 1
They are also reciprocal: coefficients are 1011 and 1101
Reducible polynomials (non-primitive):
Primitive polynomial
x  1  ( x  1)( x  x  1)
3
2
The polynomials don’t divide
evenly the polynomial x7 + 1
x 3  x 2  x  1  ( x  1)( x 2  1)
Technical University Tallinn, ESTONIA
Theory of LFSR: Examples
Is
x4  x2 1
a primitive polynomial?
Irreducible polynomial of
degree n is characterized by:
- An odd number of terms
including 1 term?
Yes, it includes 3 terms
- Divisibility into 1 + xk,
where k = 2n – 1
No, there is remainder
x4  x2 1
is non-primitive?
Divisibility check:
x11  x 9  x 5  x 3
x 4  x 2  1 x15  1
x15  x13  x11
x13  x11  1
x13  x11  x 9
x9  1
x9  x7  x5
x7  x5  1
x7  x5  x3
x3  1
Technical University Tallinn, ESTONIA
Theory of LFSR: Examples
Simulation of the behaviour of LFSR by polynomial:
Primitive polynomials
x3  x  1
100
110
111
011
101
010
001
100
x
x2
x3
Technical University Tallinn, ESTONIA
Theory of LFSR: Examples
Comparison of test sequences generated:
Non-primitive polynomials
Primitive polynomials
x3  x  1
100
110
111
011
101
010
001
100
x  x 1
x3  1
x3  x 2  x  1
100
010
101
110
111
011
001
100
100
010
001
100
010
001
100
010
100
110
011
001
100
110
011
001
3
2
Technical University Tallinn, ESTONIA
Theory of LFSR: Examples
Reducible polynomial (non-primitive):
x 3  1  ( x  1)( x 2  x  1)
x3  1 x 1
100
010
001
100
1
1
x2  x 1
Multiplication of
two primitive
polynomials:
x2
x
01
10
11
01
Is
x2  x 1
x2  x 1
x2  x 1
x3  x 2  x
x 4  x3  x 2
x4  x2 1
x4  x2 1
a primitive polynomial?
Primitive polynomial
Technical University Tallinn, ESTONIA
Theory of LFSR: Examples
Non-primitive polynomial
Primitive polynomial
x4 + x2 + 1
x4 + x + 1
x
0001
1000
0100
1010
0101
0010
0001
x2
1001
1100
1110
1111
0111
0011
1001
x3
x4
0110
1011
1101
0110
x
0001
1000
1100
1110
1111
0111
x2
1011
0101
1010
1101
0110
0011
x3
x4
1001
0100
0010
0001
Technical University Tallinn, ESTONIA
Theory of LFSR: Examples
Zero generation:
Primitive polynomial
x4 + x + 1
x
x
x2
x3
x2
x3
x4
x4
1
0001
1000
1100
1110
1111
0111
1011
0101
1010
1101
0110
0011
1001
0100
0010
0001
The code 0000 is missing
0000
1000
1100
1110
1111
0111
1011
0101
1010
1101
0110
0011
1001
0100
0010
0001
0000
Technical University Tallinn, ESTONIA
Theory of LFSR: Primitive Polynomials
Table of primitive polynomials up to degree 31
Number of primitive
polynomials of
degree N
N
No
1
1
2
1
4
2
8
16
16
2048
32
67108864
N
1,2,3,4,6,7,15,22
5,11, 21, 29
10,17,20,25,28,31
9
23
18
8
12
13
14, 16
Primitive Polynomials
1 + X + Xn
1 + X2 + Xn
1 + X3 + Xn
1 + X4 + Xn
1 + X5 + Xn
1 + X7 + Xn
1 + X2 + X3 + X4 + Xn
1 + X + X3 + X4 + Xn
1 + X + X4 + X6 + Xn
1 + X + X3 + X4 + Xn
Technical University Tallinn, ESTONIA
Theory of LFSR: Primitive Polynomials
Examples of PP (exponents of terms):
n
1
2
other
0
1
3
4
5
1
1
2
6
1
7
8
1
6
0
0
0
0
0
0
5
1
n
9
10
other
4 0
3 0
11
12
13
2
7
4
0
4
3
3
1
0
0
14 12 11
1
0
2
0
15
0 16
1
5
0
3
x3 + x + 1
x13 + x4 + x3 + x + 1
Technical University Tallinn, ESTONIA
BIST: Fault Coverage
Pseudorandom Test generation by LFSR:
Motivation of using
LFSR:
Test Pattern Generation (TPG)
- low generation cost
- high initial efeciency
Fault Coverage
BIST
Control Unit
Circuitry Under Test
CUT
Test Response Analysis (TRA)
Drawback: 100% fault coverage is difficult to achieve
Time
Technical University Tallinn, ESTONIA
© Raimund Ubar
Achilles, tortoise and fault coverage
Patterns
Truth table for adder:
Patterns
...
1
2
Adder
0
264
64
00…000
00…001
00…010
00...010
…
Possible functions
01 0 1 0 1…101
00 1 1 1 0…011
00 1 0 0 1…101
11…111
00 0 0 0 0…111
Correct
function
Test quality:
Half way
50%
tested
…
First pattern
Start
2
264
To win the tortoise
and to achieve 100%
in test
are both infeasible
100%
0% 93,75%
87,5%
4.
3.
First
pattern
75%
Second
pattern
50%
45
BIST: Fault Coverage
Pseudorandom Test generation by LFSR:
Motivation of using
LFSR:
- low generation cost
- high initial efeciency
Reasons of the high initial efficiency:
A circuit may implement
2
2n
functions
A test vector partitions the functions into 2 equal
sized equivalence classes (correct circuit in one of
them)
The second vector partitions into 4 classes etc.
Fault Coverage
After m patterns the fraction of functions
distinguished from the correct function is
1
m
2
2 2  1 i 1
n
2 n i
, 1  m  2n
Time
Technical University Tallinn, ESTONIA
BIST: Structural Approach to Test
Testing of structural faults:
1
2
Combinational
circuit
under test
n
Not tested
3. patttern
faults
4. pat.
Fault coverage
2. pattern
100%
Faults
covered by
1. pattern
Number of
patterns
4
Technical University Tallinn, ESTONIA
BIST: Two Approaches to Test
Testing of
functions:
100%
0%
Testing of
faults:
93,75%
4. pat.
Faulty
functions
covered by
1. pattern
100% will be
reached only
after 2n test
patterns
Not tested
3. patttern
faults
87,5%
2. pattern
Faults
covered by
1. pattern
3. pattern
75%
Faulty
functions
covered by
2. pattern
100%
Testing of
functions
50%
4. pat.
Testing of
faults
100% will be reached
when all faults from
the fault list are
covered
Technical University Tallinn, ESTONIA
Problems with BIST: Hard to Test Faults
The main motivations
of using random
patterns are:
- low generation cost
- high initial efeciency
Problem: Low fault coverage
Pseudorandom
test window:
Patterns from LFSR:
1
2n-1
Fault Coverage
Hard
to test
faults
Dream solution: Find LFSR such that:
2n-1
1
Time
Hard
to test
faults
Technical University Tallinn, ESTONIA
Deterministic Synthesis of LFSR
Generation of the polynomial and seed for the given test sequence
Creation of the
shortest bit-stream:
Expected shortest
LFSR sequence:
10010 1 01111
01111 (4)
Given test
sequence:
(1)
(2)
(3)
(4)
100x0 1
x1010
10101
01111
0
This deterministic test set is
generated by ATPG
Shift
Seed
1
0
1
0
0
1
0111
1011
0101 (3)
1010 (2)
0101
0010 (1)
Technical University Tallinn, ESTONIA
Deterministic Synthesis of LFSR
Generation of the polynomial and seed for the given test sequence
Expected shortest
LFSR sequence:
01111 (4)
1 0111
0 1011
1 0101 (3)
0 1010 (2)
0 0101
1 0010 (1)
System of linear equations:
01111
10111
01011
10101
01010
00101
x1
x2
x3
x4
x5
x
=
1
0
1
0
0
1
We are looking for the values of xi
:
x
x1
x2
x2
x3
x3
x4
x4
x5
Technical University Tallinn, ESTONIA
x5
Deterministic Synthesis of LFSR
Generation of the polynomial and seed for the given test sequence
Solving the equation by Gaussian
System of linear equations:
elimination with swapping of rows
1 01111
1
x1
Rows:
Results:
2
3
4
5
6
10111
x2
01011 x x
3
10101
x4
01010
x5
00101
=
0
1
0
0
1
01000
0
x1
10000
1
x2
00100 x x = 0
3
00010
0
x4
00001
1
x5
00001
1
1,2,4,6
4,6
1,3
2,4
1,3,6
Polynomial: x5 + x + 1 Seed: 01111
Solution:
x1
x
x2
x3
x4
x5
x5
x1 x2 x3 x4 x5
1 0 0 0 1
Technical University Tallinn, ESTONIA
Deterministic Synthesis of LFSR
Embedding deterministic test patterns into LFSR sequence:
Polynomial: x5 + x + 1 Seed: 01111
LFSR sequence:
x1
x
x2
Given
deterministic
test
sequence:
x4
x3
(1)
(2)
(3)
(4)
100x0
x1010
10101
01111
x5
x5
(1)
(2)
(3)
(4)
(5)
(6)
(7)
01111 (4)
10111
01011
10101 (3)
01010 (2)
00101
10010 (1)
Technical University Tallinn, ESTONIA
Which Test Patterns to Select for as HTF?
Frequences of fault detection
Fault detection
frequences for the
given random test
sequence
Easily
detectable
faults
Hard-to-test
faults (HTF)
Different faults
Technical University Tallinn, ESTONIA
Other Problems with Pseudorandom Test
The main motivations of
using random patterns
are:
- low generation cost
- high initial efeciency
Problem: low fault coverage
&
1
LFSR
Decoder
Fault Coverage
Counter
Reset
Time
If Reset = 1 signal has probability 0,5 then
counter will not work and
1 for AND gate may never be produced
Technical University Tallinn, ESTONIA
Sequential BIST
A DFT technique of BIST for sequential circuits is proposed
The approach proposed is based on all-branches coverage metrics
which is known to be more powerful than all-statement coverage
S0
S1
S0
A=1
A= 0
S5
S1
S3
A=1
S5
S1
S2
B=1
S4
B=0
S3
A=1
A= 0
A= 0
S2
B=0
S0
S2
B=1
S4
B=0
S3
B=1
S4
Technical University Tallinn, ESTONIA
S5
Sequential BIST
Digital System
•
reset
FSM
clock
test/normal
mode (TM)
•
control signals
primary
inputs
status
signals
MUX
Datapath
masked
status bits
primary outputs
observation
points
•
Status signals entering the
control part are made
controllable
In the test mode we can force
the UUT to traverse all the
branches in the FSM state
transition graph
The proposed idea of
architecture requires small
device area overhead since a
simple controller can be
implemented to manipulate
the control signals
Technical University Tallinn, ESTONIA
Testability of Design Types
T (Control logic) < T (Data path)
Control Part
y1
R1
y3
a

M1
+

M2
e
M3

*
y4
c
b

IN
y2
Solutions:
Scan-Path design strategie
Data-Flow design
R2

d
Data Part
Technical University Tallinn, ESTONIA
BIST: Different Techniques
Pseudorandom Test generation by LFSR:
Full identification is
achieved only after 2n input
combinations have been
tried out (exhaustive test)
1
2
2n
m
2

1
2 n 1
,
i 1
1  m  2n
A better fault model
(stuck-at-0/1)
may limit the number of
partitions necessary
Pseudorandom testing of sequential circuits:
The following rules suggested:
• clock-signals should not be random
• control signals such as reset, should be activated
with low probability
• data signals may be chosen randomly
Microprocessor testing
•
•
A test generator picks randomly an instruction
and generates random data patterns
By repeating this sequence a specified number of
times it will produce a test program which will
test the microprocessor by randomly exercising
its logic
Technical University Tallinn, ESTONIA
BIST: Weighted pseudorandom test
Calculation of signal probabilities:
PI1
Probability of detecting the fault
at the input 3 of the gate G:
1
1
PI2
PI3
1
2
&
G
3
PI4
PI5
PI6
1
1
For PI1 :
P = 0.15
For PI2 and PI3 :
P = 0.6
For PI4 - PI6 :
P = 0.4
1
1) equal probabilities (p = 0.5):
P = 0.5  (0.25 + 0.25 + 0.25)  0.53 =
= 0.5  0.75  0.125 =
= 0.046
2) weighted probabilities:
P = 0.85 
 (0.6  0.4 + 0.4  0.6 + 0.62) 
 0.63 =
= 0.85  0.84  0.22 =
= 0.16
Technical University Tallinn, ESTONIA
BIST: Weighted pseudorandom test
Hardware implementation of weight generator
LFSR
&
&
1/16
Weight select
Desired weighted value
&
1/8
1/4
MUX
Scan-IN
Technical University Tallinn, ESTONIA
1/2
BIST: Weighted pseudorandom test
Problem: random-pattern-resistant faults
Solution: weighted pseudorandom
testing
NDI - number of primary inputs
for each gate determined by
the back-trace cone
The probabilities of pseudorandom signals
are weighted, the weights are determined by
circuit analysis
Faults to
be tested
1
NDI - relative measure of the
number of faults to be
detected through the gate
NCV
&
Propagated
faults
NDII
NCV – non-controlling value
The more faults that must be tested
through a gate input, the more the other
inputs should be weighted to NCV
I
&
NDIG
Technical University Tallinn, ESTONIA
G
BIST: Weighted pseudorandom test
1
Faults
to be
tested
NCV
R I = NDIG / NDII
Propagated
faults
R I - the desired ratio of the
NCV to the controlling value
for each gate input
&
NCV - noncontrolling value
The more faults that must be tested
through a gate input, the more the other
inputs should be weighted to NCV
NDII
I
&
NDIG
Technical University Tallinn, ESTONIA
G
BIST: Weighted pseudorandom test
Example:
R 1 = NDIG / NDII = 6/1 = 6
PI
R 2 = NDIG / NDII = 6/2 = 3
1
PI
2
&
PI
3
PI
PI
PI
G
R 3 = NDIG / NDII = 6/3 = 2
More faults must be detected
through the third input than
through others
This results in the other inputs
being weighted more heavily
towards NCV
Technical University Tallinn, ESTONIA
BIST: Weighted pseudorandom test
Calculation of signal weights:
R2=3
W02 = 1
W12 = 3
R1=6
W01 = 1
W11 = 6
PI
W0, W1 - weights of the signals
1
PI
PI
&
2
G
Calculation of W0, W1
3
PI
PI
PI
W0G = 1
W1G = 1
R3=2
W03 = 1
W13 = 2
Function
AND
NAND
OR
NOR
WOI
WOG
W1G
RI  WOG
RI  W1G
W1I
RI  W1G
RI  WOG
W1G
WOG
Technical University Tallinn, ESTONIA
BIST: Weighted pseudorandom test
Calculation of signal weights:
R1=1
W01 = 6
W11 = 1
R1=2
W01 = 2
W11 = 3
PI1
PI2
PI3
1
W01 = 1
W11 = 6
1
1
&
2
G
Backtracing from all the
outputs to all the inputs
of the given cone
Weights are calculated for
all gates and inputs
3
R1=3
W01 = 3
W11 = 2
PI4
PI5
PI6
W02 = 1
W12 = 3
1
Function
OR
NOR
WOI
RI  WOG
RI  W1G
W03 = 1
W13 = 2
Technical University Tallinn, ESTONIA
W1I
W1G
WOG
BIST: Weighted pseudorandom test
Calculation of signal probabilities:
R1=1
W01 = 6
W11 = 1
R1=2
W01 = 2
W11 = 3
PI1
PI2
PI3
1
1
1
&
2
G
3
R1=3
W01 = 3
W11 = 2
PI4
PI5
PI6
1
PI1 :
W0 = 6 W1 = 1
P1 = 1/7 = 0.15
PI2 and PI3 : W0 = 2 W1 = 3
P1 = 3/5 = 0.6
PI4 - PI6 :
P1 = 2/5 = 0.4
W0 = 3 W1 = 2
Technical University Tallinn, ESTONIA
BIST: Weighted pseudorandom test
Calculation of signal probabilities:
PI
Probability of detecting the fault
at the input 3 of the gate G:
1
1
PI
PI
1
2
&
G
3
PI
PI
PI
1
1
For PI1 :
P1 = 0.15
For PI2 and PI3 :
P1 = 0.6
For PI4 - PI6 :
P1 = 0.4
1
1) equal probabilities (p = 0.5):
P = 0.5  (0.25 + 0.25 + 0.25)  0.53 =
= 0.5  0.75  0.125 =
= 0.046
2) weighted probabilities:
P = 0.85 
 (0.6  0.4 + 0.4  0.6 + 0.62) 
 0.63 =
= 0.85  0.84  0.22 =
= 0.16
Technical University Tallinn, ESTONIA
BIST: Response Compression
Pi-1
1. Parity checking
m
P( R)  ( ri ) mod 2
Test
UUT
i 1
2. One counting
ri
T
m
P ( R )   ri
i 1
3. Zero counting
m
P ( R )   ri
Test
UUT
ri
Counter
i 1
Technical University Tallinn, ESTONIA
BIST: Response Compression
ri
4. Transition counting
a) Transition 01
&
Test
UUT
m
P ( R )   (ri 1ri )
T
ri-1
i2
ri
b) Transition 10
m
P ( R )   (ri 1 ri )
i 2
&
Test
UUT
T
ri-1
5. Signature analysis
Technical University Tallinn, ESTONIA
Pseudorandom Test Generation
LFSR – Linear Feedback Shift Register:
Standard LFSR
x
x2
x3
x4
Modular LFSR
x
x2
x3
x4
Polynomial: P(x) = x4 + x3 + 1
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
Signature analyzer:
Standard LFSR
UUT
1
x
x2
x4
x3
Modular LFSR
Response
string
1
x
x4
x2
x3
Response in compacted
by LFSR
The content of LFSR after
test is called signature
Polynomial: P(x) = 1 + x3 + x4
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
Parallel Signature Analyzer:
Single Input Signature Analyser
UUT
x4
x2
x
1
x2
x
1
x3
x4
x3
UUT
Multiple Input Signature
Analyser (MISR)
Technical University Tallinn, ESTONIA
Theory of LFSR
The principles of CRC (Cyclic Redundancy Coding) are used
in LFSR based test response compaction
Coding theory treats binary strings as polynomials:
R = rm-1 rm-2 … r1 r0
-
m-bit binary sequence
R(x) = rm-1 xm-1 + rm-2 xm-2 + … + r1 x + r0
-
polynomial in x
Example:
11001
 R(x) = x4 + x3 + 1
Only the coefficients are of interest, not the actual value of x
However, for x = 2, R(x) is the decimal value of the bit string
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
Arithmetic of coefficients:
- linear algebra over the field of 0 and 1: all integers mapped into either 0 or 1
- mapping: representation of any integer n by the remainder resulting from
the division of n by 2:
n = 2m + r, r  { 0,1 }
or
r  n (modulo 2)
Linear - refers to the arithmetic unit (modulo-2 adder), used in CRC
generator (linear, since each bit has equal weight upon the output)
Examples:
x4 + x 3
+ x + 1
+ x4
+ x2 + x
x3 + x2
+ 1
x4 + x 3
 x + 1
+ x + 1
x5 + x 4
+ x2 + x
x4 + x 3
+ x + 1
x5
+ x3 + x2
+ 1
Technical University Tallinn, ESTONIA
Theory of LFSR
Characteristic Polynomials:

G ( x)  c0  c1 x  c2 x 2  ...  cm x m  ...   cm x m
m 0
Multiplication of
polynomials
x2  x 1
x2 1
x2  x 1
x 4  x3  x 2
x 4  x3
 x 1
Technical University Tallinn, ESTONIA
Theory of LFSR
Characteristic Polynomials:

G ( x)  c0  c1 x  c2 x 2  ...  cm x m  ...   cm x m
m 0
Divider
x2 1
x2  x 1
x 4  x3
x4
Division of
polynomials
Quotient
1
 x2
x3  x 2
1
x3
x
x2  x 1
x2
1
x
Dividend
Remainder
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
Division of one polynomial P(x) by another
G(x) produces a quotient polynomial Q(x),
and if the division is not exact, a remainder
polynomial R(x)
Example:
P( x)
R( x)
 Q( x) 
G ( x)
G ( x)
2
P( x)
x7  x3  x
x
1
3
2
 5
 x  x 1 5
3
G ( x) x  x  x  1
x  x3  x  1
Remainder R(x) is used as a check word in data transmission
The transmitted code consists of the message P(x) followed by the check word R(x)
Upon receipt, the reverse process occurs: the message P(x) is divided by known
G(x), and a mismatch between R(x) and the remainder from the division indicates
an error
Technical University Tallinn, ESTONIA
Fault Tolerant Communication System
Initial code
P(x)
Check-bits
generator
Sender
R(x)
Error
correction
code
P( x)
R( x)
 Q( x) 
G ( x)
G ( x)
P(x).R(X)
Error
P(x)/G(X) indication
R(x)
Receiver
Checker
P’(x)
Error
correction
(restoring)
P(x)
Received
correct code
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
In signature testing we mean the use of CRC
encoding as the data compressor G(x) and
the use of the remainder R(x) as the signature
of the test response string P(x) from the UUT
Signature is the CRC code word
Example:
G(x)
P( x)
R( x)
 Q( x) 
G ( x)
G ( x)
= Q(x) = x2 + 1
101
101011
P( x)
x7  x3  x
 5
G ( x) x  x 3  x  1
10001010
101011
P(x)
00100110
101011
0 0 1 1 0 1 = R(x) = x3 + x2 + 1
Signature
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
G(x)
x1
x2
IN: 01 010001
x3
x4
x5
Shifted into LFSR
P(x)
Compressor
x5 x4 x3 x2 x1
The division process can
be mechanized using LFSR
The divisor polynomial G(x)
is defined by the feedback
connections
Shift creates x5 which is
replaced by x5 = x3 + x + 1
101
G(x)
101011
P( x)
x x x
 5
G ( x) x  x 3  x  1
7
10001010
101011
3
x5
00100110
101011
Response
P(x)
0 0 1 1 0 1 = R(x) = x3 + x2 + 1
Signature
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
Aliasing:
Response
UUT
L
All possible responses
k  2L
SA
N
L - test length
N - number of stages in
Signature Analyzer
All possible signatures
k  2N
Faulty
response
Correct
response
N << L
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
Aliasing:
Response
UUT
L
k  2L
-
N - number of stages in
Signature Analyzer
N
number of different possible responses
No aliasing is possible for those strings with
represented by polynomials of degree
polynomial of LFSR
2 LN  1
L - test length
SA
-
L-N
N-1
leading zeros since they are
that are not divisible by characteristic
000000000000000 ... 00000 XXXXX
aliasing is possible
Probability of aliasing:
2L N  1
P L
2 1
L
L  1
1
P N
2
Technical University Tallinn, ESTONIA
N
BIST: Signature Analysis
Parallel Signature Analyzer:
Single Input Signature Analyser
UUT
x4
x2
x
1
x2
x
1
x3
x4
x3
UUT
Multiple Input Signature
Analyser (MISR)
Technical University Tallinn, ESTONIA
BIST: Signature Analysis
Signature calculating for multiple outputs:
LFSR - Test Pattern Generator
LFSR - Test Pattern Generator
Combinational circuit
Combinational circuit
Multiplexer
Multiplexer
LFSR - Signature analyzer
LFSR - Signature analyzer
Technical University Tallinn, ESTONIA
BIST: Joining TPG and SA
LFSR
1
UUT
Response string for
Signature Analysis
x2
x
FF
FF
x3
FF
x4
FF
Test Pattern (when generating tests)
Signature (when analyzing test responses)
Technical University Tallinn, ESTONIA
BIST Architectures
General Architecture of BIST
•
Test Pattern Generation (TPG)
•
BIST
Control Unit
Circuitry Under Test
•
CUT
•
Test Response Analysis (TRA)
BIST components:
– Test pattern generator (TPG)
– Test response analyzer (TRA)
– BIST controller
A part of a system (hardcore)
must be operational to execute a
self-test
At minimum the hardcore usually
includes power, ground, and
clock circuitry
Hardcore should be tested by
–
–
external test equipment or
it should be designed selftestable by using various forms of
redundancy
Technical University Tallinn, ESTONIA
BIST Architectures
Test per Clock:
Joint TPG and SA:
Disjoint TPG and SA:
BILBO
LFSR - Test Pattern Generator
CSTP - Circular Self-Test
Path:
LFSR - Test Pattern Generator
& Signature analyser
Combinational circuit
Combinational circuit
LFSR - Signature analyzer
Technical University Tallinn, ESTONIA
BIST: Circular Self-Test Architecture
Circuit Under Test
FF
FF
FF
Technical University Tallinn, ESTONIA
BIST: Circular Self-Test Path
CSTP
CSTP
CC
CC
CSTP
CC
R
R
CC
CSTP
CC
CSTP
Technical University Tallinn, ESTONIA
BIST Embedding Example
LFSR1
LFSR2
CSTP
M1
M2
M4
M3
MUX
Concurrent
testing:
M5
BILBO
MISR1
LFSR, CSTP  M2  MISR1
M2  M5  MISR2 (Functional BIST)
CSTP  M3  CSTP
LFSR2  M4  BILBO
MUX
M6
MISR2
Technical University Tallinn, ESTONIA
BIST Architectures
STUMPS:
LOCST: LSSD On-Chip Self-Test
Self-Testing Unit Using MISR
and Parallel Shift Register
Sequence Generator
Scan Path
BS
BS
Test Pattern Generator
CUT
...
Scan chain
Scan chain
CUT
CUT
TPG
Test
Controller
SI
MISR
SA
IC
Technical University Tallinn, ESTONIA
SO
Error
Scan-Based BIST Architecture
PS – Phase shifter
Scan-Forest
Scan-Trees
Scan-Segments (SC)
Weighted scanenables for SS
Compactor - EXORs
Copyright: D.Xiang 2003
Technical University Tallinn, ESTONIA
Software BIST
Software based test generation:
SoC
CPU Core
ROM
LFSR1: 001010010101010011
N1: 275
load (LFSRj);
for (i=0; i<Nj; i++)
...
end;
Core j
LFSR2: 110101011010110101
N2: 900
...
Core j+1
Core j+...
To reduce the hardware
overhead cost in the BIST
applications the hardware LFSR
can be replaced by software
Software BIST is especially
attractive to test SoCs, because
of the availability of computing
resources directly in the system
(a typical SoC usually contains
at least one processor core)
The TPG software is the same for all cores and is stored as a single copy
All characteristics of the LFSR are specific to each core and stored in the ROM
They will be loaded upon request.
For each additional core, only the BIST characteristics for this core have to be stored
Technical University Tallinn, ESTONIA
Problems with BIST
Problems:
•
•
•
•
Very long test
application time
Low fault
coverage
Area overhead
Additional delay
Possible solutions
Fault Coverage
•
•
Time
•
Weighted
pseudorandom test
Combining
pseudorandom test
with deterministic data
– Multiple seed
– Bit flipping
Hybrid BIST
Fault Coverage
The main motivations of
using random patterns
are:
- low generation cost
- high initial efeciency
Time
Technical University Tallinn, ESTONIA
Problems with BIST: Hard to Test Faults
The main motivations
of using random
patterns are:
- low generation cost
- high initial efeciency
Problem: Low fault coverage
Pseudorandom
test window:
Patterns from LFSR:
1
2n-1
Fault Coverage
Hard
to test
faults
Dream solution: Find LFSR such that:
2n-1
1
Time
Hard
to test
faults
Technical University Tallinn, ESTONIA
Hybrid Built-In Self-Test
Deterministic patterns
Pseudorandom
SoC
patterns
ROM
...
...
Core
PRPG
Hybrid test set contains
pseudorandom and
deterministic vectors
...
.
.
.
BIST Controller
...
CORE UNDER
TEST
MISR
Pseudorandom test is improved
by a stored test set which is
specially generated to target the
random resistant faults
Optimization problem:
Where should be this breakpoint?
Pseudorandom Test
Determ. Test
Technical University Tallinn, ESTONIA
Optimization of Hybrid BIST
Cost of BIST: CTOTAL =  k +  t(k)
FAST estimation
Total Cost
CTOTAL
Number of remaining
faults after applying k
pseudorandom test
patterns rNOT(k)
# faults
k
SLOW
Cost of
pseudorandom test
patterns CGEN
Cost of stored
analysis test CMEM
# tests
 t(k)
PR test length k
min CTOTAL
Number of pseudorandom
test patterns applied, k
Figure 2: Cost calculation for hybrid BIST
Pseudorandom Test
PR test
length
# faults not
detected
(fast analysis)
# tests needed
(slow analysis)
k
rDET(k)
rNOT(k)
FC(k)
t(k)
1
2
3
4
5
10
20
50
100
200
411
954
1560
2153
3449
4519
4520
155
76
65
90
44
104
44
51
16
18
31
18
8
11
2
2
1
839
763
698
608
564
421
311
218
145
114
70
28
16
5
3
1
0
15.6%
23.2%
29.8%
38.8%
43.3%
57.6%
68.7%
78.1%
85.4%
88.5%
93.0%
97.2%
98.4%
99.5%
99.7%
99.9%
100.0%
104
104
100
101
99
95
87
74
52
Det. Test
Technical University Tallinn, ESTONIA
41
26
12
7
3
2
1
0
Deterministic Test Length Estimation
Deterministic test (DT)
Fault coverage
Pseudorandom test (PT)
F
100%
For each PT length i* we
determine
- PT fault coverage F*, and
- the imaginable part of DT
FDk(i) to be needed for the
same fault coverage
F P E k(i)
F D k(i)
F*
ji
i*
T D Ek(i)
T D Fk
Fast estimation for the
length of deterministic test:
i
Then the remaining part of DT
TDEk(i) will be the estimation of
the DT length
Pseudorandom
test length
Deterministic test length estimation
Technical University Tallinn, ESTONIA
Calculation of the Deterministic Test Cost
Two possibilities to find the length of deterministic data for each
possible breakpoint in the pseudorandom test sequence:
ATPG based:
Fault table based:
ATPG
ATPG
Detected
Faults
Fault table
update
All PR patterns?
All PR patterns?
No
No
ATPG based approach
For each breakpoint of Psequence, ATPG is used
Fault table based approach
A deterministic test set with fault
table is calculated
For each breakpoint of
P-sequence, the fault table is
updated for not yet detected
faults
FAST estimation
Next PR
pattern
Yes
End
Next PR
pattern
Only fault coverage is calculated
Technical University Tallinn, ESTONIA
Yes
End
Calculation of the Deterministic Test Cost
ATPG based approach
For each breakpoint of P-sequence, ATPG is used
ATPG based:
R1 R2
ATPG
Detected
Faults
Task for
fault
simulator
All PR patterns?
No
Next PR
pattern
Yes
End
Task for
ATPG
T1
T2
.
.
.
.
Tn
Tn+1
Tp
Faults
detected
by
pseudorandom
patterns
Rk
Rk+1 Rk+2
Rn
Faults to be
detected
by
deterministic
patterns
New detected
faults
Technical University Tallinn, ESTONIA
Calculation of the Deterministic Test Cost
Fault table based approach
A deterministic test set with fault table is calculated
For each breakpoint of P-sequence, the fault table is updated and remaining det.
patterns are determined
Fault table based:
R1 R2
ATPG
Fault table
update
All PR patterns?
No
Next PR
pattern
Yes
End
Task for
fault
simulator
Updated
fault
tabel
T1
T2
.
.
.
.
Tn
Tn+1
Tp
Rk
Faults
detected
By
pseudorandom
patterns
Rk+1 Rk+2
Rn
Fault table
for full
deterministic
test
To be detected
faults
Technical University Tallinn, ESTONIA
Experimental Data: HBIST Optimization
Finding optimal brakepoint in the pseudorandom sequence:
Pseudorandom Test
LOPT
Det. Test
Optimized hybrid test process:
Circuit
C432
C499
C880
C1355
C1908
C2670
C3540
C5315
C6288
C7552
SOPT
LMAX
LMAX
780
2036
5589
1522
5803
6581
8734
2318
210
18704
LOPT
91
78
121
121
105
444
297
711
20
583
Pseudorandom Test
SMAX
80
132
77
126
143
155
211
171
45
267
SOPT
21
60
48
52
123
77
110
12
20
61
Bk
4
6
8
6
5
30
7
23
4
51
SMAX
Det. Test
CTOTAL
175
438
505
433
720
2754
1067
987
100
3694
Technical University Tallinn, ESTONIA
Hybrid BIST with Reseeding
The motivation of using
random patterns is:
- low generation cost
- high initial efeciency
Problem: low fault coverage  long PR test
Pseudorandom
test:
2n-1
1
Fault Coverage
Hard
to test
faults
Solution: many seeds:
Pseudorandom
test:
2n-1
1
Time
Technical University Tallinn, ESTONIA
Store-and-Generate Test Architecture
ROM
Seeds
TPG
UUT
RD
ADR
# seeds
Counter 2
Pseudorandom test windows
Window
Counter 1
CL
Seeds
•
•
•
•
ROM contains test patterns for hard-to-test faults
Each pattern Pk in ROM serves as an initial state of the LFSR for test pattern
generation (TPG) - seeds
Counter 1 counts the number of pseudorandom patterns generated starting
from Pk - width of the windows
After finishing the cycle for Counter 2 is incremented for reading the next
pattern Pk+1 – beginning of the new window
Technical University Tallinn, ESTONIA
HBIST Optimization Problem
Using many seeds:
Pseudorandom test:
Seed 1
2n-1
1
L
Problems:
How to calculate the
number and size of
blocks?
Seed 2
Deterministic
test (seeds):
Which deterministic
patterns should be the
seeds for the blocks?
Pseudorandom
sequences:
Block
size:
100% FC
Seed 1
Seed 2
Memory
Constraints
Seed n
Seed n
Minimize L at given M and 100% FC
Technical University Tallinn, ESTONIA
Hybrid BIST Optimization Algorithm 1
D-patterns are ranked
Pseudorandom
sequence
ATPG patterns
Pattern selection
PRi
FC(PRi)
Detected faults subtraction,
optimization of ATPG patterns
Modified
ATPG pattern
table
Algorithm is based on
D-patterns ranking
Deterministic test patterns
with 100% quality are
generated by ATPG
The best pattern is selected
as a seed
A pseudorandom block is
produced and the fault table
of ATPG patterns is updated
The procedure ends when
100% fault coverage is
achieved
Technical University Tallinn, ESTONIA
Hybrid BIST Optimization Algorithm 2
P-blocks are ranked
Algorithm is based on
P-blocks ranking
PT*
PTmin
Deterministic test patterns
with 100% quality are
generated by ATPG
All P-blocks are generated
for all D-patterns and
ranked
…
…
Deterministic test vector (seed) DTi
Pseudorandom test sequence PRi
Pseudorandom sequence removed with the
block length optimization
The best P-block is selected
included into sequence and
updated
The procedure ends when
100% fault coverage is
achieved
Technical University Tallinn, ESTONIA
Cost Curves for Hybrid BIST with Reseeding
Two possibilities for reseeding:
Constant block length (less HW overhead)
Dynamic block length (more HW overhead)
C1908
Test length L
10000
9000
Memory cost M
140
L1(b)
120
8000
100
7000
6000
80
5000
L2(b)
60
4000
3000
40
2000
20
1000
M(b)
0
0
500
1000
1500
2000
2500
0
3000
Block size
b
Technical University Tallinn, ESTONIA
Functional Self-Test
• Traditional BIST solutions use special hardware for pattern
generation on chip, this may introduce area overhead and
performance degradation
• New methods have been proposed which exploit specific functional
units like arithmetic blocks or processor cores for on-chip test
generation
• It has been shown that adders can be used as test generators for
pseudorandom and deterministic patterns
• Today, there is no general method how to use arbitrary functional
units for built-in test generation
Technical University Tallinn, ESTONIA
Example: Functional BIST for Divider
Functional BIST quality analysis for
Samples from N=120 cycles
SB=105
Register
block
Control
DB=64
Functional
test
ALU
Data
compression:
Fault
coverage
N*SB / DB = 197
Signature analyser
K
Data
Fault
simulator
K*N
Test patterns (samples) are
produced on-line
during the working mode
K pairs of operands B1, B2
Technical University Tallinn, ESTONIA
Functional BIST Quality for Divider
Fault coverage of FBIST compared to Functional test
Data
4/2
7/2
6/3
8/2
9/4
9/3
12/6
14/2
15/3
2/4
Aver.
Gain
Functional testing
Total
B2
B1
13.21 15.09 14.15
21.23 16.98 19.10
31.6 25.47
19.34
25.47 10.38 17.92
7.31
5.66
8.96
32.55 26.89 29.72
8.02 18.87
13.44
18.16 25.00 11.32
29.48 31.13 27.83
8.02
7.55
7.8
18.96 17.83 17.97
1.0
1.0
1.0
Functional BIST
Total
B2
B1
35.14 40.57 29.72
38.44 47.64 29.25
41.04 39.62 42.45
32.07 40.57 25.00
36.56 47.64 25.47
43.63 46.07 40.57
36.08 39.62 32.55
37.50 49.06 25.94
47.88 50.00 45.75
29.01 20.75 33.02
37.74 42.15 32.97
1.8
2.4
2.0
Traditional
Functional
test
FBIST
UUT
UUT
Result
Result

HW
overhead
Signature

Go/NoGo
Reference
Reference
FBIST: collection and analysis of samples during the working mode
Fault coverage is better, however, still very low (ranging from 42% to 70%)
Technical University Tallinn, ESTONIA
Go/NoGo
Hybrid Functional BIST
• To improve the quality of FBIST we introduce the
method of Hybrid FBIST
• The idea of Hybrid FBIST consists in using for test
purposes the mixture of
– functional patterns produced by the microprogram (no
additional HW is needed), and
– additional stored deterministic test patterns to improve the total
fault coverage (HW overhead: MUX-es, Memory)
• Tradeoff should be found between
– the testing time and
– the HW/SW overhead cost
Technical University Tallinn, ESTONIA
Hybrid Functional BIST for Divider
Functional BIST implementation
MUX
M
Register
block
ALU
Automatic
Test Pattern
Generator
Deterministic
test set
Random
resistant
faults
Signature analyser
K
Test patterns are
stored in the
memory
Data
Technical University Tallinn, ESTONIA
Cost Functions for Hybrid Functional BIST
Cost
Total cost:
CTotal = CFB_Total +CD_Total
CTotal = CFB_Total +CD_Total
Opt.
The cost of functional test part:
cost
CFB_Total = CFB_Const + CFB_T + CFB_M
CFB_T + CFB_M
The cost of deterministic test part:
CD_Total = CD_Const + CD_T + CD_M
CD_T + CD_M
CD_Const
CFB_Const
CFB_Const, CD_Const - HW/SW overhead
CFB_T, CD_T
- testing time cost
, 
- weights of time and
memory expenses
Length of
FBIST
Opt. length
Problem: minimize CTotal
Technical University Tallinn, ESTONIA
Hybrid Functional BIST Quality
Functional test part
Determ. test
part
Total
Total
D
cost
cost
Total
cost
k
Nj
N
FC
%
0
0
0
100
0
58
6148
6148
1
108
108
66,8
140
24
2544
2684
2
105
213
76,7
277
18
1908
2185
3
113
326
83,3
518
17
1802
2320
4
108
434
85,5
690
16
1696
2386
5
110
544
88,4
864
15
1590
2454
k – number of
operands used
in the FBIST
The fault
coverage
increases if
k increases
Technical University Tallinn, ESTONIA
Functional Self-Test with DFT
Example: N-bit multiplier
Improving
controllability
T
N cycles
MUX
F
Register
block
ALU
EXOR
Improving
observability
Signature analyser
K
Data
Technical University Tallinn, ESTONIA
At-Speed FBIST of Pipe-Lined Architectures
Bioimpedance Signal processor
Fault coverage of real analog
signals as FBIST
FC%
100%
100
95
90
85
80
LFSR
Sine
Sawtooth
75
70
65
60
Chirp
55
Test length
Technical University Tallinn, ESTONIA
At-Speed FBIST of Pipe-Lined Architectures
Fault coverage of real analog
signals as FBIST
Signals used for measuring bioimpedance
FC%
Sine
100%
100
95
Chirp
90
85
Sawtooth
80
LFSR
Sine
Sawtooth
75
70
LFSR
65
60
Chirp
55
Test length
Technical University Tallinn, ESTONIA
At-Speed FBIST of Pipe-Lined Architectures
MISR is inserted to monitor the behaviour of
blocks in the pipe-lined architecture
Technical University Tallinn, ESTONIA
At-Speed FBIST of Pipe-Lined Architectures
Initial placement of MISR
Monitoring options
for on-line at-speed
testing
with the goal
to minimize the number
of MISR
at the tradeoff
between
the number of MISR,
fault coverage and
test length
Final placement of MISR
Technical University Tallinn, ESTONIA
At-Speed FBIST of Pipe-Lined Architectures
Example of
merging and splitting
the blocks in UUT
with high and low
fault detection coverage
Two procedures: merging and
splitting of blocks under test
The final partitioning of
the architecture
depends on the tradeoff
between
the number of MISR,
fault coverage and
test length
Technical University Tallinn, ESTONIA
Exploration
General
procedure
for
minimization
of the number of
observation
points
The problem is:
fault simulation
Technical University Tallinn, ESTONIA
Evaluation of the Quality of FBIST
Fault simulation in
sequential circuits
Full task of fault
simulation
Test
sequence
Transforming sequential fault
simulation into sub-tasks of
combinational fault simulation
Test
sequence
T
Sequential
UUT
Sequential
UUT
Logic simulator
Sub-test
sequences
T1
Fault simulator for
sequential circuits
Tn
Fault simulator for
combinational circuits
Combinational
sub-circuits
B1
Sub-tasks of
fault simulation
Technical University Tallinn, ESTONIA
Bn
Hybrid BIST for Multiple Cores
Embedded tester for testing multiple cores
Embedded Tester
C2670
Test
Controller
BIST
C3540
Test access
mechanism
BIST
Tester
Memory
BIST
C1908
BIST
C880
BIST
C1355
SoC
Technical University Tallinn, ESTONIA
Hybrid BIST for Multiple Cores
Deterministic test (DT)
How to pack
knapsack?
How to
compress the
test sequence?
Pseudorandom test (PT)
Technical University Tallinn, ESTONIA
Multi-Core Hybrid BIST Optimization
Cost of BIST: CTOTAL =  k +  t(k)
FAST estimation
Total Cost
CTOTAL
Number of remaining
faults after applying k
pseudorandom test
patterns rNOT(k)
# faults
k
Cost of
pseudorandom test
patterns CGEN
Cost of stored
test CMEM
SLOW analysis
# tests
 t(k)
PR test length k
min CTOTAL
Number of pseudorandom
test patterns applied, k
Figure 2: Cost calculation for hybrid BIST
Pseudorandom Test
Det. Test
Two problems:
1) Calculation of DT cost is
difficult
2) We have to optimize n (!)
processes
How to avoid the calculation of
the very expensive full DT cost
curve?
Technical University Tallinn, ESTONIA
Deterministic Test Length Estimation
Deterministic test (DT)
Fault coverage
Pseudorandom test (PT)
F
100%
For each PT length i* we
determine
- PT fault coverage F*, and
- the imaginable part of DT
FDk(i) to be used for the
same fault coverage
F P E k(i)
F D k(i)
F*
ji
i*
T D Ek(i)
T D Fk
Solution of the first
problem:
i
Then the remaining part of DT
TDEk(i) will be the estimation of
the DT length
Pseudorandom
test length
Deterministic test length estimation for a single core
Technical University Tallinn, ESTONIA
Deterministic Test Cost Estimation
Total cost calculation of core costs:
8000
DT cost
Memory usage: 5357 bits
Core name:
c499
c880
c1355
c1908
c5315
c6288
c432
Mem ory Constraint
Constraint
6000
5500
Memory (bits)
4000
Memory usage:
1353
480
1025
363
2136
0
0
Deterministic
time:
33
8
25
11
12
0
0
Estimated Cost
Real cost
Real Cost
Cost Estimates
Core
costs
for Individual Cores
2000
Estimated cost
0
500
542
1000
Total Test Lenght (clocks) 1500
Total
test
length
Solution
Technical University Tallinn, ESTONIA
Total Test Cost Estimation
COST
Using total cost solution
we find the PT length:
E
COST T,k
DT cost
Using PT length, we calculate
the test processes for all cores:
Total cost
Total cost
E*
COST
solution
T
c432
Deterministic
Pseudorandom
Solution
c6288
c880
Pseudorandom test
(PT) length
COSTP,k
PT costE
COST D,k
jmin
205
4
j*k
j
4
2
6
13
c1908
203
19
c5315
21
169
40
c1355
Total Test
190
46
123
86
c499
50
73
136
0
50
48
100
PT length solution
Technical University Tallinn, ESTONIA
150
25
200
Multi-Core Hybrid BIST Optimization
Iterative optimization process:
1 - First estimation
1* - Real cost calculation
2 - Correction of the estimation
2* - Real cost calculation
3 - Correction of the estimation
3* - Final real cost
G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of
Core-Based Systems. Asian Test Symposium 2003, Xi’an, China, November 17-19, 2003,
Technical University Tallinn, ESTONIA
Optimized Multi-Core Hybrid BIST
Pseudorandom test is carried out in parallel,
deterministic test - sequentially
Technical University Tallinn, ESTONIA
Test-per-Scan Hybrid BIST
Every core’s BIST logic is capable to produce a set of independent pseudorandom test
The pseudorandom test sets for all the cores can be carried out simultaneously
s298
Scan Path
Scan Path
Scan Path
Scan Path
Test
C ontroller
LFSR
Scan Path
Scan Path
Scan Path
LFSR
Scan Path
LFSR
Em bedded Tester
LFSR
s3271
Only one test
access bus at
the system level
Tester
Mem ory
s1423
LFSR
LFSR
Scan Path
Scan Path
Scan Path
LFSR
Scan Path
LFSR
Scan Path
is needed.
Scan Path
Scan Path
SoC
TAM
Deterministic
tests can only
be carried out
for one core at a
time
Scan Path
s838
Technical University Tallinn, ESTONIA
Bus-Based BIST Architecture
• Self-test control broadcasts patterns to each CUT over bus –
parallel pattern generation
• Awaits bus transactions showing CUT’s responses to the
patterns: serialized compaction
Source: VLSI Test: Bushnell-Agrawal
Technical University Tallinn, ESTONIA
Broadcasting Test Patterns in BIST
Concept of test pattern sharing via novel scan structure – to
reduce the test application time:
...
CUT 1
...
CUT 2
Traditional single scan design
...
CUT 1
...
CUT 2
Broadcast test architecture
While one module is tested by its test patterns, the same test
patterns can be applied simultaneously to other modules in the
manner of pseudorandom testing
Technical University Tallinn, ESTONIA
Broadcasting Test Patterns in BIST
Examples of connection possibilities in Broadcasting BIST:
CUT 1
CUT 2
j-to-j connections
CUT 1
CUT 2
Random connections
Technical University Tallinn, ESTONIA
Broadcasting Test Patterns in BIST
Scan configurations in Broadcasting BIST:
Scan-In
Scan-In
...
...
CUT 1
...
...
...
CUT n
CUT 1
CUT n
...
...
...
MISR 1
MISR n
...
MISR
Scan-Out
Common MISR
Scan-Out
Individual and multiple MISRs
Technical University Tallinn, ESTONIA
Embedded Built-in Self-Diagnosis (BISD)
• Introduction to Fault Diagnosis
– Combinational diagnosis (effect-cause approach)
– Sequential (adaptive) diagnosis (cause-effect approach)
• General conception of embedded BISD
• Diagnostic resolution
– Intersection based on test subsequences
– Intersection based on using signature analyzers
• Fault model free diagnosis
• Fault evidence based diagnosis
Technical University Tallinn, ESTONIA
Research in ATI
© Raimund Ubar
Why Fault Masking is Important Issue?
Diagnosis
method
Test
result
Fault table
Tested faults
Devil’s
advocate
approach
Passed
Tested faults
Failed
Tested faults
Fault
candidates
Single fault
assumption
Multiple
faults
allowed
Angel’s
advocate
?
Failed
Diagnosis
Fault candidates
Proved OK
Fault
candidates
139/24
Fault Diagnosis
Test experiment
Fault table
Fault
modeling
How many
rows
and
columns
should be
in the
Fault Table?
T1
T2
T3
T4
T5
T6
F1
0
1
1
0
0
0
F2
1
0
1
1
0
0
F3
1
0
0
0
1
1
F4
0
1
1
0
0
0
F5
0
0
0
1
1
0
F6
0
0
1
0
1
1
F7
0
0
0
0
0
1
E1
0
0
0
1
1
0
E2
0
1
1
0
0
0
E3
1
0
0
1
1
0
Fault F5 located
Testing
Fault diagnosis
Fault simulation
Test generation
Technical University Tallinn, ESTONIA
Combinational Fault diagnosis
Fault localization by fault tables (cause-effect concept)
T1
T2
T3
T4
T5
T6
F1
0
1
1
0
0
0
F2
1
0
1
1
0
0
F3
1
0
0
0
1
1
F4
0
1
1
0
0
0
F5
0
0
0
1
1
0
F6
0
0
1
0
1
1
E1
0
0
0
1
1
0
F7
0
0
0
0
0
1
E2
0
1
1
0
0
0
E3
1
0
0
1
1
0
Fault F5 located
Faults F1 and F4 are not distinguishable
No match, diagnosis not possible
Technical University Tallinn, ESTONIA
Combinational Fault Diagnosis
Fault localization by fault dictionaries (cause-effect concept)
•
Fault dictionaries contain the sama data as the fault tables with the difference
that the data is reorganised
•
The column bit vectors can be represented by ordered decimal codes or by some
kind of compressed signature
No Bit vectors
1
000001
2
000110
3
001011
4
011000
5
100011
6
101100
Decimal numbers
01
06
11
24
35
44
Faults
F7
F5
F6
F1, F4
F3
F2
Test results:
E1 = 06, E1 = 24, E1 = 38
No match
Technical University Tallinn, ESTONIA
Sequential Fault Diagnosis
Sequential fault diagnosis by Edge-Pin Testing (cause-effect)
T1
T2
T3
T4
T5
T6
F1,F2
F3,F4
F5,F6
F7
F1
0
1
1
0
0
0
F2
1
0
1
1
0
0
T1
F3
1
0
0
0
1
1
F4
0
1
1
0
0
0
F5
0
0
0
1
1
0
P
F1,F4,F5,F6,F7
F
F2, F3
F6
0
0
1
0
1
1
F7
0
0
0
0
0
1
T2
P
Diagnostic tree
Two faults F1,F4 remain indistinguishable
Not all test patterns used in the fault table
are needed
Different faults need for identifying test
sequences with different lengths
The shortest test contains two patterns,
the longest four patterns
F1,F4
F
P
T3
F3
F5,F6,F7
F
F2
P
T3
F5,F7
F
F6
P
T4
F7
F
F5
Technical University Tallinn, ESTONIA
Embedded BIST Based Fault Diagnosis
Pseudorandom test
sequence:
BISD scheme:
Test Pattern Generator
(TPG)
BISD
Control Unit
......
Circuit Under Diagnosis
(CUD)
Test patterns
Pattern Signature Faults
......
Output Response
Analyser
(ORA)
May 11-14, 2008
............
............
............
............
............
............
............
............
.............
.............
.............
.............
.............
.........
.............
.............
.............
.......
.......
.......
.......
.......
.......
.... .......
.......
.......
Diagnostic Points (DPs) –
patterns that detect new faults
Further minimization of DPs –
as a tradeoff with diagnostic
resolution
Technical University Tallinn, ESTONIA
26th International Conference on Microelectronics, Niš, Serbia
4/20
Built-In Fault Diagnosis
Diagnosis procedure:
Test Pattern Generator
(TPG)
1. test
BIST
Control Unit
......
Circuit Under Test
(CUT)
3. test
2. test
Faulty
signature
Test patterns
3. test
Number Signature Faults
......
Output Response
Analyser (ORA)
............
............
............
............
............
............
............
............
.............
.............
.............
.............
.............
.............
.............
.............
.......
.......
.......
.......
.......
.......
.......
.......
Correct
signature
Faulty signature
Pseudorandom test sequence
Technical University Tallinn, ESTONIA
Built-In Fault Diagnosis
Measuring of information we
get from the test:
Binary search with
bisectioning of test patterns
I = - p log2 p – (1-p) log2 (1-p)
ERROR
Pseudorandom test fault
simulation (detected faults)
№ All faults
1
5
2
15
3
16
4
17
5
20
6
21
7
25
8
26
9
29
10
30
New faults
5
10
1
1
3
1
4
1
3
1
Coverage
16.67%
50.00%
53.33%
56.67%
66.67%
70.00%
83.33%
86.67%
96.67%
100.00%
5
OK
2
8
1
5
6
3
10
1
4
1
1
3
9
7
4
10
3
1
Average number of test sessions: 3,3
Average number of clocks: 8,67
Technical University Tallinn, ESTONIA
1
Built-In Fault Diagnosis
Binary search with
bisectioning of faults
Pseudorandom test fault
simulation (detected faults)
№ All faults
1
5
2
15
3
16
4
17
5
20
6
21
7
25
8
26
9
29
10
30
New faults
5
10
1
1
3
1
4
1
3
1
Coverage
16.67%
50.00%
53.33%
56.67%
66.67%
70.00%
83.33%
86.67%
96.67%
100.00%
ERROR
OK
2
1
5
6
5
10
4
3
1
8
1
3
7
4
9
1
10
3
1
1
Average number of test sessions: 3,06
Average number of clocks: 6,43
Technical University Tallinn, ESTONIA
Built-In Fault Diagnosis
Diagnosis with multiple signatures
(based on reasoning of spacial information):
SA1
Test pattern generator
SA2
D3
Fault
D2
D1
CUD
D7
D5
D6
SA3
D4
SA1
SA2
SA3
Technical University Tallinn, ESTONIA
Built-In Fault Diagnosis
Diagnosis with multiple signatures:
No
Codeword
Diagnosis
Diagnostic tree
h
i
0
0
1
R1
0
0
1
R1’’’
R1’’’
R1’, R2’, R3’
h
F/001
j
0
1
1
R2
R1
F/001
P
i
v
k
l
0
1
1
1
1
1
R1’’, R2’’
F/011
P
F/111
j
k
R2
F/011
R3
P
l
R3
F/111
R1’’, R2’’
v
1
1
1
R1’, R2’, R3’
Technical University Tallinn, ESTONIA
Built-In Fault Diagnosis
BIST with multiple
signature analyzers
Faulty
signature
Intersection
using tests
Test pattern generator
Correct
signature
Fault
Faulty signature
CUD
SA1
SA2
D3
D2
D1
SA1
SA2
SA3
Intersection
using SA-s
Optimization of the interface between
CUD and SA-s
D7
D5
SA3
D6
D4
Technical University Tallinn, ESTONIA
1 SA Resolution
5 SA Resolution
10 SA Resolution
1 SA Test length
5 SA Test length
10 SA Test length
240.0
230.0
220.0
210.0
200.0
190.0
180.0
170.0
160.0
150.0
140.0
130.0
120.0
110.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
Diagnosis with multiple
signatures:
65.0
60.0
55.0
Gain in
speed of
diagnosis
50.0
45.0
40.0
35.0
Optimal
number of
failed
patterns
30.0
25.0
Average test length
Average resolution
Built-In Fault Diagnosis
Measured:
- average resolution
- average test length
Compared: 1SA, 5SA, 10SA
Gain in test length: 6 times
20.0
15.0
10.0
1
2
3
4
5
6
7
Failed patterns
8
9
10
5.0
ALL
R.Ubar, S.Kostin, J.Raik. Embedded Fault
Diagnosis in Digital Systems with BIST.
J. of Microprocessors and Microsystems,
Volume 32, August 2008, pp. 279-287.
Technical University Tallinn, ESTONIA
Extended Fault Models
Extensions of the parallel critical path tracing for two large
general fault classes for modeling physical defects:
Multiple
fault
0
1
0
1
Resistive bridge fault
Defect
SAF
Conditional fault
Pattern fault
Constrained SAF
Single faulty signal
X-fault
Byzantine fault
Bridges
Stuck-opens
Multiple faulty signal
Technical University Tallinn, ESTONIA
Fault-Model Free Fault Diagnosis
Combined cause-effect and
effect-cause diagnosis
Effect
Faulty
area
Effect
Cause
Cause
Faulty
block
2) Effect-Cause
Fault Diagnosis
Faulty
area
Faulty system
1) Cause-Effect
Fault Diagnosis
Suspected faulty area is
located based on the
fault table (dictionary)
Faulty block is located in the
suspected faulty area
Fault
3) Fault Reasoning
Failing test patterns are mapped
into the suspected defect or into a
set of suspected defects in the
faulty block
Test
Failing
test
patterns
Diagnosis of Fault Model Free Defects
Real test
experiment
Simulation
Circuit Under
Diagnosis
Faulty machine
FM(f)
t
Fault evidence:
for test pattern t
e(f,t) = (t , t, lt, t)
t = min (t, lt)
t
f
lt
Fault
for full test T (sum)
e(f,T) = ( , , l, )
Test pattern t
Correct outputs
Erroneus outputs
Copyright: H.J.Wunderlich 2007
Technical University Tallinn, ESTONIA
Diagnosis of Fault Model Free Defects
Real test
experiment
Simulation
Circuit Under
Diagnosis
Faulty machine
FM(f)
t
t
lt
Test pattern t
f
Fault
Different classical fault cases
lt
t
t
Single SAF
0
0
0
Multiple SAF
0
>0
0
Single conditional SAF
>0
0
0
Multiple cond. SAF
>0
>0
0
Delay fault
>0
0
>0
General case
>0
>0
>0
Classic model
Copyright: H.J.Wunderlich 2007
Technical University Tallinn, ESTONIA
Diagnosis of Fault Model Free Defects
Real test
experiment
Simulation
Circuit Under
Diagnosis
Faulty machine
FM(f)
d
t
Defect
f
Fault
Test pattern t
Different classical fault cases
lt
t
t
Single SAF
0
0
0
Multiple SAF
0
>0
0
Single conditional SAF
>0
0
0
Multiple cond. SAF
>0
>0
0
Delay fault
>0
0
>0
General case
>0
>0
>0
Classic model
Copyright: H.J.Wunderlich 2007
Technical University Tallinn, ESTONIA
Diagnosis of Fault Model Free Defects
Real test
experiment
Simulation
Circuit Under
Diagnosis
Faulty machine
FM(f)
d1
d2
t
t
f
Fault
Multiple
defects
Test pattern t
Different classical fault cases
lt
t
t
Single SAF
0
0
0
Multiple SAF (defects)
0
>0
0
Single conditional SAF
>0
0
0
Multiple cond. SAF
>0
>0
0
Delay fault
>0
0
>0
General case
>0
>0
>0
Classic model
Copyright: H.J.Wunderlich 2007
Technical University Tallinn, ESTONIA
Diagnosis of Fault Model Free Defects
Different classical fault cases
Real test
experiment
Simulation
Circuit Under
Diagnosis
Faulty machine
FM(f)
d
Defect
t
lt
f
Fault
Condition
lt
t
t
Single SAF
0
0
0
Multiple SAF
0
>0
0
Single conditional SAF >0
0
0
Multiple cond. SAF
>0
>0
0
Delay fault
>0
0
>0
General case
>0
>0
>0
Classic model
Test pattern t
Defect
Copyright: H.J.Wunderlich 2007
Condition
Technical University Tallinn, ESTONIA
Fault Diagnosis Without Fault Models
RT Level
Logic level
Transistor level
&
Reverse
defect
mapping
x1
M1
+
M3
&
&
&
1
IN
M2
R2
*
&
x4
x2
x3
R1
&
System level
Defect
dy
x5
Wd
Defective
area
Error
detection
Logic level
Error (defective area) diagnosis
Technical University Tallinn, ESTONIA
Diagnosis of Fault Model Free Defects
Real test
experiment
Simulation
Circuit Under
Diagnosis
Faulty machine
FM(f)
t
t
lt
Test pattern t
Ranking
(on the top the most
suspicious faults):
SAF
T
T
lT
f1
0
42
0
f2
30
42
15
f3
30
42
25
f4
30
42
30
equal then by
f5
30
36
38
increasing lT
f6
38
23
22
f7
38
23
23
(1) By increasing T
(single SAF on top)
f
Fault
Example:
(2) If T are equal then
by decreasing T
(3) If T and T are
t = min (t, lt)
Copyright: H.J.Wunderlich 2007
Technical University Tallinn, ESTONIA
Fault Tolerance: Error Detecting Codes
System
Checker
Not eligible code
Parity bit
Examples:
Decimal digits:
Eligible: 0,1,2,..., 9
Not eligible: 10,11,..., 15
Parity check:
00 0
01 1
10 1
11 0
0
3
5
6
1
2
4
7
Eligible
Not eligible
Technical University Tallinn, ESTONIA
Error Detecting/Correcting Codes
Hamming distance between codes:
Eligible
codes
Minimal number of bits
how two codes differ
from each other
d
Parity bit
110
100
101 111 011
001
Eligible
000
codes
010
Parity check:
d=2
00
01
10
11
0
1
1
0
0
3
5
6
1
2
4
7
Eligible
Not eligible
Not eligible codes
Technical University Tallinn, ESTONIA
Error Detecting/Correcting Codes
Error detecting codes:
Eligible
codes
d=2
Error
detection:
direction
unknown
Error correcting codes:
d=3
Error correction is
possible: direction
is known
Eligible
codes
Eligible
codes
Detection
not possible
Not eligible codes
Correction
not possible
Technical University Tallinn, ESTONIA
Fault Tolerance: Error Correcting Codes
d = 2e + 1
-
2e - error detection
e - error correction
One error correction code: 2c  q + c + 1
Check bits
Error free
q
Information bits
c
For addressing of the
erroneous bit
Technical University Tallinn, ESTONIA
Fault Tolerance: One Error Correcting Code
Analogy with fault diagnosis
by using fault table:
Location of erroneous bit:
7
6
5
4
3
2
1
1
0
1
0
1
0
1
7
6
5
4
3
2
1
1
0
1
1
1
0
1
Initial code
Received code
Check bits
b2i, i = 1,...,c
P1 = b1  b3  b5  b7 = 0
P2 = b2  b3  b6  b7 = 0
P3 = b4  b5  b6  b7 = 0
Test
7
6
5
4
3
2
1
0
1
1
1
P1 1
P2 1 1
1 1
P3 1 1 1 1
Check bits have to be independently assigned
Diagnosis
Technical University Tallinn, ESTONIA
0
0
1
Fault Tolerant Communication System
Initial code
Check-bits
generator
Error
indication
Sender
Error
correction
code
Receiver
Checker
Error
correction
(restoring)
Received
correct code
Technical University Tallinn, ESTONIA
Error Detection in Arithmetic Operations
Check bits
Residue codes
Information bits
N – information code
C = (N) mod m - check code
m – residue of the code
p = log2 m  – number of check bits
Example
Information bits: I2, I1, I0
m = 3, p = 2
Check bits: c1, c0
I2
0
0
0
0
1
1
1
1
I1
0
0
1
1
0
0
1
1
I0
0
1
0
1
0
1
0
1
I
0
1
2
3
4
5
6
7
c
0
1
2
0
1
2
0
1
c1
0
0
1
0
0
1
0
0
c0
0
1
0
0
1
0
0
1
Technical University Tallinn, ESTONIA
Error Detection in Arithmetic Operations
Addition:
Multiplication:
Information bits Check bits
0 0 1 0
1 0
2.2
0 1 0 0
0 1
4.1
0 1 1 0
(6)mod3 = 0
1 1
6.3
(3)mod3 = 0
(4)mod3 = 1
Error!
1 1
(3)mod3 = 0
1 0 0 0
(8)mod3 = 2
Information bits Check bits
0 0 1 0
1 0
2.2
0 1 0 0
0 1
4.1
0 1 0 0
Information bits Check bits
0 0 1 0
1 0
2.2
0 1 0 0
0 1
4.1
4.3
1 0
8.2
(2)mod3 = 2
Information bits Check bits
0 0 1 0
1 0
2.2
0 1 0 0
0 1
4.1
1 0 0 1
(9)mod3 = 0
Error!
1 0
(2)mod3 = 2
Technical University Tallinn, ESTONIA
9.2
Error Detection in Arithmetic Operations
A
B
Check
bit
generator
Adder
Adder mod m
A+B
Residue
calculator
C(A) C(B)
C(C(A) + C(B))
C(A + B)
Comparator
Error
indicator
Technical University Tallinn, ESTONIA
Fault Tolerance: One Error Correcting Code
One error correction code: 2c  q + c + 1
Calculation of check sums:
bc+q
7
6
b2 b1
5
4
3
2
1
Check bits
 bk  0, i  1,..., c
kPi
Parity bits for c = 3:
P1 = b1  b3  b5  b7 = 0
P2 = b2  b3  b6  b7 = 0
P3 = b4  b5  b6  b7 = 0
Technical University Tallinn, ESTONIA