Electronics update
E. Noah, A. Blondel, Y. Favre, R.
Tsenov
29 July 2015
Baby MIND electronics chain
2
Baby MIND FEB sketch
3
Baby MIND FEB
 FEB characteristics :
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•
•
•
•
•
•
96 SiPM channels (mini coax. connectors), 84 used for Baby MIND
3 CITIROC ASICs (32 ch charge ampl., trigs, ext. common HV + independent 0/4V)
12-bits 8-ch ADC 40Ms/s/ch
2 x 6Gb/s transceiver (800Mb/s for Baby MIND)
USB3.0 (5Gb/s) µC for lab, calib. & maintenance
LV & HV power supplies
Altera ARIA 5 FPGA (mid-range), firmware :
•
•
•
•
•
84 ch. Timing meas (2/2.5ns resolution)
Charge meas. (from 12-bits ADC)
Baseline computation (filtering)
USB3.0 gateway
Gigabit protocol for readout (exp.)
•
PCB:
•
• 8 layers
• 120µm space/width lines
• Impedance & length control (TDC)
Schedule:
• First prototype FEB 11 March 2015
• Firmware development ongoing
• ~ 30 Baby MIND FEBs Dec. 2015
Baby MIND FEB (Photo by Y. Favre 12 March 2015)
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Baby MIND FEB firmware status
• Detailed and well documented architecture
• Large fraction of firmware is written
– USB3 connectivity tested to 2.5 Gbit/s
– CITIROC ASIC configuration untested
• Firmware versions:
– First version of firmware allows for charge
readout – end Aug. 2015
– Second version of firmward allows for charge and
timestamp – end Sept. 2015
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Tests with CITIROC Evaluation Board
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Photosensors
 Options tested:
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•
MPPC/ASD40/KETEK/SensL
Several MPPC variants
 Selection:
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Hamamatsu MPPC S12571-025C
1 × 1 mm2
25 mm cell size
3000 delivered by 6 Mar. 2015
MPPC test data by Hamamatsu
vop
darkcnt
htemp
Entries
3000
Mean
67.51
RMS
0.1426
200
180
160
Vop [V]
25oC
140
120
180
160
120
100
80
80
60
60
40
40
20
20
67.2
67.4
67.6
67.8
68
68.2
68.4
Dark cnts [kHz]
thres.: 0.5 p.e.
140
100
0
htemp
Entries
3000
Mean
83.34
RMS
12.36
200
68.6
vop
0
60
80
100
120
140
160
WLS fiber and MPPC alignment
180
darkcnt
103
DCR_map_9
120
100
80
60
40
102
20
0
0
10
20
30
40
50
60
70
80
90 100
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Bar light yield test: post module assembly
Channel configuration: channels under test ch0-15
ch15
ch7
ch23
ch0
ch8
ch16
ch27
ch24
ch31
ch28
Setup in dark room
25oC
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Module characterisation with CITIROC evaluation board
ADC
[12-bit]
FPGA
MPPC
x32
Delay
Plastic
Scint.
bars
x32
usb
LabVIEW
9
CITIROC shaper time constant
25 ns
37.5 ns
50 ns
62.5 ns
75 ns
87.5 ns
30 ns
40 ns
50 ns
60 ns
OR32/Hold delay
20 ns
10 ns
12.5 ns
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Varying Pre-amp Feedback capacitance
• Regime:
Feedback capa.
= 1 [arb.]
48.2 ADC/p.e.
– high enough gain to
resolve indivual p.e.
peaks
whilst avoiding saturation
• Dynamic range (HG):
–
–
–
–
12-bit ADC
Baseline ~950
19.3 ADC/p.e.
160 p.e.
• > 1600 p.e. with LG.
Feedback capa.
= 4 [arb.]
32.2 ADC/p.e.
Feedback capa.
= 6 [arb.]
25.6 ADC/p.e.
Feedback capa.
= 8 [arb.]
19.3 ADC/p.e.
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Light yield: sum of both ends of bar
Bar pos. Bar ID Bar INR
[#]
[#]
[p.e.]
Module
[p.e.]
1
6421
124.4
145.2
2
6411
125.4
155.4
3
6422
119.0
138.7
4
6410
134.6
153.6
5
6414
112.9
142.5
6
6409
118.6
136.6
7
6412
129.4
146.2
8
6413
119.0
183
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“Optical” crosstalk: light yield in adjacent bars
b
a
d
c
ch15
ch7
ch23
ch0
ch8
ch16
ch27
ch24
ch31
ch28
L.y. cuts:
Ch3>70p.e.
Ch11>70p.e.
Ch19>70p.e.
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“Optical” crosstalk: l.y. sum of both ends collected in adjacent bars
(ch2-946.070)/19.29+(ch10-947.900)/18.05 {(((ch19-950)/18.12>70)&&((ch3-951.540)/18.46>70))&&((ch11-946.130)/17.25>70)}
htemp
888
Entries
11.39
Mean
41.83
RMS
350
300
(ch1-949.020)/17.71+(ch9-948.280)/20.14 {(((ch19-950)/18.12>70)&&((ch3-951.540)/18.46>70))&&((ch11-946.130)/17.25>70)}
600
a
250
400
150
300
100
200
50
100
0
50
100
150
c
500
200
0
htemp
888
Entries
0.4442
Mean
25.73
RMS
700
200
250
300
350
(ch2-946.070)/19.29+(ch10-947.900)/18.05
0
-50
350
b
300
100
150
200
250
300
350
(ch1-949.020)/17.71+(ch9-948.280)/20.14
htemp
888
Entries
-0.7479
Mean
22.51
RMS
700
600
d
500
250
400
200
300
150
200
100
100
50
0
50
(ch5-939.850)/19.04+(ch13-947.020)/19.51 {(((ch19-950)/18.12>70)&&((ch3-951.540)/18.46>70))&&((ch11-946.130)/17.25>70)}
(ch4-945.350)/19.15+(ch12-951.450)/18.94 {(((ch19-950)/18.12>70)&&((ch3-951.540)/18.46>70))&&((ch11-946.130)/17.25>70)}
htemp
888
Entries
10.66
Mean
35.75
RMS
0
0
50
100
150
200
250
300
350
(ch4-945.350)/19.15+(ch12-951.450)/18.94
0
-50
0
50
100
150
200
250
300
350
(ch5-939.850)/19.04+(ch13-947.020)/19.51
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Summary
• Electronics-related work proceeding with two
cards:
– The Baby MIND FEB: firmware writing,
first version end of August will do charge only
– The CITIROC evaluation board:
exploration of range of configuration parameters
for the CITIROC
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