Budapest University of Technology and Economics
Department of Electron Devices
Overview, main features, design & manufacturing, costs, etc.
http://www.eet.bme.hu/~poppe/miel/en/ 16-ICdesign1.pptx
http://www.eet.bme.hu

Budapest University of Technology and Economics
Department of Electron Devices
► Moore's law and its manifestations
► Roadmap data
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► We've seen what building blocks are being used in today's digital ICs:
 CMOS logic gates
• main features, construction
– logic model → circuit schematic
► We've seen the basic principles of IC manufacturing
 planar process, photo lithography
► We've seen that the in-depths structure is determined by 2D shapes on the applied photomasks: layout
► We've seen that there was a direct path from the logic level circuit schematics to the layout
► Now we discuss some non technical aspects of
IC manufacturing
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20-11-2014 3

Budapest University of Technology and Economics
Department of Electron Devices
Moore's law
► In 1965 Gordon Moore predicted that in every 14..18 months the number of transistors integrated in a chip will double
(exponential growth)
► This prediction is valid even today.
► The 1 million transistors/chip threshold was reached in the
1980-ies
 2300 transistors, 1 MHz clock frequency (Intel 4040) - 1971
 16 millió transistors (Ultra Sparc III)
 42 millió transistors, 2 GHz clock frequency (Intel P4) - 2001
 140 millió transistors, (HP PA-8500)
► More than Moore : further increase of integration density, e.g.
3D stacking of chips (RAM-s, pen drives)
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20-11-2014 4

Budapest University of Technology and Economics
Department of Electron Devices
► Leading industrial experts provide continousely updated forecasts about the development trends microelectronics
(manufacturing processes and technologies)
Year 1999 2002 2005 2008 2011 2014
Feature size (nm)
Mtrans/cm 2
Chip size (mm 2 )
Signal pins/chip
Clock rate (MHz)
Wiring levels
Power supply (V)
High-perf power (W)
Battery power (W)
180
7
130
14-26
100
47
70 50 35
115 284 701
170 170-214 235 269 308 354
768 1024 1024 1280 1408 1472
600
6-7
1.8
90
1.4
800
7-8
1.5
130
2.0
1100
8-9
1.2
1400
9
0.9
1800
9-10
0.6
2200
10
0.6
160 170 174 183
2.4
2.0
2.2
2.4
NTRS = National Technolgy Roadmap for Semiconductors
SIA = Semiconductor Industry Association http://www.itrs.net/ntrs/publntrs.nsf
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Physical limits approached
Decrease of supply voltage , threshold voltage and oxide thickness with the decrease of the channel length
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Increase of design productivity is behind increase of circuit complexity:
10,000 100,000
1,000
Logic Tr./Chip
Tr./Staff Month.
10,000
100 1,000
10
58%/Yr. compounded
Complexity growth rate
100
1 10 x
0.1
x
1 x x x x x x
21%/Yr. compound
Productivity growth rate
0.01
0.1
0.01
0.001
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Increasing complexity / increasing costs
► Gap between complexity and design capacity
► Design and manufacturing separated
► Cost reduction
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Microscopic Problems
 Ultra-high speed design
 Interconnect
 Noise, Crosstalk
 Reliability,
Manufacturability
 Power Dissipation
 Clock distribution
► Macroscopic Issues
 time-to-market
 design complexity (millions of logic gates)
 high abstraction level, testing
 reusability, IP, portability
 systems on a chip (SoC)
 tool interoperability
YEAR
1997
1998
1999
2002
20-11-2014
Tech.
(MFS, μm)
0.35
0.25
0.18
Complexity
13 M Tr.
20 M Tr.
32 M Tr.
Clock frequency
400 MHz
500 MHz
600 MHz
0.13
130 M Tr.
800 MHz
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
Design effort in person years
210
270
360
800
Design cost
$90 M
$120 M
$160 M
$360 M
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Budapest University of Technology and Economics
Department of Electron Devices
► Functionality
► Costs
 One-time, fix costs or non-recurring engineering costs ( NRE ) – e.g. labor cost of design
 proportional costs ( RE ) – materials, packaging, testing
► Reliability, robustness
 noise margins
 noise immunity
► Performance
 speed (delays)
 dissipation (energy consumption)
► Time-to-market
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► One-time, fix costs or non-recurring engineering costs (NRE)
 Costs of the design
• personal effort / labor cost of design work, CAD framework license fee
• labor costs of design verification
• mask manufacturing cost
 Determined by the design complexity and design productivity
 More significant in case of smaller production volumes
► Recurring engineering costs
 costs of silicon processing
• proportional to the chip area
 assembly costs (bonding, packaging)
 testing
Plus amortization costs of the foundry cost per IC = proprtional costs per IC + fix cost volume
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Increasing NREs
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
cost:
¢-per-transistor
1
0.1
0.01
0.001
Fabrication capital cost per transistor (Moore’s law)
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
IC chip or die
(AMD Athlon processors)
Si szelet ( wafer )
►
Going up to 12” (30cm)
Influenced by
 wafer size, die size
 yield: # of functional / # of manufactured ICs
 testing
• in-line, before packaging
• final testing (after packaging)
 assembly costs
Dies per wafer

 
 wafer diameter/2

2 die area

  wafer diameter
2
 die area
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20-11-2014 15

Budapest University of Technology and Economics
Department of Electron Devices
die yield

1
 defects per unit
 area
 die area
 
 is approximately 3
Yield

No.
of good chips per wafer
Total number of chips per wafer

100 % cost of a good die = costs of a wafer volume × yield die cost + die testing cost + assembly cost volume related cost =
20-11-2014 yield of final testing
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Example
 wafer diameter 12", die size 2.5 cm 2 , 1 defect/cm 2 ,

= 3 (is a measure of process complezity)
 252 dice/wafer(rounded wafer, rectangular dice!)
 die yield: 16%
 252 x 16% = only 40 dice / wafer !
► Cost of a die is a strong function of die size (area)
 proportional to the 3 rd or 4 th power of the size
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
Chip
386DX
486DX2
PowerPC
601
HP PA
7100
DEC Alpha
Super
SPARC
Pentium
Interconnect layers
2
3
4
3
3
3
3
MFS Wafer cost defects
/ cm 2
0.90
$900 1.0
0.80
$1200 1.0
0.80
$1700 1.3
Area
(mm 2 )
43
81
121
0.80
0.70
0.70
0.80
$1300
$1500
$1700
$1500
1.0
1.2
1.6
1.5
196
234
256
296 chip
/ wafer
360
181
115 yield Chip cost
71%
54%
28%
$4
$12
$53
66
53
48
40
27%
19%
13%
9%
$73
$149
$272
$417
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Increase of design productivity is behind increase of circuit complexity:
10,000 100,000
1,000
Logic Tr./Chip
Tr./Staff Month.
10,000
100 1,000
10
58%/Yr. compounded
Complexity growth rate
100
1 10
0.1
x x x x
Possible solutions:
21%/Yr. compound
1 x x x
1.
x
Productivity growth rate
DESIGN ON HIGHER ABSTRACTION LEVEL
2.
AUTOMATED PHYSICAL DESIGN (SYNTHESIS)
0.001
0.01
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
Vertical structure: from the manufacturing process
Horizontal structure: from the design
These are separated in space and time
The link between the design and manufacturing is established by the design rules.
This applies to the (lateral) geometry of the devices.
Regarding the operation of the active devices the link between the technology and design is realized by the model parameters which are used in computer simulation (e.g. SPICE simulations).
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20-11-2014 20

Budapest University of Technology and Economics
Department of Electron Devices
► Manufacturing plants (fabs) are more and more expensive
 Order of magnitude of billion US $ (huge CapEx costs)
 Less and less advanced fabs world-wide
► Using the processes is getting also more expensive
 Due to costs of masks, NRE (non-recurring engineering cost) of the advanced IC-s is increasing
► Few fabs – many designers
 waferless fab – e.g. Silicon Labs, Duolog
Design and manufcaturing are strictly separated, but for proper design one has to be aware of the basics of the manufacturing processes and the physical operation of the devices.
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Pre-design
 Example: standard cell design (see details later)
Essentially: We work with pre-design circuit elements
(both in terms of schematics and layout).
► Pre-fabrication (see also pre-fab buildings)
 Extreme example of the pre-fab principle for digital circuits: FPGA (Altera, Xilinx)
FPGA = field programmable gate array
It’s a matrix of logic gates with user programmable interconnections
Includes everything which is needed for a digital circuit. The NRE of manufacturing is distributed over among a huge number of manufactured IC-s. Costs of individual circuit design are only the cost of preparing a HDL description of the circuit.
Most popular realization technique today.
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20-11-2014 22

Budapest University of Technology and Economics
Department of Electron Devices
► MPW – multi-project wafer
 One wafer – joint manufacturing of multiple designs: tipycally 10-20 designs on the same wafer
 Individual design
 Individual fabrication
 costs (NRE-s): 10-20 fold reduction per design
 prototyping / small volume production
See details later
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Abstraction levels
►
►
Typical tools
Design using HDL – see the lab sessions
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
Simulator: Representation: Abstraction level
System simulator
Behavioral description
Specification in VHDL or in Verilog
System level design
Synthesis
Logic simulation Structural description
Logic level design
Schematic editor
Layout generation
Timing parameters
Circuit simulator
Device parameters
Layout description
Transistor level design
Layout editor
Design rules
Process simulation
Ordinary designers do not use such tools.
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Budapest University of Technology and Economics
Department of Electron Devices
►
►
►
►
Circuit entry
 Textual: using hardware description languages or HDLs (e.g.: Verilog,
VHDL)
• behavioral description (Verilog, VHDL, SystemC)
• structural description (Verilog, VHDL)
 Graphical: schematic entry (structural description)
Simulation (on all abstraction levels)
 system level, gate level logic, transistor/circuit
 results visualization tools
 tools for conceptual design, physical design verification tools
High level synthesis: behavioral → RTL → structural
Layout synthesis
On all abstraction levels a given representations of the design – data bases
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Formerly: different in-house HDLs
 exchange / re-use of designs
 standards were needed
VHDL(Very high speed IC Hardware Description Language) : defined by the US DoD (Department of Defence); became the IEEE standard
► Suitable to describe all kinds of electronics systems realized by all kinds of technology
► Abstraction levels where VHDL can be used
 Behavioral : for the description of the algorithm
 Register Transfer Level, RTL : for the description of the data flow
 Structural : logic gate level description
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
► Technology independent description
► Generic language: on structural level description is independent of the characteristics of the assumed elementary building blocks
► Human readable, relatively easy to read
► entity and architecture blocks
 entity: declaration of the name, inputs and outputs and further parameters of the building block
 architecture: description of the operation and some actual physical parameters
• within this: the "instructions" between the begin & end keywords are "executed" at the same time (hardware!)
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20-11-2014 30

Budapest University of Technology and Economics
Department of Electron Devices
► Verilog : an HDL originating from the C language
 "The" language in the CADENCE design environment
 Simple, easy to read, most EDA environments can handle
► SYSTEM C: a new HDL based on C++
 the usual language of hardware-software co-design
 in fact collection of appropriate C++ classes
Synthesis options e.g:
1. SystemC

Verilog converter
2. Verilog

VHDL converter
3. VHDL based synthesis tool
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
VHDL
Verilog
20-11-2014
Using Verilog is dealt with in the lab
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
32

Budapest University of Technology and Economics
Department of Electron Devices
► Like computer programming
► BUT: the result will be a real hardware
E.g. a for (i=0, i<n, i++) like loop means, that the building blocks referred to in the core of the loop must be
"placed" (or instanced) n-times, e.g. connection to an n-bit bus
Discussed during lab
► not know yet what will be the final realization technology.
► The result of technology mapping could be:
 netlist of a full custom IC (base of layout synthesis)
 FPGA (generating a code to be downloaded int an FPGA)
33

Budapest University of Technology and Economics
Department of Electron Devices
► Mentor Graphics:
• some of Mentor's tools are used in the lab
► Cadence:
• Using this suite we demonstrate a complete IC designflow
► Usual platforms (Linux, Windows)
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20-11-2014 34

Budapest University of Technology and Economics
Department of Electron Devices
► Players:
 silicon foundry (e.g. ST, AMS, NXP, ...)
 EDA vendor (pl. Cadence, Mentor, ...)
 Packaging house
 MPW service provider silicon broker (pl. EUROPRACTICE, CMP,
MOSIS)
 end-user who is also the designer is (like us)
► MPW manufacturing = M ultiP roject W afer
 1 Si wafer: 10-15 chips,
 manufacturing runs: every 2-3 months (3-4-5 times a year)
 turnaround: from layout submission to packaged chip: 2-3 months
 sharing the costs (NREs), costs proportional to Si-area
E.g.:
250 EUR/mm 2 , 4 mm 2

1000 EUR + 100 EUR packaging
5 packaged chips, 10 bare dice (66 EUR/chip)
 typical use case: prototyping
 small volume production : pl. 5-6 wafers with the same chip
Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20-11-2014 35

Budapest University of Technology and Economics
Department of Electron Devices
designer 1
MPW service provider designer 2
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 designer 3
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Budapest University of Technology and Economics
Department of Electron Devices
Si-foundry
Design rules, device parameters, standard cell library
Chip layouts united
Si wafer with 10-15
ICs
Packaging house
Bare chips
Packaged ICs
MPW service provider
CAD tool, design kit
Chip layout
Designer and end-user
CAD tool
EDA vendor
Packaged IC
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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Budapest University of Technology and Economics
Department of Electron Devices
20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014
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