Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Design
Methodologies
December 10, 2002
© Digital Integrated Circuits2nd
Design Methodologies
10,000,000
Logic Transistors/Chip
100,000,000
.10m 1,000,000
Transistor/Staff Month
10,000,000
100,000
.35m
10,000
100,000
1,000
10,000
X
100
X x
2.5m
1,000,000
58%/Yr. compound
Complexity growth rate
10
X X
X
1,000
X
100
21%/Yr. compound
Productivity growth rate
2009
2007
2005
2003
2001
10
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
1
Logic Transistors
per Chip (K)
Productivity (Trans./Staff-Month)
Logic Transistors per Chip (K)
The Design Productivity Challenge
Produc
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
A growing gap between design complexity and design productivity
Source: sematech97
© Digital Integrated Circuits2nd
Design Methodologies
A Simple Processor
INPUT/OUTPUT
MEMORY
CONTROL
INPUT-OUTPUT
DATAPATH
© Digital Integrated Circuits2nd
Design Methodologies
A System-on-a-Chip: Example
Courtesy: Philips
© Digital Integrated Circuits2nd
Design Methodologies
None
© Digital Integrated Circuits2nd
1-10
Embedded microprocessor
Configurable/Parameterizable
10-100
Hardwired custom
Energy Efficiency (in MOPS/mW)
100-1000
Domain-specific processor
(e.g. DSP)
Impact of Implementation Choices
0.1-1
Somewhat
flexible
Fully
flexible
Flexibility
(or application scope)
Design Methodologies
Design Methodology
• Design process traverses iteratively between three abstractions:
behavior, structure, and geometry
• More and more automation for each of these steps
© Digital Integrated Circuits2nd
Design Methodologies
Implementation Choices
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Standard Cells
Compiled Cells
© Digital Integrated Circuits2nd
Macro Cells
Array-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
Design Methodologies
The Custom Approach
Intel 4004
© Digital Integrated Circuits2nd
Courtesy Intel
Design Methodologies
Transition to Automation and Regular Structures
Intel 4004 (‘71)
Intel 8080
Intel 8286
© Digital Integrated Circuits2nd
Intel 8085
Intel 8486
Courtesy Intel
Design Methodologies
Cell-based Design (or standard cells)
Routing channel
requirements are
reduced by presence
of more interconnect
layers
© Digital Integrated Circuits2nd
Design Methodologies
Standard Cell — Example
[Brodersen92]
© Digital Integrated Circuits2nd
Design Methodologies
Standard Cell – The New Generation
Cell-structure
hidden under
interconnect layers
© Digital Integrated Circuits2nd
Design Methodologies
Standard Cell - Example
3-input NAND cell
(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time
© Digital Integrated Circuits2nd
Design Methodologies
Automatic Cell Generation
Initial transistor
geometries
© Digital Integrated Circuits2nd
Placed
transistors
Routed
cell
Compacted
cell
Courtesy Acadabra
Finished
cell
Design Methodologies
A Historical Perspective: the PLA
Product terms
x0 x1
x2
AND
plane
OR
plane
f0
x0
© Digital Integrated Circuits2nd
x1
f1
x2
Design Methodologies
Two-Level Logic
Every logic function can be
expressed in sum-of-products
format (AND-OR)
minterm
Inverting format (NORNOR) more effective
© Digital Integrated Circuits2nd
Design Methodologies
PLA Layout – Exploiting Regularity
And-Plane
V DD
x0 x0 x1 x1 x2 x2
Pull-up devices
© Digital Integrated Circuits2nd
Or-Plane
f
GND
f0 f1
Pull-up devices
Design Methodologies
Breathing Some New Life in PLAs
River PLAs

BUFFER
PRE-CHARGE

A cascade of multiple-output PLAs.
Adjacent PLAs are connected via river routing.
PRE-CHARGE
BUFFER
PRECHARGE
BUFFER
PRE-CHARGE
BUFFER
PRE-CHARGE
BUFFER
PRE-CHARGE
BUFFER
PRECHARGE
BUFFER
BUFFER
© Digital Integrated Circuits2nd
PRE-CHARGE
• No placement and routing needed.
• Output buffers and the input buffers
of the next stage are shared.
Courtesy B. Brayton
Design Methodologies
Area:
RPLAs (2 layers)
1.23
SCs (3 layers) 1.00,
NPLAs (4 layers)
1.31
Delay
RPLAs
1.04
SCs
1.00
NPLAs
1.09
Synthesis time: for RPLA , synthesis time equals design time;
SCs and NPLAs still need P&R.
delay
Experimental Results
1.4
1
0.6
Also: RPLAs are regular and predictable
0.2
0
Layout of C2670
Standard cell,
2 layers channel routing
© Digital Integrated Circuits2nd
2
SC
Standard cell,
3 layers OTC
Network of PLAs,
4 layers OTC
4
NPLA
6
area
RPLA
River PLA,
2 layers no additional routing
Design Methodologies
MacroModules
25632 (or 8192 bit) SRAM
Generated by hard-macro module generator
© Digital Integrated Circuits2nd
Design Methodologies
“Soft” MacroModules
© Digital Integrated Circuits2nd
Synopsys DesignCompiler
Design Methodologies
“Intellectual Property”
A Protocol Processor for Wireless
© Digital Integrated Circuits2nd
Design Methodologies
Semicustom Design Flow
Design Capture
Behavioral
HDL
Design Iteration
Pre-Layout
Simulation
Structural
Logic Synthesis
Floorplanning
Post-Layout
Simulation
Placement
Circuit Extraction
Routing
Physical
Tape-out
© Digital Integrated Circuits2nd
Design Methodologies
The “Design Closure” Problem
Iterative Removal of Timing Violations (white lines)
© Digital Integrated Circuits2nd
Courtesy Synopsys
Design Methodologies
Integrating Synthesis with
Physical Design
RTL (Timing) Constraints
Physical Synthesis
Macromodules
Fixed netlists
Netlist with
Place-and-Route Info
Place-and-Route
Optimization
© Digital Integrated Circuits2nd
Artwork
Design Methodologies
Late-Binding Implementation
Array-based
Pre-diffused
(Gate Arrays)
© Digital Integrated Circuits2nd
Pre-wired
(FPGA's)
Design Methodologies
Gate Array — Sea-of-gates
polysilicon
VD D
rows of
uncommitted
cells
metal
possible
contact
GND
In1 In 2
Uncommited
Cell
In3 In4
routing
channel
Committed
Cell
(4-input NOR)
Out
© Digital Integrated Circuits2nd
Design Methodologies
Sea-of-gate Primitive Cells
Oxide-isolation
PMOS
PMOS
NMOS
NMOS
NMOS
Using oxide-isolation
© Digital Integrated Circuits2nd
Using gate-isolation
Design Methodologies
Example: Base Cell of Gate-Isolated GA
© Digital Integrated Circuits2nd
From Smith97
Design Methodologies
Example: Flip-Flop in Gate-Isolated GA
© Digital Integrated Circuits2nd
From Smith97
Design Methodologies
Sea-of-gates
Random Logic
Memory
Subsystem
LSI Logic LEA300K
(0.6 mm CMOS)
© Digital Integrated Circuits2nd
Courtesy LSI Logic
Design Methodologies
The return of gate arrays?
Via programmable gate array
(VPGA)
Via-programmable cross-point
metal-5
metal-6
programmable via
Exploits regularity of interconnect
© Digital Integrated Circuits2nd
[Pileggi02]
Design Methodologies
Prewired Arrays
Classification of prewired arrays (or fieldprogrammable devices):

Based on Programming Technique
 Fuse-based (program-once)
 Non-volatile EPROM based
 RAM based

Programmable Logic Style
 Array-Based
 Look-up Table

Programmable Interconnect Style
 Channel-routing
 Mesh networks
© Digital Integrated Circuits2nd
Design Methodologies
Fuse-Based FPGA
antifuse polysilicon
ONO dielectric
n+ antifuse diffusion
2l
Open by default, closed by applying current pulse
© Digital Integrated Circuits2nd
From Smith97
Design Methodologies
Array-Based Programmable Logic
I5
I4
I3
I2
I1
I0
Programmable
OR array
Programmable AND array
I3
I2
I1
I0
Programmable
OR array
Fixed AND array
O 3O 2O 1O 0
PLA
I5
I4
I3
I2
I1
I0
Fixed OR array
Programmable AND array
O3O2O1O0
PROM
O 3O 2O 1O 0
PAL
Indicates programmable connection
Indicates fixed connection
© Digital Integrated Circuits2nd
Design Methodologies
Programming a PROM
1
X2
X1
X0
: programmed node
NA NA f 1 f 0
© Digital Integrated Circuits2nd
Design Methodologies
More Complex PAL
i inputs, j minterms/macrocell, k macrocells
© Digital Integrated Circuits2nd
From Smith97
Design Methodologies
2-input mux
as programmable logic block
Configuration
A
0
F
B
1
S
© Digital Integrated Circuits2nd
A
B
S
F=
0
0
0
0
X
Y
Y
1
1
1
0
X
Y
Y
0
0
1
0
0
1
0
1
1
X
Y
X
X
X
Y
1
0
X
Y
XY
XY
XY
X1 Y
X
Y
1
Design Methodologies
Logic Cell of Actel Fuse-Based FPGA
A
B
1
SA
Y
1
C
D
1
SB
S0
S1
© Digital Integrated Circuits2nd
Design Methodologies
Memory
Look-up Table Based Logic Cell
Out
In
Out
00
00
01
1
10
1
11
0
ln1 ln2
© Digital Integrated Circuits2nd
Design Methodologies
LUT-Based Logic Cell
Figure must be
updated
4
C1....C4
xx
xxxx
xxxx
xxxx
Bits
control
D4
D3
D2
Logic
function
of
xxx
D1
Logic
functionx
of
xxx
F4
F3
F2
F1
xx
xx
xx
xx
Logic
function
of
xxx
x
xxxxx
Xilinx 4000 Series
© Digital Integrated Circuits2nd
xxxx
xx
x xx x
xx xx
x
x
x
x
Bits
control
xx
xx
xx
xx
xxxx
x xx x
xx
xx xx
H
P
x
x
Multiplexer Controlled
by Configuration Program
Courtesy Xilinx
Design Methodologies
Array-Based Programmable Wiring
M
Interconnect
Point
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks
© Digital Integrated Circuits2nd
Design Methodologies
Mesh-based Interconnect Network
Switch Box
Connect Box
Interconnect
Point
© Digital Integrated Circuits2nd
Courtesy Dehon and Wawrzyniek
Design Methodologies
Transistor Implementation of Mesh
© Digital Integrated Circuits2nd
Courtesy Dehon and Wawrzyniek
Design Methodologies
Hierarchical Mesh Network
Use overlayed mesh
to support longer connections
Reduced fanout and reduced
resistance
© Digital Integrated Circuits2nd
Courtesy Dehon and Wawrzyniek
Design Methodologies
EPLD Block Diagram
Macrocell
Primary inputs
© Digital Integrated Circuits2nd
Courtesy Altera
Design Methodologies
Altera MAX
© Digital Integrated Circuits2nd
From Smith97
Design Methodologies
Altera MAX Interconnect Architecture
column channel
row channel
t PIA
LAB1
LAB2
LAB
PIA
t PIA
LAB6
Array-based
(MAX 3000-7000)
© Digital Integrated Circuits2nd
Mesh-based
(MAX 9000)
Courtesy Altera
Design Methodologies
Field-Programmable Gate Arrays
Fuse-based
I/O Buffers
Program/Test/Diagnostics
Vertical routes
I/O Buffers
I/O Buffers
Standard-cell like
floorplan
Rows of logic modules
Routing channels
I/O Buffers
© Digital Integrated Circuits2nd
Design Methodologies
Xilinx 4000 Interconnect Architecture
CLB
12
Quad
8
Single
4
Double
3
Long
2
3
12
4
4
8
Quad
Long
Global
Long
Clock
© Digital Integrated Circuits2nd
4
8
4
Double Single Global
Direct
Connect
Long
2
Carry
Direct
Clock Chain Connect
Courtesy Xilinx
Design Methodologies
RAM-based FPGA
Xilinx XC4000ex
© Digital Integrated Circuits2nd
Courtesy Xilinx
Design Methodologies
A Low-Energy FPGA (UC Berkeley)
Array Size: 8x8 (2 x 4
LUT)
 Power Supply: 1.5V &
0.8V
 Configuration: Mapped as
RAM
 Toggle Frequency:
125MHz
 Area: 3mm x 3mm

© Digital Integrated Circuits2nd
Design Methodologies
Larger Granularity FPGAs
PADDI-2 (UC Berkeley)

1-mm 2-metal
CMOS tech

1.2 x 1.2 mm2

600k transistors

208-pin PGA

fclock = 50 MHz
 Pav =

© Digital Integrated Circuits2nd
3.6 W @ 5V
Basic Module: Datapath
Design Methodologies
Design at a crossroad
500 k Gates FPGA
MultiSpectral
+ 1 Gbit DRAM
RAM
Imager
Preprocessing
64 SIMD Processor
Array + SRAM
Image Conditioning
100 GOPS
Analog
System-on-a-Chip
mC
system
+2 Gbit
DRAM
Recognition





© Digital Integrated Circuits2nd
Embedded applications
where cost, performance,
and energy are the real
issues!
DSP and control intensive
Mixed-mode
Combines programmable
and application-specific
modules
Software plays crucial role
Design Methodologies
Addressing the Design Complexity Issue
Architecture Reuse
Reuse comes in generations
Generation
Reuse element
Status
1st
Standard cells
Well established
2nd
IP blocks
Being introduced
3rd
Architecture
Emerging
4th
IC
Early research
Source: Theo Claasen (Philips) – DAC 00
© Digital Integrated Circuits2nd
Design Methodologies
Architecture ReUse

Silicon System Platform






Flexible architecture for hardware and software
Specific (programmable) components
Network architecture
Software modules
Rules and guidelines for design of HW and SW
Has been successful in PC’s
 Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints)




Speed (compute power)
Dissipation
Costs
Real / non-real time data
© Digital Integrated Circuits2nd
Design Methodologies
Platform-Based Design
“Only the consumer gets freedom of choice;
designers need freedom from choice”
(Orfali, et al, 1996, p.522)




A platform is a restriction on the space of possible implementation
choices, providing a well-defined abstraction of the underlying
technology for the application developer
New platforms will be defined at the architecture-micro-architecture
boundary
They will be component-based, and will provide a range of choices
from structured-custom to fully programmable implementations
Key to such approaches is the representation of communication in
the platform model
© Digital Integrated Circuits2nd
Source:R.Newton
Design Methodologies
Berkeley Pleiades Processor
• 0.25um 6-level metal CMOS
FPGA
• 5.2mm x 6.7mm
• 1.2 Million transistors
Reconfigurable
Data-path
• 40 MHz at 1V
• 2 extra supplies: 0.4V, 1.5V
Interface
ARM8 Core
© Digital Integrated Circuits2nd
• 1.5~2 mW power dissipation
Design Methodologies
Heterogeneous Programmable Platforms
FPGA Fabric
Embedded memories
Embedded PowerPc
Hardwired multipliers
Xilinx Vertex-II Pro
High-speed I/O
© Digital Integrated Circuits2nd
Courtesy Xilinx
Design Methodologies
Summary
Digital CMOS Design is kicking and healthy
 Some major challenges down the road
caused by Deep Sub-micron

 Super GHz design
 Power consumption!!!!
 Reliability – making it work
Some new circuit solutions are bound to emerge

Who can afford design in the years to come?
Some major design methodology change in
the making!
© Digital Integrated Circuits2nd
Design Methodologies