Chapter 3
Solid-State Diodes and Diode Circuits
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Modified by Ming Ouhyoung
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Chap 3 -1
Chapter Goals
• Understand diode structure and basic layout
• Develop electrostatics of the pn junction
• Explore various diode models including the mathematical model, the
ideal diode model, and the constant voltage drop model
• Understand the SPICE representation and model parameters for the
diode
• Define regions of operation of the diode (forward bias, reverse bias,
and reverse breakdown)
• Apply the various types of models in circuit analysis
• Explore different types of diodes
• Discuss the dynamic switching behavior of the pn junction diode
• Explore diode applications
• Practice simulating diode circuits using SPICE
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Chap 3 -2
Diode Introduction
• A diode is formed by joining
an n-type semiconductor
with a p-type semiconductor.
• A pn junction is the
interface between n and p
regions.
Diode symbol
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Chap 3 -3
metallurgical junction
• plane in the p-n junction at which concentration of
acceptors is the same as concentration of donors.
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pn Junction Electrostatics
Donor and acceptor concentration
on either side of the junction.
Concentration gradients give rise
to diffusion currents.
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Chap 3 -5
Diffusion
• Diffusion from a microscopic and macroscopic point of
view. Initially, there are solute molecules on the left side of
a barrier (purple line) and none on the right. The barrier is
removed, and the solute diffuses to fill the whole container.
Top: A single molecule moves around randomly.
• Middle: With more molecules, there is a clear trend where
the solute fills the container more and more uniformly.
Bottom: With an enormous number of solute molecules, all
apparent randomness is gone: The solute appears to move
smoothly and systematically from high-concentration areas
to low-concentration areas following Fick’s laws.
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Drift Currents
• Diffusion currents lead to localized charge density variations near the
pn junction.
• Gauss’ law predicts an electric field due to the charge distribution:
c
E 
s
• Assuming constant permittivity,
1
 E(x)  
s
  (x)dx
• Resulting electric field gives rise to a drift current. With no external
circuit connections, drift and diffusion currents cancel. There is no
actual current, since this would imply power dissipation, rather the
electric field
 cancels the diffusion current ‘tendency.’
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Chap 3 -8
Space-Charge Region Formation
at the pn Junction
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Chap 3 -9
Potential Across the Junction
Charge Density
Electric Field
Potential
 N AN D 
kT


 j   E ( x)dx  VT ln 
, VT 
2

q
 ni 

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Chap 3 -10
Width of Depletion Region (Example)
Problem: Find built-in potential and depletion-region width for given diode
Given data: On p-type side: NA = 1017/cm3 on n-type side: ND = 1020/cm3
Assumptions: Room-temperature operation with VT = 0.025 V


 N AN D 
 1017 /cm3 10 20 /cm3
 j  VT ln  2   0.025 V * ln 
20
6
10 /cm
 ni 

0.979 V
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

Chap 3 -11
 

• εs = 11.7 εo, where εo = 8.85*10-14 F/cm q = 1.60*10-19 C
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Internal Diode Currents
Mathematically, for a diode with no external connections, the total current
expressions developed in Chapter 2 are equal to zero. The equations only
dictate that the total currents are zero. However, as mentioned earlier,
since there is no power dissipation, we must assume that the field and
diffusion current tendencies cancel and the actual currents are zero.
n
=0
x
p
T
j p  q p pE  qDp
=0
x
j nT  q n nE  qDn
When external bias voltage is applied to the diode, the above equations are
no longer equal to zero.

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Chap 3 -13
3.2 The i-v characteristics of the diode
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Diode Junction Potential for Different
Applied Voltages
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Chap 3 -15
Diode i-v Characteristics
The turn-on voltage marks the point of significant current flow.
Is is called the reverse saturation current.
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Chap 3 -16
3.3 The Diode Equation
  v
 qv D  
i D  I S exp 
1 I S exp  D
 nkT  
 nVT
where

IS
vD
q
k
T
n
VT
=
=
=
=
=
=
=
 
1
 
reverse saturation current (A)
voltage applied to diode (V)
electronic charge (1.60 x 10-19 C)
Boltzmann’s constant (1.38 x 10-23 J/K)
absolute temperature
nonideality factor (dimensionless)
kT/q = thermal voltage (V) (25 mV at room temp.)
IS is typically between 10-18 and 10-9 A, and is strongly temperature dependent due
to its dependence on ni2. The nonideality factor is typically close to 1, but
approaches 2 for devices with high current densities. It is assumed to be 1 in this
text.
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Chap 3 -17
IS, the reverse bias saturation current for an ideal p-n diode is given by, (Schubert 2006, 61)
where
IS is the reverse bias saturation current,
e is elementary charge
A is the cross-sectional area
Dp,n are the diffusion coefficients of holes and electrons, respectively,
ND,A are the donor and acceptor concentrations at the n side and p side, respectively,
ni is the intrinsic carrier concentration in the semiconductor material,
τp,n are the carrier lifetimes of holes and electrons, respectively.
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Diode Voltage and Current Calculations
(Example)
Problem: Find diode voltage for diode with given specifications
Given data: IS = 0.1 fA, ID = 300 A
Assumptions: Room-temperature dc operation with VT = 0.025 V
Analysis:
With IS = 0.1 fA

With IS = 10 fA




-4
ID 
VD  nVT ln1 1(0.0025V )ln(1 310 A) 0.718 V
IS 
10-16 A
VD 0.603V

VD  0.748V
With ID = 1 mA, IS = 0.1 fA

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Chap 3 -19
3.4 Diode characteristics under Reverse,
Zero, and Forward bias
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Diode Current for Reverse, Zero, and
Forward Bias
• Reverse bias:
  v  
iD  IS exp D 1 IS 0 1  IS
 nVT  
• Zero bias:
  v  
iD  IS exp D 1 IS 11  0
 nVT  
 bias:
• Forward

  v  
 v D 
D
iD  IS exp
1 IS exp

nVT 
 nVT  
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Chap 3 -21
Semi-log Plot of Forward Diode Current and
Current for Three Different Values of IS
I S [ A]  10I S [B]  100 I S [C]

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Chap 3 -22
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3.5 Diode Temperature Coefficient
Diode voltage under forward bias:
iD  kT iD  kT iD 
v D  VT ln   1
ln   1
ln  
IS  q IS  q IS 
Taking the derivative with respect to temperature yields
dvD k i D  kT 1 dI S v D
1 dI S v D  VGO  3VT
 ln 

 VT

dT
q I S  q I S dT
T
I S dT
T
V/K

Assuming iD >> IS, IS  ni2, and VGO is the silicon bandgap energy at 0K.
For a typical silicon diode

dvD 0.65  1.12  0.075 V

= -1.82 mV/K  - 1.8 mV/ C
dT
300 K
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Chap 3 -26
The Nobel Prize in Chemistry 2011 is awarded to
Dan Shechtman for the discovery of quasicrystals.
• The achievement of Dan Shechtman is clearly not only the
discovery of quasicrystals, but the realization of the
importance of this result and the determination to
communicate it to a skeptical scientific community.
• 盡信書，不如無書
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• To make the discovery even more astounding, Shechtman
found that by rotating the sample he could identify
additional 5-fold axes as well as 3-fold and 2-fold. It
became clear that the symmetry of his sample was not
merely 5-fold but icosahedral (figure 4).
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Figure 4. Original electron diffraction images taken by Dan
Shechtman. The angular relationship between the various
zones examined by Shechtman shows that the sample exhibits
icosahedral symmetry6.
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Figure 7. Pentagonal Penrose tiling.
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• An important discovery that helped pave the way for the
understanding of the discovery of quasicrystals was the construction
and analysis by Penrose of his famous pentagonal tiling. The
pentagonal Penrose tiling (figure 7) is a self-similar pattern with 5fold symmetry, long-range order and no translational periodicity. de
Bruijn applied the higher dimensional approach to Penrose tiles, and
Mackay subjected an image of the vertices of a Penrose tiling to
optical diffraction and was able to show that it has a discrete
diffraction diagram. These early results were certainly instrumental in
allowing Levine and Steinhardt to accomplish their remarkable early
analysis (and resulting paper) on quasicrystals, and helped establish
the credibility of the discovery.
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Properties of quasicrystals
• Intermetallic quasicrystals are typically hard and brittle
materials with unusual transport properties and very low
surface energies. Thermal and electronic transport in solid
materials is normally enhanced by phonons and Bloch
waves that develop as a consequence of the periodic
• nature of crystals.
• The low surface energy of quasicrystals make them
corrosion- and adhesion-resistant and imparts them with
low friction coefficients.
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Surface energy
• Surface energy quantifies the disruption of intermolecular
bonds that occur when a surface is created. In the physics
of solids, surfaces must be intrinsically less energetically
favorable than the bulk of a material, otherwise there
would be a driving force for surfaces to be created,
removing the bulk of the material.
• The surface energy may therefore be defined as the excess
energy at the surface of a material compared to the bulk.
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Reverse Bias
External reverse bias adds to the built-in potential of the pn
junction. The shaded regions below illustrate the increase in the
characteristics of the space charge region due to an externally
applied reverse bias, vD.
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Chap 3 -37
Reverse Bias (cont.)
External reverse bias also increases the width of the depletion
region since the larger electric field must be supported by
additional charge.
2 s  1
1 
w d  (x n  x p ) 
 
 j  v R
q N A N D 

wd  wd 0


vR
1
j
2 s  1
1 
where w d 0  (x n  x p ) 
 
 j
q N A N D 

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Chap 3 -38
Reverse Bias Saturation Current
We earlier assumed that the reverse saturation current was constant.
Since it results from thermal generation of electron-hole pairs in
the depletion region, it is dependent on the volume of the space
charge region. It can be shown that the reverse saturation gradually
increases with increased reverse bias.
I S  I S0 1
vR
j
IS is approximately constant at IS0 under forward bias.

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Chap 3 -39
Reverse Breakdown
Increased reverse bias
eventually results in the diode
entering the breakdown
region, resulting in a sharp
increase in the diode current.
The voltage at which this
occurs is the breakdown
voltage, VZ.
2 V < VZ < 2000 V
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Chap 3 -40
Reverse Breakdown Mechanisms
• Avalanche Breakdown
Si diodes with VZ greater than about 5.6 volts breakdown according to
an avalanche mechanism. As the electric field increases, accelerated
carriers begin to collide with fixed atoms. As the reverse bias
increases, the energy of the accelerated carriers increases, eventually
leading to ionization of the impacted ions. The new carriers also
accelerate and ionize other atoms. This process feeds on itself and
leads to avalanche breakdown.
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Chap 3 -41
Reverse Breakdown Mechanisms (cont.)
• Zener Breakdown
Zener breakdown occurs in heavily doped diodes. The heavy doping
results in a very narrow depletion region at the diode junction.
Reverse bias leads to carriers with sufficient energy to tunnel directly
between conduction and valence bands moving across the junction.
Once the tunneling threshold is reached, additional reverse bias leads
to a rapidly increasing reverse current.
• Breakdown Voltage Temperature Coefficient
Temperature coefficient is a quick way to distinguish breakdown
mechanisms. Avalanche breakdown voltage increases with
temperature, whereas Zener breakdown decreases with temperature.
For silicon diodes, zero temperature coefficient is achieved at
approximately 5.6 V.
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Chap 3 -42
Breakdown Region Diode Model
In breakdown, the diode is
modeled with a voltage source,
VZ, and a series resistance, RZ.
RZ models the slope of the i-v
characteristic.
Diodes designed to operate in
reverse breakdown are called
Zener diodes and use the
indicated symbol.
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Chap 3 -43
Reverse Bias Capacitance
Changes in voltage lead to changes in depletion width and charge.
This leads to a capacitance that we can calculate from the chargevoltage dependence.
 N N 
Qn  qN D x n A  q A D w d A Coulombs
N A  N D 

C j0 A
dQn


Cj 

 s F/cm 2 where C j 0  s
dvR
wd
wd 0
vR
1
j
Cj0 is the zero bias junction capacitance per unit area.
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Chap 3 -44
Reverse Bias Capacitance (cont.)
Diodes can be designed with hyper-abrupt doping profiles that
optimize the reverse-biased diode as a voltage controlled capacitor.
Circuit symbol for the variable
capacitance diode (Varactor)
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Chap 3 -45
Forward Bias Capacitance
In forward bias operation, additional charge is stored in neutral
region near edges of space charge region.
QD  iD T Coulombs
T is called diode transit time and ranges from 10-15 to more than
10-6 s depending on size and type of diode.
Additional diffusion capacitance, associated with forward region
of operation is proportional to current and becomes quite large at
high currents.
dQD iD  IS  T iD  T
Cj 


F
dv D
VT
VT
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Chap 3 -46
3.8 Schottky Barrier Diode
One semiconductor region of the pn
junction diode can be replaced by a
non-ohmic rectifying metal contact.
A Schottky contact is easily formed
on n-type silicon. The metal region
becomes the anode. An n+ region is
added to ensure that the cathode
contact is ohmic.
Schottky diodes turn on at a lower
voltage than pn junction diodes and
have significantly reduced internal
charge storage under forward bias.
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Chap 3 -47
3.9 Diode Spice Model
Rs represents the inevitable series
resistance of a real device structure. The
current controlled current source
models the ideal exponential behavior
of the diode. Capacitor C includes
depletion-layer capacitance for the
reverse-bias region as well as diffusion
capacitance associated with the junction
under forward bias.
Typical default values: Saturation
current IS = 10 fA, Rs = 0 W, transit
time TT = 0 seconds, N = 1
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Chap 3 -48
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Diode Layout
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Chap 3 -50
3.10 Diode Circuit Analysis: Basics
The loop equation for the diode circuit is:
V  I D R  VD
V and R may represent the Thévenin
equivalent of a more complex 2terminal network. The objective of
diode circuit analysis is to find the
quiescent operating point for the
diode.
Q-Point = (ID, VD)
This is also called the load line for the
diode. The solution to this equation can
be found by:
• Graphical analysis using the load-line
method.
• Analysis with the diode’s mathematical
model.
• Simplified analysis with the ideal diode
model.
• Simplified analysis using the constant
voltage drop (CVD) model.
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Chap 3 -51
Load-Line Analysis (Example)
Problem: Find diode Q-point
Given data: V = 10 V, R = 10kW.
Analysis:
10  I D104  VD
To define the load line we use,
For VD  0, ID  10V 10kW  1 mA
For VD  5V, ID  5V 10kW  0.5 mA

These points and the resulting
load line are plotted.Q-point is
given by intersection of load line
and diode characteristic:
Q-point = (0.95 mA, 0.6 V)
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Chap 3 -52
Analysis using Mathematical Model for
Diode
Problem: Find the Q-point for a given
diode characteristic.
Given data: IS =10-13 A, n=1, VT =0.0025 V
Analysis:
•Make initial guess VD0 .
•Evaluate f and its derivative f’ for this
value of VD.
•Calculate new guess for VD using
 
0
VD  VD
1
0
f VD

0
f ' (VD )
 V  
I D  I S exp  D   1  1013exp 40VD   1
•Repeat steps 2 and 3 till convergence.
  nVT  
Using a spreadsheet we get :
10  1041013exp 40VD   1  VD
Q-point = ( 0.9426 mA, 0.5742 V)
The solution is given by a transcendental
equation. A numerical answer can be found
by using Newton’s iterative method.
f  10  1041013exp 40VD   1  VD
Since, usually we don’t have accurate
saturation current values and significant
tolerances exist for sources and passive
components, we need answers precise to
only 2or 3 significant digits.
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Chap 3 -53
Newton’s method
f ' (VD ) 
0
     0  f V 
f VD1  f VD 0
VD1  VD 0
0
D
VD1  VD 0
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Analysis using Ideal Model for Diode
If an ideal diode is forward-biased, the voltage
across the diode is zero. If an ideal diode is
reverse-biased, the current through the diode is
zero.
vD = 0 for iD > 0 and iD = 0 for vD < 0
Thus, the diode is assumed to be either on or off.
Analysis is conducted in following steps:
• Select a diode model.
• Identify anode and cathode of the diode and
label vD and iD.
• Guess diode’s region of operation from circuit.
• Analyze circuit using diode model appropriate
for assumed region of operation.
• Check results to check consistency with
assumptions.
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Chap 3 -55

Analysis using Ideal Model for Diode:
Example
Since source is forcing current backward
through diode assume diode is off. Hence
ID = 0 . Loop equation is:
10  VD  10 4 ID  0
Since source appears to force positive
current through diode, assume diode is on.
(10  0)V
ID 
 1 mA | ID  0
10kW
Our assumption is correct, and the
Q-Point = (1 mA, 0V)
VD  10V | VD  0
Our assumption is correct and the
Q-Point = (0, -10 V)

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Chap 3 -56
Analysis using Constant Voltage Drop
Model for Diode
Analysis:
Since the 10-V source appears to force positive
current through the diode, assume diode is on.
(10  Von )V
10kW
(10  0.6)V

 0.940 mA
10kW
ID 
vD = Von for iD > 0 and
vD = 0 for vD < Von.
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Chap 3 -57
Two-Diode Circuit Analysis
Analysis: The ideal diode model is chosen. Since the
15-V source appears to force positive current through
D1 and D2, and the -10-V source is forcing positive
current through D2, assume both diodes are on.
Since the voltage at node D is zero due to the short
circuit of ideal diode D1,
(15  0)V
 1.50 mA
10kW
0  10V 
ID 2 
 2.00 mA
5kW
I1  ID1  ID 2 | ID1  1.50  2.00  0.500 mA
I1 
The Q-points are (-0.5 mA, 0 V) and (2.0 mA, 0 V)

But, ID1 < 0 is not allowed by the diode, so try again.
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Chap 3 -58
Two-Diode Circuit Analysis (contd.)
Since the current in D1 is zero, ID2 = I1,
Analysis: Since current in
D2 is valid, but that in D1 is
not, the second guess is D1
off and D2 on.
1510,000I1  5,000ID2 (10) 0
25V
I1 
1.67 mA
15,000W
VD1 1510,000I1 1516.7  1.67 V

Q-Points are D1 : (0 mA, -1.67 V):off
D2 : (1.67 mA, 0 V) :on
Now, the results are consistent with the
assumptions.
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McGraw-Hill
Chap 3 -59
3.12 Analysis of Diodes in Reverse
Breakdown Operation
Choose 2 points (0V, -4 mA) and (-5 V, -3 mA)
to draw the load line. It intersects the i-v
characteristic at the Q-point: (-2.9 mA, -5.2 V).
Using the piecewise linear model:
IZ ID 0

205100IZ 5 0
(205)V
IZ 
 2.94 mA
5100W
Using load-line analysis:
 20VD 5000I D
Since IZ > 0 (ID < 0), the solution is

consistent
with Zener breakdown.
Microelectronic Circuit Design, 4E
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Chap 3 -60
Voltage Regulator Using the Zener Diode
VS VZ (205)V

 3 mA
R
5kW
V
5V
IL  Z 
1 mA | IZ  IS  IL  2 mA
RL 5kW
IS 

The Zener diode keeps the
voltage across load resistor
RL constant. For Zener
breakdown operation, IZ > 0.
For proper regulation, Zener current must be
positive. If the Zener current < 0, the Zener
diode no longer controls the voltage across
the load resistor and the voltage regulator is
said to have “dropped out of regulation”.


VS
R
1
1

IZ  VZ    0 | RL  
R

R
R
min
R

L 
V

 S 1


V

 Z

Microelectronic Circuit Design, 4E

McGraw-Hill
Chap 3 -61
Voltage Regulator Using a Zener Diode:
Example Including Zener Resistance
VL  20V VL  5V  VL  0
5000W 100W 5000W
VL  5.19 V
Problem: Find the output voltage
and Zener diode current for a Zener
diode regulator.
Given data: VS = 20 V, R = 5 kW,
RZ = 0.1 kW,VZ = 5 V
Analysis: The output voltage is a
function of the current through the
Zener diode.
I Z  VL  5V  5.19V  5V 1.9 mA  0
100W
100W
Microelectronic Circuit Design, 4E
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Chap 3 -62
Line and Load Regulation
Line regulation characterizes how sensitive the output voltage is to input
voltage changes. (Circuit on previous page, Figure 3.41)
Line Regulation
dVL
dVS
mV/V
For a fixed load current, Line Regulation =
RZ
R+ RZ
Load regulation characterizes how sensitive the output voltage is to
changes
in load current withdrawn from regulator.

dV
Load Regulation L W
dIL
For changes in load current, Load Regulation RZ R
Load regulation is the Thévenin equivalent resistance looking back
into the regulator from the load terminals.
Microelectronic Circuit Design, 4E
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Chap 3 -63
Rectifier Circuits
• A basic rectifier converts an ac voltage to a pulsating dc voltage.
• A filter then eliminates ac components of the waveform to
produce a nearly constant dc voltage output.
• Rectifier circuits are used in virtually all electronic devices to
convert the 120-V 60-Hz ac power line source to the dc voltages
required for operation of electronic devices.
• In rectifier circuits, the diode state changes with time and a given
piecewise linear model is valid only for a certain time interval.
Microelectronic Circuit Design, 4E
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Chap 3 -64
Half-Wave Rectifier Circuit with
Resistive Load
For the positive half-cycle of the input, the source forces positive current
through the diode, the diode is on, and vO = vS.
During the negative half cycle, negative current can’t exist in the diode.
The diode is off, current in resistor is zero, and vO = 0 .
Microelectronic Circuit Design, 4E
McGraw-Hill
Chap 3 -65
Half-Wave Rectifier Circuit with
Resistive Load (cont.)
Using the constant voltage drop CVD model,
during the on-state of the diode vO = (VP sinwt)Von. The output voltage is zero when the diode is
off.
Often a step-up or step-down transformer is used
to convert the 120-V, 60-Hz voltage available
from the power line to the desired ac voltage
level as shown.
Time-varying components in the rectifier output
are removed using a filter capacitor.
Microelectronic Circuit Design, 4E
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Chap 3 -66
Peak Detector Circuit
As the input voltage rises, the diode is on,
and the capacitor (initially discharged)
charges up to the input voltage minus the
diode voltage drop.
At the peak of the input voltage, diode
current tries to reverse, and the diode cuts
off. The capacitor has no discharge path
and retains a constant voltage providing a
constant output voltage:
Vdc = VP - Von
Microelectronic Circuit Design, 4E
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Chap 3 -67
Half-Wave Rectifier Circuit with RC Load
As the input voltage rises during the first quarter
cycle, the diode is on and the capacitor (initially
discharged) charges up to the peak value of the
input voltage.
At the peak of the input, the diode current tries
to reverse, the diode cuts off, and the capacitor
discharges exponentially through R. Discharge
continues till the input voltage exceeds the
output voltage which occurs near the peak of
next cycle. This process then repeats once every
cycle.
Microelectronic Circuit Design, 4E
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Chap 3 -68
Peak Diode Current
In rectifiers, nonzero current exists in the
diode for only a very small fraction of
period T, yet an almost constant dc current
flows out of the filter capacitor to load.
The total charge lost from the filter
capacitor in each cycle is replenished by the
diode during a short conduction interval
causing high peak diode currents.
Microelectronic Circuit Design, 4E
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Chap 3 -69
Peak Inverse Voltage Rating
The peak inverse voltage (PIV) rating of
the rectifier diode is the diode
breakdown voltage.
When the diode is off, the reverse-bias
across the diode is Vdc - vS. When vS
reaches negative peak,
PIVVdc vsmin VP Von (VP )2VP

The PIV value corresponds to the
minimum value of Zener breakdown
voltage required for the rectifier diode.
Microelectronic Circuit Design, 4E
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Chap 3 -70
Microelectronic Circuit Design, 4E
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AM demodulation
Microelectronic Circuit Design, 4E
McGraw-Hill
AM Demodulation
• The waveform for a 100% amplitude modulated (AM)
signal is shown in the figure below and described
mathematically by vAM = 2(1+sin ωMt) sin ωCt V in which
ωC is the carrier frequency (fC = 50 kHz) and ωM is the
modulating frequency (fM = 5 kHz).
• The envelope of the AM signal contains the information
being transmitted, and the envelope can be recovered from
the signal using a simple half-wave rectifier.
• The R2C1 time constant is set to filter out the carrier
frequency but follow the signal’s envelope.
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Microelectronic Circuit Design, 4E
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Microelectronic Circuit Design, 4E
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Microelectronic Circuit Design, 4E
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First-order Linear Circuits
•
•
•
•
•
ReqiC + vC = vOC (t)
Q=C*v
i = dQ/dt
iC = C dv/dt
vC(t) = vOC (1 – e(-t/ReqC) )
Microelectronic Circuit Design, 4E
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Full-Wave Rectifiers (10/12)
Full-wave rectifiers cut capacitor discharge
time in half and require half the filter
capacitance to achieve a given ripple voltage.
All specifications are the same as for halfwave rectifiers.
Reversing polarity of the diodes gives a fullwave rectifier with negative output voltage.
Microelectronic Circuit Design, 4E
McGraw-Hill
Chap 3 -78
Full-Wave Bridge Rectification
The requirement for a centertapped transformer in the fullwave rectifier is eliminated
through use of 2 extra diodes. All
other specifications are the same
as for a half-wave rectifier except
PIV = VP.
Microelectronic Circuit Design, 4E
McGraw-Hill
Chap 3 -79
Rectifier Topology Comparison
• Filter capacitors are a major factor in determining cost, size and weight
in design of rectifiers.
• For a given ripple voltage, a full-wave rectifier requires half the filter
capacitance as that in a half-wave rectifier. Reduced peak current can
reduce heat dissipation in diodes. Benefits of full-wave rectification
outweigh increased expenses and circuit complexity (an extra diode and
center-tapped transformer).
• The bridge rectifier eliminates the center-tapped transformer, and the
PIV rating of the diodes is reduced. Cost of extra diodes is negligible.
Microelectronic Circuit Design, 4E
McGraw-Hill
Chap 3 -80
Rectifier Topology Comparison and
Design Tradeoffs
Microelectronic Circuit Design, 4E
McGraw-Hill
Chap 3 -81
Dynamic Switching Behavior of Diodes
The non-linear depletion-layer
capacitance of the diode prevents the
diode voltage from changing
instantaneously and determines turn-on
and recovery times. Both forward and
reverse current overshoot the final
values when the diode switches on and
off as shown. Storage time is given by:






 S   T ln 1
Microelectronic Circuit Design, 4E

McGraw-Hill

I F 
I



R 
Chap 3 -82
Photo Diodes and Photodetectors
If the depletion region of a pn junction diode is illuminated with
light with sufficiently high frequency, photons can provide
enough energy to cause electrons to jump the semiconductor
bandgap to generate electron-hole pairs:
EP  h 
hc

 EG
h =Planck’s constant = 6.626 x 10-34 J-s
 = frequency of opticalillumination
= wavelength of optical illumination
c = velocity of light = 3 x 108 m/s
--------------------------------------------------------------------------Photon-generated current can be used in photodetector circuits
to generate an output voltage vO iPHR
The diode is reverse-biased to enhance depletion-region width
and electric field.

Microelectronic Circuit Design, 4E
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Chap 3 -83
Solar Cells and Light-Emitting Diodes
In solar cell applications, optical illumination
is constant, and dc current IPH is generated.
The goal is to extract power from the cell, and
the i-v characteristics are plotted in terms of
cell current and cell voltage. For a solar cell to
supply power to an external circuit, the ICVC
product must be positive, and the cell should
be operated near the point of maximum output
power Pmax.
Light-Emitting Diodes (LEDs) use
recombination processes in the forward-biased
pn junction diode to produce light. When a
hole and electron recombine, an energy equal
to the bandgap of the semiconductor is
released as a photon.
Microelectronic Circuit Design, 4E
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Chap 3 -84
End of Chapter 3
Microelectronic Circuit Design, 4E
McGraw-Hill
Chap 3 -85