UART via SGPIO on NXP LPC4300
Rev. 1 — 28 March 20135
Document information
Info
Content
Keywords
LPC4300, SGPIO, UART
Abstract
This application note describes how to implement multi-UART (including
single UART) transmission and reception function using SGPIO handled
by the Cortex-M4 or Cortex-M0 core on NXP’s LPC43xx. The UART
protocol implemented in this application note is configurable. The
following configuration are tested: 8 data bits, no parity, 1 stop bit, no
flow control. The baud rates are configurable as well.
Implementing multi-UART via SGPIO on NXP LPC4300
Revision history
Rev
Date
Description
1
20150416
Initial version.
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UART via SGPIO on NXP LPC4300
1. Overview
NXP’s LPC43xx is an ARM Cortex-M4 based microcontroller for embedded applications,
which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash, up to 264 KB of
SRAM, and advanced configurable peripherals such as the Serial General Purpose I/O
(SGPIO) interface. The LPC43xx devices operate at CPU frequencies of up to 204MHz.
The LPC43xx is a dual-core microcontroller in which the ARM Cortex-M4 host CPU is
used as the top-level system controller and the ARM Cortex-M0 CPU is controlled by the
host CPU. The startup process of the dual core is shown in Fig 1.
Fig 1.
Dual core startup process
This application note describes how to implement multi-UART, including single UART,
transmission and reception functions (hereafter called TX and RX) using SGPIO handled
by the Cortex-M4 or Cortex-M0 core on the LPC43xx. The software architecture design is
shown in Fig 2:
Fig 2.
Software architecture design
Remarks:

The emulated UART protocol is configurable. The following configurations are
tested: 8 data bits, no parity, 1 stop bit, no flow control. There are several
configurable baud rates supported in this implementation.

Service routines include SGPIO ISR, common sending and receiving functions.

Board configurations include clock and pin setup.

There are two examples (echo demo and self-loop demo) included to
demonstrate the emulated UART communication.
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UART via SGPIO on NXP LPC4300
2. SGPIO Peripheral Introduction
SGPIO is a new peripheral available on the LPC43XX devices from NXP.
SGPIO offers standard GPIO functionality enhanced with features to accelerate serial
and parallel data stream processing. The enhanced features are realized with slices.
There are 16 SGPIO slices and 16 SGPIO I/O pins. A slice is a section of hardware that
handles the data processing when sending or receiving serial data.
A slice consists of a 32-bit FIFO that is used to clock data in or out, a data shadow
register, and a clock divider to generate a clock for the slice. Slices also have several
interrupt capabilities. See the user manual UM10503 for details on the interrupt
functionality of a slice. The basic operation of one slice is shown in Fig 3.
Fig 3.
Basic operation of one slice
3. Environment
The following sections describe hardware and software environment set up for
development and test.
3.1 Hardware
-
Board: MCB4300 evaluation board with UART
-
Debugger: KEIL ULINK2 for Keil IDE, Segger JLINK for IAR IDE, LPC-LINK2 for
LPCXpresso IDE
-
Connections:
 For echo demo, the hardware setup are as following:
 The TX/RX pins (P2_0/P2_1) of UART0 on the MCB4300 board are configured as
SGPIO pins.
 Jumpers J16 and J13 should be set to UART0.
 A COM cable needs to connect UART0 on MCB4300 to a COM port on PC.
Fig 4 shows the connection diagram of the target board.
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UART via SGPIO on NXP LPC4300
Fig 4.
Connection diagram
 For self-loop demo, the hardware setup are as following:
On the MCB4300 board, test points for most of MCU pins are provided (see the green
region in Fig 4). The LPC4300 can supports up to 8 channels of UARTs since there are
16 SGPIO pins. See Table 5.
Table 1.
UART channel TX and RX pin allocation
Channel No.
TX Pin
RX Pin
0
PF_3
PF_1
1
PF_9
P0_1
2
PD_0
PD_1
3
P6_7
P6_8
4
P1_12
P1_13
5
PD_6
PD_7
6
P1_18
P1_6
7
P1_20
P1_5
To test self-loop communication of a channel, the corresponding TX and RX pins must
be connected, for example, PF_3 should be connected to PF_1 for UART channel 0.
3.2 Software
- Development IDE:

KEIL uVision4 (V4.6). The latest version (V5.13) is also supported.
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
IAR Embedded Workbench for ARM V7.20.1

LPCXpresso V7.6.2_326
- Tool: COM communication tool on the PC, such as AccessPort, SSCOM and PuTTy.
This tool is used for the echo demo only.
4. System configurations
The system configuration is related to the target board. It includes clock setup and pin
assignment for SGPIO peripheral.
4.1 SGPIO peripheral clock setup
The SGPIO peripheral clock, as input clock to the SGPIO, needs to be set according to
the UART baud rate, SGPIO Counter and system clock. It is configured to generate the
SGPIO shift clock and swap clock for serial data communication.
For setup details, see the function SGPIO_UART_SetCLK() in sgpio_mcb_4357.c.
4.2 SGPIO pins assignment
Based on the MCB4300 board, some SGPIO pins are selected for echo demo or selfloop demo. The SGPIO slice and pin mapping to UART TX and RX is shown in Error!
Reference source not found..
Table 2.
SGPIO slice and pin mapping
In echo demo:
Slice
Pin
Function
C/K
SGPIO_4/SGPIO_5
TX/RX
Slice
Pin
Function
E/A
SGPIO_2/SGPIO_0
TX/RX
J/I
SGPIO_3/SGPIO_1
TX/RX
C/K
SGPIO_4/SGPIO_5
TX/RX
In self-loop demo:
F/L
SGPIO_6/SGPIO_7
TX/RX
B/M
SGPIO_8/SGPIO_9
TX/RX
G/N
SGPIO_10/SGPIO_11
TX/RX
D/H
SGPIO_12/SGPIO_14
TX/RX
O/P
SGPIO_13/SGPIO_15
TX/RX
For more details, refer to function SGPIO_Borad_CfgUART0_Chn() and
SGPIO_Borad_Cfg_Chn() in sgpio_mcb_4357.c.
5. Drivers
This section describes the SGPIO drivers that emulate UART protocol to send and
receive data. The user can skip this section if he doesn’t care how to implement and use
the drivers. This section includes:
 UART protocol initialization.
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 SGPIO shift clock and swap clock configuration for UART communications.
 SGPIO pin initialization and slice configuration for UART TX and RX function.
 Emulate sending and receiving of data frames conforming to UART protocol.
Fig 55 shows the waveform showing a UART protocol.
Fig 5.
UART waveform
The UART protocol initialization is implemented in function SGPIO_UART_InitProtocol()
in sgpio_uart_43xx.c.
5.1 SGPIO clock configuration
After the SGPIO slice input clock is decided, the slice needs to be set to generate shift
and swap clock. The shift clock frequency should be equal to UART baud rate which
samples once for each bit and the swap clock should be designed as the cycle time of a
frame. The main settings are shown in Table 3:
Table 3.
Register
SGPIO clock control setting
Slice for TX Slice for RX
SLICE_MUX_CFG
0<<2 | 0<<6
0<<2 | 0<<6
Function Description
(1) Use clock internally generated by
COUNTER
(2) Shift 1 bit per clock
SGPIO_MUX_CFG
0<<5
0<<5
enable clock
For additional details, See the function SGPIO_UART_InitSGPIO() in the
sgpio_uart_43xx.c file.
5.2 SGPIO initialization
Initialize the SGPIO for UART TX and RX to function. The pin for TX should be
configured as an SGPIO output slice and all of the data bits in the data and shadow
registers should be “1” to set the UART to idle mode. See Table 4.
Table 4.
Register
SGPIO TX initialization
Setting
OUT_MUX_CFG
0 | 0<<4
Function Description
(1) 1-bit mode
(2) state set by GPIO_OEREG
GPIO_OENREG
1<<(Pin No. of SGPIO[15:0])
Enable output for TX
REG/ REG_SS
0xFFFFFFFF
Keep idle state before send valid data
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For RX, besides setting up for input mode, the SGPIO should be initialized to get ready to
match the start bit of UART RX. Table 5 shows the setting of SGPIO.
Table 5.
Register
SGPIO RX initialization
Setting
Function Description
GPIO_OENREG
0<<(Pin No. of SGPIO[15:0])
Enable input for RX
SLICE_MUX_CFG
1<<0
Pattern match mode
1<<4
Bit falling edge match for start bit 0
0xFFFFFFFF
Keep idle state before receive valid data
REG
See the related source code for more details regarding SGPIO initialization.
5.3 Control SGPIO
To start UART for transmission or receiving, enable the SGPIO slices. To stop UART,
disable the SGPIO slices.
5.4 Send data frame
Create the serial data frame to be sent first, according to the UART protocol (1 start bit, 8
data bit, no parity, 1 stop bit). See Fig 6:
Fig 6.
Create TX data frame
The data frame can now be put directly in TX slice’s data register to be shifted out. And
the next data frame can also be loaded in the shadow register to be swapped with the
data register when the previous frame has been shifted out completely.
5.5 Receive data frame
When the data frame with start bit is captured and the start bit is shifted to the bit 0 in the
data register, an interrupt will be generated. In the interrupt handler, the data frame can
be read from the data register. Then the valid data needs to be extracted from the frame.
More details on the implementation are described in the following sections.
5.5.1 Oversampling
To improve the reliability of data reception, each bit is sampled three times in reception.
Then the SGPIO UART driver extracts each valid data bit from the sampled data frame.
The criteria to extract a bit is to compare the three sampled values to each other and
then choose the one that occurs two or more times. For more detail, See the function
SGPIO_UART_Extract_Rxdata() in sgpio_uart_43xx.c.
5.6 Driver APIs
The driver APIs are implemented in sgpio_uart_43xx.c and can be called to realize UART
communication combined with an appropriate SGPIO ISR (interrupt service routine). For
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the interrupt service routine implementation, see ISR SGPIO_IRQHandler() in
sgpio_uart_srv.c.
The driver APIs are listed in Table 6:
Table 6.
API functions
Prototype
Input
Return
Description
SGPIO_UART_InitProtocol
ch_no: UART channel No.
None
Initialize default protocol of
one UART channel
None
Initialize the SGPIO
including SGPIO clock of
one UART channel
None
Enable/Disable data
transmission/reception
(TX/RX) for one UART
channel
data: valid data to be sent
a UART data
frame
Create a frame to be sent
over one UART channel
ch_no: UART channel No.
None
Start a data frame for
transmission over one
UART channel
None
Transmit a frame for
swapping to be sent over
one UART channel
UART_cfg: the UART protocol
information used for initialization
SGPIO_UART_InitSGPIO
ch_no: UART channel No.
clk_pre: preset value for SGPIO
shift clock
SGPIO_UART_Control
ch_no: UART channel No.
dir: communication direction.
0: TX 1: RX
NewState: Enable/Disable UART
= ENABLE: Enable UART
= DISABLE: Disable UART
SGPIO_UART_Create_Txframe ch_no: UART channel No.
SGPIO_UART_Start_Txdata
dframe: a data frame to be sent
SGPIO_UART_Put_Txdata
ch_no: UART channel No.
dframe: a data frame to be sent
SGPIO_UART_Get_Rxframe
ch_no: UART channel No.
received data
frame excluding
start bit
Receive a data frame
received from one UART
channel
SGPIO_UART_Extract_Rxdata
size: valid data size in an UART
frame
payload data in a
frame
Extract payload data from
an UART frame without start
bit
dframe: data frame without start bit
Remark:

SGPIO_UART_Start_Txdata(): It loads a frame into data register (called REG in
Fig 3) to be shifted out right after TX is enabled. It can be used for sending the
first one in a series of frames.

SGPIO_UART_Put_Txdata(): It loads a frame into the shadow data register
(called REG_SS in Fig 3) to be swapped to REG after the previous one in REG
is shifted out. It can be used for sending the remained frames after calling
SGPIO_UART_Start_Txdata().
For detailed usage see function SGPIO_UART_Send() in sgpio_uart_srv.c.
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6. Demonstration
6.1 Common routines
The common service routines include common functions and SGPIO ISR to send and
receive via the SGPIO emulated UART. As shown in Fig 2, these routines are midware,
which are based on the low level drivers and used for the examples. The routines are
implemented based on cycle queue. Users can utilize them without changing or
modifying them or develop their own routines according to the particular application’s
requirements.
The routines are listed in Table 7.
Table 7. Common routines introduction
Prototype
Description
SGPIO_UART_InitVal
Initialize global variables for UART TX and RX
SGPIO_UART_Send
Send a serial of data without blocking via UART
SGPIO_UART_Block_Send
Send a serial of data with blocking via UART
SGPIO_UART_Recv
Receive a serial of data without blocking via UART
SGPIO_UART_Block_Recv
Receive a serial of data with blocking via UART
SGPIO_IRQHandler
SGPIO IRQ handler for UART TX and RX
For more details, see the file sgpio_uart_srv.c.
6.2 Examples
There are two examples (echo demo and self-loop demo) that are designed to
demonstrate the UART communication emulated using SGPIO.

The echo demo demonstrates communication between COM port on PC and
UART emulated using SGPIO on target board.

The self-loop demo demonstrates self-loop communication between UART TX
and RX pins which are emulated using SGPIO. It is convenient to evaluate the
performance of the simulated UART.
For ease of evaluation and providing good application reference, there are multiple
project targets created within the KEIL, IAR and LPCXpresso IDE. Table 8 shows the
details
Table 8.
Example project targets
Project Target Name
Description
echo_IRAM_M4
echo demo in internal SRAM on M4 core
selfloop_IRAM_M4
self-loop demo in internal SRAM on M4 core
echo_IFlash_M4
echo demo in internal Flash on M4 core
selfloop_IFlash_M4
self-loop demo in internal Flash on M4 core
echo_IFlash_M0
echo demo in internal Flash on M0 core
selfloop_IFlash_M0
self-loop demo in internal Flash on M0 core
IFlash_DC_M4
boot loader in internal Flash on M4 core which subsequently
releases M0 core
How to run “echo_IFlash_M0” or “selfloop_IFlash_M0” project:
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1. Build the M0 project and download the M0 image
2. Build the “IFlash_DC_M4” project and download the image. This step may only be
operated once for different M0 project running.
3. Reset or re-power on. The image on M4 will run to release M0 core and boot the M0
image.
Notes:
If reports error, such as “Could not stop Cortex-M device!” in Keil IDE, when downloading
M0 image, please try to change the debug port to SW for the M0 project. See below:
For KEIL IDE
For IAR IDE
However, remember that the debug port should be reconfigured to JTAG and M0
IDCODE should be reselected for KEIL IDE when debugging.
7. Test and Performance
7.1 Test and result
Use the following steps to demonstrate and test the examples:
1. Setup the test environment as mentioned above. Note: User needs to configure UART
protocol (Defaults: 8 data bit, 1 stop bit, no parity and 9600 baud rate) in COM
communication tool on PC for testing echo demo.
2. Open the project:
- For KEIL IDE
\application\lpc18xx_43xx\keil_project\SGPIO_Uart.uvproj.
- For IAR IDE
\application\lpc18xx_43xx\iar_project\SGPIO_Uart.eww
- For LPCXpresso IDE
Import the project archive (.zip) after setting a worksapce.
3. Select a project target to build.
4. Debug or download the demo to test after built.
When the demo is running, the debug screen on PC will print the contents shown as:
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Fig 7.
UART output on PC
Type a character or string on the COM communication tool, for example “1234abcd”, and
the string will be echoed by the UART and printed on the screen:
Fig 8.
UART echo on PC
The UART baud rate is configurable. It can be changed in sgpio_single_uart_echo.c:
Fig 9.
Baud rate setting
The Self-loop demo that demonstrates self-loop communication is repeated automatically
at configurable baud rate via multi-UART channels. There are two modes to test the
function of the systems. In both modes, the test result is a success if sent characters are
equal to received ones, otherwise the result is a failure.
(1) Variable mode: A variable initialized to zero is added when the test result is a
success, or the other variable is added if it is a failure. The variables can be
observed in watch window in debugging mode. Fig 10 shows that all of 183 tests,
in the example have succeeded and 0 failed:
Fig 10. Variable watch
(2) LED mode: The sample project will turn on one LED on the target board when
the self-loop test on one UART succeeds. The LED will not be turned on when
the test fails. For example, the LED named PD_10 on MCB4300 board will be
turned on if self-loop test via channel 0 succeeds. UART channel mapping to
LEDs on MCB4300 board is shown in Table 9:
Table 9.
UART channel mapping to LED on MCB4300
Channel No.
LED Name
0
PD_10
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Channel No.
LED Name
1
PD_11
2
PD_12
3
PD_13
4
PD_14
5
P9_0
6
P9_1
7
P9_2
Table 10 shows the settings to easily test the self-loop demo.
Table 10. Self-loop demo settings
Macro Definition
Description
Defined in
UART_BAUDRATE
communication baud rate
sgpio_uart_selfloop.c
TX_BYTE_NUM
communication size in byte
sgpio_uart_selfloop.c
RESULT_DEBUG
1: variable mode
sgpio_uart_selfloop.c
0: LED mode
MAX_CH_NUM
maximum channels supported
sgpio_uart_43xx.h
7.2 Performance
Table 11 lists some of the passed test cases in self-loop demo to show the performance
(With test conditions changed, the performance may vary):

Test conditions:
- Project target: selfloop_IRAM_M4
- Definition RESULT_DEBUG set to 1
- Running at 180Mhz CPU frequency on M4 in internal SRAM
- Communication byte size: 60bytes
- Self-loop test times: 300
- Full duplex operation

Test cases and results:
Table 11.
Test cases and results
Baud Rate
No. of UART Channels that can
function concurrently
9600bps
up to 8
19200bps
up to 6
38400bps
up to 4
57600bps
up to 3
115200bps
up to 2
up to 604800bps
1
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8. Conclusion
This application note describes how to implement multi-UART (including single UART)
using the SGPIO peripheral on LPC4300. The UART transmission and reception by both
the M4 and M0 cores are introduced.
Initializing the SGPIO peripheral correctly is very critical for this multi-UART
implementation.
Two examples with multiple project targets are provided in the sample code to allow easy
evaluation of the project. It also provides reference for users to implement one or more
UART channels using SGPIO on LPC4300.
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9. References
[1]
NXP LPC43xx User Manual UM10503, NXP Semiconductors
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Notice: All referenced brands, product names, service names and
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Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP
AN11351
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11. Contents
1.
2.
3.
3.1
3.2
4.
4.1
4.2
5.
5.1
5.2
5.3
5.4
5.5
5.5.1
5.6
6.
6.1
6.2
7.
7.1
7.2
8.
9.
10.
10.1
10.2
10.3
11.
Overview .............................................................. 3
SGPIO Peripheral Introduction........................... 4
Environment ........................................................ 4
Hardware............................................................ 4
Software ............................................................. 5
System configurations ........................................ 6
SGPIO peripheral clock setup ............................ 6
SGPIO pins assignment ..................................... 6
Drivers .................................................................. 6
SGPIO clock configuration ................................. 7
SGPIO initialization ............................................ 7
Control SGPIO ................................................... 8
Send data frame................................................. 8
Receive data frame ............................................ 8
Oversampling ..................................................... 8
Driver APIs ......................................................... 8
Demonstration ..................................................... 9
Common routines ............................................... 9
Examples ......................................................... 10
Test and Performance ....................................... 11
Test and result ................................................. 11
Performance..................................................... 13
Conclusion ......................................................... 14
References ......................................................... 15
Legal information .............................................. 16
Definitions ........................................................ 16
Disclaimers....................................................... 16
Trademarks ...................................................... 16
Contents ............................................................. 17