MICROPROCESSOR
MEMORY ORGANIZATION
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3.1 Introduction
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3.2 Main memory
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3.3 Microprocessor on-chip memory
management unit and cache
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A memory unit :hold instructions and data.
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Memory system can be divided into three groups:
1. Microprocessor memory: set of microprocessor
registers, used to hold temporary results
2. Primary or main memory: storage area in which
all programs are executed, include ROM & RAM
3. Secondary memory: devices such as hard disks,
also called virtual memory.
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The microcomputer cannot execute programs stored in
the secondary memory directly, so to execute these
programs the microcomputer must transfer them to its
main memory by the operating system.
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L0:
registers
Smaller, faster, and
more expensive (per
byte) storage
devices
L1: on-chip L1
cache (SRAM)
L2:
L3:
Larger, slower, and
cheaper (per byte)
storage devices L4:
L5:
off-chip L2
cache (SRAM)
main memory
(DRAM)
local secondary storage (virtual memory)
(local disks)
remote secondary storage
(tapes, distributed file systems, Web servers)
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8-bit microprocessors:
The memory is divided into a number of 8-bit
units called memory words (byte). Therefore,
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for an 8-bit microprocessor, memory word
and memory byte mean the same thing.
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16-bit microprocessors:
 The memory is divided into a word contains 2
bytes (16 bits). A memory word is identified in the
memory by an address.
 For example, the Pentium microprocessor uses
32-bit addresses for accessing memory words.
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
This provides a maximum of 232 = 4,294,964,296 = 4
GB of memory addresses, ranging from 00000000,, to
data input lines
FFFFFFFF,, in hexadecimal.
n
address lines
Read
Write
k
memory
Unit of size 2k
n
data output lines
Intel Pentium microprocessors (1MB):
 The memory is divided into segments
 Segment = 216 =64KB= addressed by16bits
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High bit for address
LOW bit for
segment number
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I MB memory  220 / 216 = 24
No. of segment (24) =size of memory (220) / size of one segment(216)

For example, the computer uses 24 address
pins to address 224= 16 MB of memory
directly with addresses from 000000,, to
FFFFFF,,.
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An important characteristic of a memory is
whether it is volatile or nonvolatile.
The contents of a volatile memory are lost
when the power is turned off.
RAM is a volatile memory.
A nonvolatile memory retains its contents
after power is switched off.
ROM is a typical example of nonvolatile
memory.
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
ROMs are divided to:
◦ mask ROM, Erasable PROM(EPROM),
and EAROM (electrically alterable
ROM)[also called EEPROM or E2PROM
(electrically erasable PROM)]
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Mask ROMs are programmed by a masking operation
performed on a chip during the manufacturing
process. The contents of mask ROMs are permanent
and cannot be changed by the user.
When designing a microcomputer for a particular
application, permanent programs are stored in ROMs.
Also, Control memories used to microprogram the
control unit are ROMs.
EPROMs can be programmed, and their contents can
also be altered by using special equipment, UV device/
EPROM programmer.
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EPROMs must be removed from the microcomputer
system for programming. This memory is erased by
exposing the chip to ultraviolet light
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EAROMs can be programmed without removing
the memory from the ROM’s sockets.
These memories are also called read-mostly
memories (RMMs), because they have much
slower write times than read times.
Flash memory (nonvolatile), is designed using a
combination
of
EPROM
and
E2PROM
technologies.
Flash memory can be reprogrammed electrically
while embedded on the board. An example of
Flash memory is used in cellular phones and
digital cameras.
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There are two types of RAM: Static RAM (SRAM),
and Dynamic RAM (DRAM).
SRAM
DRAM
stores data in flip-flops (on/off stores data in capacitors.
switches).
memory does not need to be
refreshed.
it can hold data for a few
milliseconds, need to be
refreshed
have lower densities
have higher densities
DRAMs are inexpensive, occupy less space, and dissipate less
power than SRAMs.
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
Two enhanced versions of DRAM are:
 ED0 DRAM (Extended Data Output DRAM)
 SDRAM (Synchronous DRAM).
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The ED0 DRAM provides fast access by allowing the
DRAM controller to output the next address at the
same time the current data is being read.
An SDRAM contains multiple DRAMs (typically, four)
internally. SDRAMs utilize the multiplexed addressing
of conventional DRAMs.
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We consider the instruction fetch, memory
READ, and memory WRITE timing diagrams
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1. The microprocessor performs the instruction
fetch cycle to READ the opcode.
2. The microprocessor interprets the opcode as
a memory READ operation.
3. When the clock signal goes HIGH, the
microprocessor places the contents of MAR on
the address A0-A19.
4. At the same time, the microprocessor raises
the READ signal to HIGH.
5. The logic external to the microprocessor gets
the contents of the location in the main
ROM/RAM addressed by the MAR and places it
on the Data bus.
6. Finally, the microprocessor gets this data
from the Data bus via D0 – D15, and stores it
in an internal register.
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Write timing
1. When the CLK signal goes HIGH, the
microprocessor places the contents of the MAR on
the address A0-A19 of the µp chip.
2. At the same time, the microprocessor raises the
WRITE pin signal to HIGH.
3. The microprocessor places data to be stored from
the contents of an internal register onto Data bus
Do-D15.
4. The logic external to the microprocessor stores the
data from the register into a RAM location
addressed by the MAR.
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