STM32VL- Training
Esprit 2012
V1.0
1
CONTENTS
 PART I : CORTEX-M3
 PART II : STM32F100 device
 PART III : STM32 Value line Discovery Kit
2
PART - I
CORTEX M3
3
CONTENTS

Objectives

Introduction

Cortex-M3 Processor

Cortex M3 interrupt handling

Cortex-M3 Memory Map

Power Management

System Timer (SysTick)

Debug Capabilities
4
OBJECTIVES
 Familiarize with Cortex M3
 At the end of the part you will be able to List the
main features of the Cortex M3
5
CONTENTS

Objectives

Introduction

Cortex-M3 Processor

Cortex M3 interrupt handling

Cortex-M3 Memory Map

Power Management

System Timer (SysTick)

Debug Capabilities
6
What is ARM(Advanced Risc Machines)?
 ARM is an UK company that designs
innovative 32-bit microprocessors
 ARM leads the world of RISC
microprocessor cores
 ARM develops directly and through
partnership the tools, systems and
services to support its architecture.
7
Why use an ARM-based processor?
 Most popular 32-bit core
 Becoming an industrial standard like the C51
 Compatible leading edge core roadmap
 ARM7 -> ARM9 /10->CortexM3, M4,…
 Large number of product choices
 Multiple vendors means a large choice
8
Sales in billions of dollars
Why use an ARM-based processor?
9
Why Cortex M3?
RISC Processor
core
Low power
modes
Tools and RTOS
support
10
Why Cortex M3?
More Than 28 company
ST, NXP, Atmel, Samsung…
Cortex-A Series, applications processors for complex OS and user applications.
Cortex-R Series, real-time systems profile.
Cortex-M Series, microcontroller profile optimized for cost-sensitive applications..
The number at the end of the Cortex name refers to the relative performance
level, with 1 the lowest and 8 the highest.
11
ARM Cortex-M code size advantage
explained
12
Industry standard
13
CONTENTS

Objectives

Introduction

Cortex-M3 Processor

Cortex M3 interrupt handling

Cortex-M3 Memory Map

Power Management

System Timer (SysTick)

Debug Capabilities
14
Cortex-M3 Processor(1/2)
 Hierarchical processor integrating core and
advanced system peripherals
 Cortex-M3 Processor





Cortex-M3 core
Configurable interrupt controller
Bus matrix
Advanced debug components(ETM…)
Optional MPU(Not available in STM32F10x)
 Cortex-M3 core




Harvard architecture
3-stage pipeline prediction
Thumb®-2
ALU w. H/W divide and single cycle multiply
15
Cortex-M3 Processor(2/2)
Non Maskable
Interrupt
3-Stage Pipeline, Harvard Architecture,
Thumb-2 ISA (or Thumb)
30K* Gates
1-240 Configurable
Interrupts
with Configurable Priority
Levels
SWD or JTAG
Breakpoints
Data Watchpoints
& Trace
* Preliminary gate counts & power consumption based on initial implementation
Gate Counts are based on TSMC 0.18 at 50MHz
Optional ETM & MPU gate counts not included
Cortex M3 Total
60k* Gates
16
Cortex-M3 Processor Main Features
 ARM v7M Architecture
 Thumb-2 Instruction Set Architecture
 Mix of 16 and 32 bit instructions for very high code density
 Harvard architecture
 Separate I & D buses allow parallel instruction fetching & data storage
 Integrated Nested Vectored Interrupt Controller (NVIC) Vector Table is
addresses.
 Integrated Bus Matrix
 Data memory management
 3 Stage Pipeline
 Integrated System Timer (SysTick) for Real Time OS
17
Data Memory management (1/7)

Cortex-M3 includes two technologies to reduce Data
memory requirements:
1. Unaligned Data Support
2. Atomic Bit Banding

These technologies can dramatically improve data
(SRAM) memory utilization, potentially enabling silicon
designers and users to reduce the amount of SRAM
required and dramatically impacting silicon usage.
18
Data Memory management(2/7)
• Unaligned Data Support:
Other Core does not
support unaligned
data
Data aligned
on word
boundaries
Long (32)
Long (32)
short (16)
short (16)
Char
Char
Char
Char
Unused (wasted) space
ARM Cortex-M3
supports unaligned
data that can improve
SRAM utilization
Long (32)
Long (32)
short (16) short (16)
Char Char Char Char
Free space Can be used
Reduces SRAM Memory Requirements By Over
50%
Less Memory - LowER Cost
devices
19
Data Memory management(3/7)
long (32)
char (8)
32bit machine
which does
not support
unaligned data
long (32)
char (8) char (8) char (8)
Data
aligned
int (16)
long (32)
int (16)c
char (8)
Structure
management
example
long (32)
char (8)
long (32) …
… long
char (8) char (8) char (8)
int (16)
long (32) …
… long
int (16)c
char (8)
int (16)
long …
… long (32)
int (16)
long (32)
Unused (wasted) space
Free space for the rest of the application
Reduces SRAM Memory Requirements By Over
25%
20
Data Memory management(4/7)
• Bit Banding:
 Traditional method
 Speed and code size optimized
Cortex-M3 implementation
Disable external events
32bit
Read byte (RAM, register)
0 1 0 0 1 0 1 1
Mask and modify bit element
X X X X X 1 X X
@Rbase+N b31
b0
example: 20000000h to 200FFFFFh
b31
Write byte (RAM, register)
0 1 0 0 1 1 1 1
REAL
memory
image
VIRTUAL
aliased
bit banding
image
b0
Enable external events
♦ Bit Banding done by bus matrix.
♦ Single instruction Read/Modify/Write (no more masking).
♦ No new instruction set  Use standard data one (AND, OR, XOR…).
Optimized RAM, peripherals and IOs registers accesses Easy multi-task
semaphore management
21
Data Memory management(5/7)
32MB alias region
1MB Peripheral bit-band region
22
Data Memory management(6/7)
• Bit Banding formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number ×
4)
where:
bit_word_addr: is the address of the word in the alias memory region that
maps to the targeted bit.
bit_band_base is the starting address of the alias region (0x22000000 )
byte_offset is the number of the byte in the bit-band region that contains the
targeted bit
bit_number
is the bit position of the targeted bit(0-7)
Example -1:
. How to map bit 2 of the byte located at Peripheral X address 0x20000300 in the
alias region (Peripheral X based address is 0x20000000 ):
23
Data Memory management(7/7)
• Solution:
0x22006008 = 0x22000000 + (0x300*32) + (2*4).
Writing to address 0x22006008 has the same effect as a read-modify-write
operation on bit 2 of the byte at SRAM address 0x20000300.
Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the
byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset).
For more information on Bit-Banding, please refer to the Cortex™-M3
Technical Reference Manual.
24
Instruction Pipeline(1/3)
 PC points to fetch stage:
FETCH
DECODE
Instruction fetched from memory
Instruction decoded
Register(s) read from Register Bank
EXECUTE
Shift and ALU operation or memory access
Write register(s) back to Register Bank
25
Instruction Pipeline(2/3)
 Optimal Pipelining:
Cycle
1
2
3
4
5
6
7
8
9
Operation
ADD
F
SUB
D
E
F
D
E
F
D
E
F
D
E
F
D
E
F
D
ORR
AND
ORR
EOR
F- Fetch
D - Decode
E
E - Execute
 All operations here are registers (single cycle execution)
 In this example it takes 6 cycles to execute 6 instructions
 Clock cycles per Instructions (CPI) = 1
26
Instruction Pipeline(3/3)
 Flushing :
A flush of the pipeline can occur because of
 A Branch
 An exception
 A breakpoint

Branch Pipeline Example:
Cycle
1
Address Operation
0x8000 B 0x8FEC
0x8002
SUB
0x8004
ORR
0x8FEC
AND
0x8FEE
ORR
0x8FF0
EOR
F
D
E
F
D
2
3
4
5
F
D
E
F
D
E
F
D
6
7
8
9
F
F- Fetch
D - Decode
E
E - Execute
27
Register Set(1/2)
 Registers R0-R12 are simple registers
that can be used to hold program
variables.
Register Set
R0
R1
R2
R3
 Registers R13-R15 have special functions
within the Cortex CPU.
 R13: Register R13 is used as the stack pointer
 R14: called the link register. used to store the
return address when a call is made to a
procedure
 R15: is the program counter
 xPSR:The Program Status Register
contains status fields for instruction
execution
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13(SP)
R14(LR)
R15 (PC)
xPSR
28
CONTENTS

Objectives

Introduction

Cortex-M3 Processor

Cortex M3 interrupt handling

Cortex-M3 Memory Map

System Timer (SysTick)

Debug Capabilities
29
Interrupt Handling
 The Cortex-M3 processor integrates an advanced
Nested Vectored Interrupt Controller (NVIC)
 The NVIC supports up to 240 dynamically reprioritizes
interrupts each with up to 256 levels of priority
 Supports advanced features for next generation real-time
applications:
 Tail-chaining of pending interrupts
 Interrupt Pre-emption
 Late Arrival
30
Interrupt Response- Tail Chaining(1/3)
Highest
IRQ1
IRQ2
42 CYCLES
ARM7
Interrupt handling in
assembler code
PUSH
ISR 1
POP
26
PUSH
16
26
ISR 2
POP
ISR 2
POP
16
Tail-chaining
Cortex-M3
Interrupt handling in HW
PUSH
ISR 1
12
6
12
6 CYCLES
ARM7
Cortex-M3
• 26 cycles from IRQ1 to ISR1 entered
•Up to 42 cycles
•42 cycles from ISR1 exit to ISR2 entry
•16 cycles to return from ISR2
• 12 cycles from IRQ1 to ISR1 entered
• 12 cycles
•6 cycles from ISR1 exit to ISR2 entry
•12 cycles to return from ISR2
31
Interrupt Response – Preemption(2/3)
Highest
IRQ1
IRQ2
42 CYCLES
ARM7
ISR 1
POP
PUSH 2
16
Cortex-M3
ISR 1
26
POP
112
ISR 2
ISR 2
6
POP
16
POP
7-18 CYCLES
12
32
Interrupt Response – Late Arriving(3/3)
Less than 12 cycle
IRQ1
Highest
IRQ2
ARM7
PUSH
PUSH
26
Cortex-M3
PUSH
ISR 1
POP
26
16
ISR 2
ISR 1
6
TailChaining
ISR 2
POP
16
POP
12
33
Interrupt Response – Lab
More than12 cycle
Highest
NMI
IRQ1
IRQ2
IRQ3
Less than12 cycle
PUSH
ISR 2
Starts
PUSH
NMI
ISR 1
 Push for ISR1 begins
 Pre-empted by NMI
 New instruction fetch in
parallel minimises time to NMI
POP
ISR 2
ISR 3
POP
Cortex-M3
•Following NMI processor tail-chains into ISR1
•ISR2 Completed
•Pop only occurs on return to “Main”
34
NVIC Registers

Each interrupt input has several registers to control it
 Enable/Disable Bit
 Enable or disable the interrupt
 Can be set, cleared or read
 Pending Bit
 If the pending bit is set, then the interrupt is pending
 A pending interrupt can only be taken (become active) if it is enabled and it
has sufficient priority to run
 Pending bit can be set, cleared or read
 Active Bit
 A bit is set if the interrupt is executing or “active-stacked”
 “Active-stacked” means the interrupt was executing, but was preempted by another higher-priority interrupt
 Active register is normally read only
 Priority field
 priority management for each interrupt
35
Cortex-M3 Exception Types
No.
Exception Type
Priority
Type of
Priority
Descriptions
1
Reset
-3 (Highest)
fixed
Reset
2
NMI
-2
fixed
Non-Maskable Interrupt
3
Hard Fault
-1
fixed
Default fault if other hander not
implemented
4
MemManage Fault
0
settable
MPU violation or access to illegal locations
5
Bus Fault
1
settable
Fault if AHB interface receives error
6
Usage Fault
2
settable
Exceptions due to program errors
Reserved
N.A.
N.A.
11
SVCall
3
settable
System Service call
12
Debug Monitor
4
settable
Break points, watch points, external debug
13
Reserved
N.A.
N.A.
14
PendSV
5
settable
Pendable request for System Device
15
SYSTICK
6
settable
System Tick Timer
16
Interrupt #0
7
settable
External Interrupt #0
7-10
……
256
…………………..
Interrupt#240
………………
247
settable
settable
…………………..
External Interrupt #240
36
CONTENTS

Objectives

Introduction

Cortex-M3 Processor

Cortex M3 interrupt handling

Cortex-M3 Memory Map

Power Management

System Timer (SysTick)

Debug Capabilities
37
Cortex-M3 Memory Map
38
CONTENTS

Objectives

Introduction

Cortex-M3 Processor

Cortex M3 interrupt handling

Cortex-M3 Memory Map

Power Management

System Timer (SysTick)

Debug Capabilities
39
Power Management

8bit Microcontroller like power mode management
 SLEEP NOW
♦ “Wait for Interrupt” instructions to enter low power mode
No more dedicated control register settings sequence
♦ “Wait for Event” instructions to enter low power mode
No need of Interrupt to wake-up from sleep
Rapid resume from sleep
 SLEEP on EXIT
♦ Sleep request done in interrupt routine
♦ Low power mode entered on interrupt return
Very fast wakeup time
 DEEP SLEEP
♦ Long duration sleep
From product side: PLL can be stopped or shuts down the
power to digital parts of the system
Enables low power consumption
 Optimized RUN mode CORE power consumption
40
CONTENTS

Objectives

Introduction

Cortex-M3 Processor

Cortex M3 interrupt handling

Cortex-M3 Memory Map

Power Management

System Timer (SysTick)

Debug Capabilities
41
System Timer (SysTick)
 Flexible system timer
 24-bit self-reloading down counter with end of count interrupt
generation
 2 configurable Clock sources
 Suitable for Real Time OS or other scheduled tasks
In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8
(provided externally by the Reset Clock Control )
42
CONTENTS

Objectives

Introduction


What is ARM ?

Why use an ARM-based processor?
Cortex-M3 Processor

Cortex-M3 Processor Main Features

Data Memory

Instruction Pipeline

Write Buffer

Privilege, Modes, Stacks and Register Set

Cortex M3 interrupt handling

Exception/Interrupt Handling,

NVIC Registers

Cortex-M3 Exception Types

Vector Table

Cortex-M3 Memory Map

Power Management

System Timer (SysTick)

Debug Capabilities
43
Debug Capabilities

JTAG
ETM
 Three solutions are possible :
SWD
More pins available
for the application
Joint Test Action Group easy flashed application debugging
♦ 8 hardware breakpoints
 Serial Wire Debug for targeted low bandwidth data trace

Enhanced Thematic Mapper capability for better real time debugging
 ♦ Instruction trace only
44
Performance
Power
Management
Real time
5 reasons
to choose
Cortex-M3
Optimized
Memory
Powerful
Debugging
45
PART - II
STM32F10x Device
46
CONTENTS
 Objectives
 STM32F10x Device
 Block Diagram
 Memory mapping and boot modes
 System Architecture
 STM32F10x System Peripherals
 Main features
 STM32F10x Minimum External Components
 STM32F10x standard peripheral Library
 What is CMSIS?
 Package organization
 STM32F10xxx standard peripheral library architecture
 Coding conventions
 Using the Library
47
OBJECTIVES
 Familiarize with STM32F10x device
 At the end of the training you will be able to
 List the main features of the STM32F10x system
peripherals
 Configure the standard library environment
 Develop your applications using the STM32F10x
standard library
48
CONTENTS
 Objectives
 STM32F10x Device
 Block Diagram
 Memory mapping and boot modes
 System Architecture
 STM32F10x System Peripherals
 Main features
 STM32F10x Minimum External Components
 STM32F10x standard peripheral Library
 What is CMSIS?
 Package organization
 STM32F10xxx standard peripheral library architecture
 Coding conventions
 Using the Library
49
More choice with STM32 series
 The general purpose F-1 series
addresses a wide range of applications,
from the lowest price-sensitive design to
the computing intensive, high memory
Footprint
 Get the highest performance with the
F-2 series for computing intensive
application and advanced connectivity.
The F-2 series maintains the compatibility
with the F-1 series.
 Get the highest performance with the
Design ultra-low-power applications with
the L-1 series for those who are power
conscious and seek the absolute lowest
energy consumption. The L-1 series
maintains the compatibility with the F-1
series.
50
STM32 portfolio based on F1 series
51
STM32 Value line 16K-32KBytes block diagram



ARM® Cortex™-M3 1.25
DMIPS/MHz up to 24 MHz
2.0 V to 3.6 V range
-40 to +105 °C
CORTEXTM-M3
CPU
24 MHz
JTAG/SW Debug
Nested vect IT Ctrl

Rich connectivity




1 x Systick Timer
5 communications peripherals
Advanced analog
12-bit1.2 µs conversion time ADC
Dual channel 12-bit DAC
Flash I/F
Core and operating conditions
DMA
ARM Lite Hi-Speed Bus
Matrix / Arbiter (max 24MHz)

16kB - 32kB
Flash Memory
4kB SRAM
Power Supply
Reg 1.8V
POR/PDR/PVD
XTAL oscillators
32KHz + 4~25MHz
20B Backup Data
Int. RC
oscillators
40KHz + 8MHz
PLL
Clock Control
7 Channels
Bridge
RTC / AWU
ARM® Peripheral Bus 1
(max 24MHz)
Enhanced control


16-bit motor control timer
5x 16-bit PWM timers
Synchronized AC Timer
Up to 16 Ext. ITs
37/51 I/Os

LQFP48, LQFP/BGA64
1 x SPI
1 x USART/LIN
Smartcard/IrDa
Modem Control
5 x 16-bit timer
(max 24MHz)

ARM® Peripheral Bus 2
Bridge
1 x 16-bit PWM
1 x CEC
2 x Watchdog
(independent & window)
2-channel 12-bit DAC
1 x USART/LIN
Smartcard / IrDa
Modem Control
1 x 12-bit ADC
up to 16 channels
Temperature Sensor
1 x I 2C
52



ARM® Cortex™-M3 1.25
DMIPS/MHz up to 24 MHz
2.0 V to 3.6 V range
-40 to +105 °C
24 MHz
JTAG/SW Debug
Nested vect IT Ctrl
Rich connectivity

8 communications peripherals
DMA
7 Channels



12-bit1.2 µs conversion time ADC
Dual channel 12-bit DAC
Synchronized AC Timer
Enhanced control


16-bit motor control timer
6x 16-bit PWM timers
Up to 16 Ext. ITs
37/51/80 I/Os
1 x SPI

8kB SRAM
LQFP48, LQFP/BGA64, LQFP100
1 x USART/LIN
Smartcard/IrDa
Modem Control
Power Supply
Reg 1.8V
POR/PDR/PVD
XTAL oscillators
32KHz + 4~25MHz
20B Backup Data
Int. RC
oscillators
40KHz + 8MHz
PLL
Clock Control
Bridge
1 x 16-bit PWM

64kB - 128kB
Flash Memory
Advanced analog
RTC / AWU
ARM® Peripheral Bus1
(max 24MHz)
Bridge
6 x 16-bit Timer
(max 24MHz)

1 x Systick Timer
ARM® Lite Hi-Speed Bus
Matrix / Arbiter (max 24MHz)
Core and operating conditions
CORTEXTM-M3
CPU
ARM® Peripheral Bus2

Flash I/F
STM32 Value line 64K-128KBytes block diagram
1 x CEC
2 x Watchdog
(independent & window)
2-channel 12-bit DAC
2 x USART/LIN
Smartcard / IrDa
Modem Control
1 x 12-bit ADC
up to16 channels
1 x SPI
Temperature Sensor
2 x I 2C
53
STM32 Value line 256K-512KBytes block diagram


ARM® Cortex™-M3 1.25
DMIPS/MHz up to 24 MHz
2.0 V to 3.6 V range
-40 to +105 °C
JTAG/SW Debug
Nested vect IT Ctrl
Rich connectivity


1 x Systick Timer
11 communications peripherals
DMA
up to 12 Channels
SRAM, NOR, memories support.
LCD Parallel interface 8/16-bit
Intel 8080 and Motorola 68K
Reg 1.8V
POR/PDR/PVD
XTAL oscillators
32KHz + 4~25MHz
84B Backup Data
Int. RC oscillators
40KHz + 8MHz
FSMC
SRAM/ NOR/ LCD parallel
interface
Bridge
PLL
RTC / AWU
Enhanced control


16-bit motor control timer
10x 16-bit PWM timers
(max 24MHz)
Bridge
Up to 16 Ext. ITs
51/80/112 I/Os
1 x SPI
LQFP64, LQFP100, LQFP144
ARM® Peripheral Bus 1
1 x 16-bit PWM
Synchronized AC Timer

24KB-32kB SRAM
Power Supply
FSMC




256KB-512kB
Flash Memory
Clock Control
1 x USART/LIN
Smartcard/IrDa
Modem Control
10 x 16-bit Timer
(max 24MHz)

Flash I/F

ARM ® Lite Hi-Speed 36us
Matrix / Arbiter (max 24MHz)
Core and operating conditions
ARM® Peripheral Bus 2

CORTEXTM-M3
CPU
24 MHz
1 x CEC
2 x Watchdog
(independent & window)
4 x USART/LIN
2-channel 12-bit DAC
Smartcard / IrDa
Modem Control
1 x 12-bit ADC
up to 16 channels
2 x SPI
Temperature Sensor
2 x I 2C
54
Memory Mapping and Boot Modes



Addressable memory space of 4 GBytes
RAM : up to 32 kBytes
FLASH : up to 512 kBytes

Boot modes:
Depending on the Boot configuration
- Embedded Flash Memory
- System Memory
- Embedded SRAM Memory
is aliased at @0x00
0xFFFF FFFF
0xE010 0000
0xE00F FFFF
0xE000 0000
Reserved
Cortex-M3
internal
peripherals
Reserved
Reserved
Option Bytes
BOOT Mode
Selection Pins
0x1FFF F80F
0x1FFF F800
Reserved
0x2000 0000
SRAM
Reserved
0x0000 0000
User Flash
User Flash is selected as
boot space
BOOT1
BOOT0
0x1FFF F000
x
0
0
1
SystemMemory
SystemMemory is
selected as boot space
1
1
Embedded
SRAM
Embedded SRAM is
selected as boot space
Reserved
0x0801 FFFF
Peripherals
Aliasing
0x1FFF F7FF
SystemMemory
0x4000 0000
Boot Mode
Flash
0x0800 0000

SystemMemory: contains the Bootloader
used to re-program the FLASH through USART1.
CODE
55
System Architecture

Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA
 BusMatrix added to Harvard architecture allows parallel access
Efficient DMA and Rapid data flow
 Direct path to SRAM through arbiter, guarantees alternating access
 Harvard architecture + BusMatrix allows Flash execution in parallel with DMA transfer
I-bus
D-bus
BusMatrix
CORTEX-M3
Master 1
Flash I/F

GP-DMA
Master 2
FLASH
SRAM
Slave
APB2
AHB
AHB-APB2
AHB-APB1
Arbiter
Peripheral Bus APB2
APB1
Peripheral Bus APB1
Bridges
Buses are not overloaded with data movement tasks
56
CONTENTS
 Objectives
 STM32F10x Device
 Block Diagram
 Memory mapping and boot modes
 System Architecture
 STM32F10x System Peripherals
 Main features
 STM32F10x Minimum External Components
 STM32F10x standard peripheral Library
 What is CMSIS?
 Package organization
 STM32F10xxx standard peripheral library architecture
 Coding conventions
 Using the Library
57
STM32F101x Series Block Diagram
Nested vect IT Ctrl
1 x Systick Timer
DMA
up to 12 Channels
ARM ® Lite Hi-Speed 36us
Matrix / Arbiter (max 24MHz)
JTAG/SW Debug
Flash I/F
CORTEXTM-M3
CPU
24 MHz
256KB-512kB
Flash Memory
24KB-32kB SRAM
Power Supply
Reg 1.8V
POR/PDR/PVD
XTAL oscillators
32KHz + 4~25MHz
84B Backup Data
Int. RC oscillators
40KHz + 8MHz
FSMC
SRAM/ NOR/ LCD parallel
interface
Clock Control
Bridge
PLL
RTC / AWU
ARM® Peripheral Bus
(max 24MHz)
Bridge
1 x 16-bit PWM
51/80/112 I/Os
1 x SPI
1 x USART/LIN
Smartcard/IrDa
Modem Control
10 x 16-bit Timer
(max 24MHz)
Up to 16 Ext. ITs
ARM® Peripheral Bus
Synchronized AC Timer
1 x CEC
2 x Watchdog
(independent & window)
4 x USART/LIN
2-channel 12-bit DAC
Smartcard / IrDa
Modem Control
1 x 12-bit ADC
up to 16 channels
2 x SPI
Temperature Sensor
2 x I 2C
58
Power Control (PWR) and Backup Domain
(BKP)
59
Power Supply
• Power Supply Schemes
 VDD = 2.0 to 3.6 V: External
Power Supply for I/Os and the
internal regulator.
 VDDA = 2.0 to 3.6 V: External
Analog Power supplies for ADC,
Reset blocks, RCs and PLL.
 ADC working only if VDDA ≥ 2.4
V
VDDA domain
VREFVREF+
A/D converter
Temp. sensor
Reset block
PLL
VDDA
VSSA
VDD domain
V18 domain
I/O Rings
VSS
VDD
 VBAT = 1.8 to 3.6 V: For Backup
domain when VDD is not present.
STANDBY circuitry
(Wake-up logic,
IWDG, RCC CSR reg)
Core
Memories
Digital
peripherals
Voltage Regulator
Low Voltage Detector
Backup domain
VBAT
LSE crystal 32K osc
BKP registers
RCC BDCR register
RTC
60
Power On Reset / Power Down Reset
• Integrated POR(Power On
Reset )/ PDR(Power Down
Reset ): circuitry guarantees
proper product reset when
voltage is not in the product
guaranteed voltage range (2V
to 3.6V)
 No need for external reset circuit
• POR and PDR have a typical
hysteresis of 40mV
VDD
Vtrh
POR
40mv hysteresis
Vtrl
PDR
Tempo
2ms
Reset
Vtrl min 1.8V / Vtrh max 2V
61
Programmable Voltage Detector (PVD)
• Programmable Voltage
Detector(PVD)
VDD
 Enabled by software
 Monitor the VDD power supply
by comparing it to a threshold
 Threshold configurable from
2.2V to 2.9V by step of 100mV
PVD Threshold
100mv
hysteresis
PVD
Output
Threshold
62
Backup Domain
• Backup Domain contains
 RTC (Counter, Prescaler and Alarm mechanism)
 Separate 32KHz Osc (LSE) for RTC
 20-byte user backup data
 RCC BDSR register: RTC source clock selection
and enable + LSE config
 Reset only by Backup domain RESET
• VBAT independent voltage supply
 Automatic switch-over to VBAT when VDD goes lower
than PDR level
Backup domain
VBAT
power switch
RCC BDSR
reg
32KHz OSC
(LSE)
20 byte
data
RTC
VDD
ANTI_
TAMP
 No current sunk on VBAT when VDD present
• Tamper detection: resets all user backup
registers
 Configurable level: low/high
 Configurable interrupt generation
63
Low Power Modes
 STM32F10x Low Power modes: uses CortexM3 Sleep
modes
 SLEEP, STOP and STANDBY modes
 The reset circuitry, POR/PDR, is active in STANDBY and STOP modes
Feature
STM32F10x typ
Consumption in RUN mode w/ execute from Flash on internal RC and
peripherals clock ON
4.9mA
Consumption in RUN mode w/ execute from Flash on PLL 24 MHz
(HSE : external clock = 8MHz) and peripherals clock ON
36mA
Consumption in RUN mode w/ execute from Flash on PLL 24 MHz
(HSE : external clock = 8MHz) and peripherals clock OFF
27mA
STOP w/ Voltage Regulator in low power
Low speed and high-speed internal RC oscillators and high-speed oscillator
OFF(no independent watchdog)
14µA
STANDBY w/ low-speed oscillator and RTC OFF
Low-speed internal RC oscillator and independent watchdog OFF
2µA
RTC on VBAT
(*) : Typical
(*)
1.4 µA
values are measured at TA = 25 °C, VDD/VBAT = 3.3 V.
64
CONTENTS
 Objectives
 STM32F10x Device
 Block Diagram
 Memory mapping and boot modes
 System Architecture
 STM32F10x System Peripherals
 Main features
 STM32F10x Minimum External Components
 STM32F10x standard peripheral Library
 What is CMSIS?
 Package organization
 STM32F10xxx standard peripheral library architecture
 Coding conventions
 Using the Library
65
STM32F10x Minimum External Components

Built-in Power Supply Supervisor reduces need for external
components
 Filtered reset input, integrated POR/PDR circuitry, programmable Voltage
Detector (PVD).

Embedded 8 MHz High-Speed Internal (HSI) RC oscillator can be
used as main clock

Optional main crystal drives entire system
 Inexpensive 4-16 MHz crystal drives CPU, all peripherals

Optional 32.768 kHz crystal needed additionally for RTC, can run on
40KHz Low Speed Internal (LSI) RC oscillator
 Only 7 mandatory external passive components for base
system on LQFP100 package!
Application Note is available from www.st.com/mcu
AN2586: STM32F10xxx Hardware development : getting started
66
CONTENTS
 Objectives
 STM32F10x Device
 Block Diagram
 Memory mapping and boot modes
 System Architecture
 STM32F10x System Peripherals
 Main features
 STM32F10x Minimum External Components
 STM32F10x standard peripheral Library
 What is CMSIS?
 Package organization
 STM32F10xxx standard peripheral library architecture
 Coding conventions
 Using the Library
67
What is CMSIS?
• Definition:
The Cortex-M3™ Microcontroller Software Interface Standard (CMSIS) is defined in
close cooperation with various silicon and software vendors and provides a common
approach to interface to peripherals, real-time operating systems and middleware
components. For more details, please refer to www.onarm.com.
• CMSIS layer structure
68
Package organization
69
STM32 Firmware Library User Manual
Main page
70
STM32 Firmware Library User Manual
71
STM32F10xxx standard peripheral library
architecture
- STM32 interrupt IRQ list/ Specific
options for the Cortex-M3 core
- STM32 peripheral memory mapping
and physical register address definition
- Configuration options
…
User application
Cortex-M3 exceptions
Peripheral header file
Include NVIC and
SysTick drivers
Low-level & API functions to
Perform basic operations
offered by the peripheral
72
Coding conventions
 All firmware is coded in ANSI-C
 Strict ANSI-C for all library peripheral files
 Relaxed ANSI-C for projects & Examples files.
 PPP is used to reference any peripheral acronym, e.g.
TIM for Timer.
 Registers & Structures
 FW library registers have the same names as in STM32F10x
Datasheet & reference manual.
 All registers hardware accesses are performed through a C
structures :
 Improve code re-use : e.g. the same structure to handle and
initialize 3 USARTs.
73
Using the Library (1/4)
1) Before configuring a peripheral, you have to enable its clock by calling one of the
following functions:
 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_PPPx , ENABLE);
 RCC_APB2PeriphClockCmd(RCC_APB2Periph_PPPx , ENABLE);
 RCC_APB1PeriphClockCmd(RCC_APB1Periph_PPPx , ENABLE);
2) PPP_DeInit(..) function can be used to set all PPP’s peripheral registers to their
reset values:
 PPP_DeInit(PPPx);
3) If after peripheral configuration, the user wants to modify one or more peripheral
settings he should proceed as following:
 PPP_InitStucture.memberX = valX;
 PPP_InitStructure.memberY = valY;
 PPP_Init(PPPx, &PPP_InitStructure);
74
Using the Library (2/4)
 At this stage the PPP peripheral is initialized and can be enabled by
making a call to PPP_Cmd(..) function: PPP_Cmd(PPPx, ENABLE);
 Note: This function is used only for communication peripherals like UART,
SPI, …
 To access the functionality of the PPP peripheral, the user can use a set
of dedicated functions. These functions are specific to the peripheral and
for more details refer to STM32F10x Firmware Library User Manual.
Example of GPIO
Functions available
75
Using the Library (3/4)
 UART1 configuration example :


/* Enable USART1 Clock */
RCC_APB2PeriphClockCmd( USART1, ENABLE );

/* set all UART1’s peripheral registers to their reset values */

USART_DeInit( USART1 ) ;


/* USART1 configuration ------------------------------------------------------*/
/* USART1 configured as follow:


- BaudRate = 19200 baud
- Word Length = 8 Bits


- One Stop Bit
- Even parity


- Hardware flow control disabled (RTS and CTS signals)
- Receive and transmit enabled

*/

USART_InitStructure.USART_BaudRate = 9600;

USART_InitStructure.USART_WordLength = USART_WordLength_8b;

USART_InitStructure.USART_StopBits = USART_StopBits_1;

USART_InitStructure.USART_Parity = USART_Parity_Even;

USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;

USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;


/* Configure USART1 */
USART_Init( USART1, &USART_InitStructure);


/* Enable USART1 */

USART_Cmd( USART1, ENABLE );
USART 1 is ready now …
76
Using the Library (4/4)
• Files to be modified by the user:

stm32f10x_conf.h
/* Includes -----------------------------------------------------------------*/
/* Uncomment the line below to enable peripheral header file
inclusion */
/* #include "stm32f10x_adc.h" */
/* #include "stm32f10x_bkp.h" */
/* #include "stm32f10x_can.h" */
…
…

stm32f10x.h
/* Uncomment the line below according to the target STM32
device used in your application */
#if !defined (STM32F10X_LD) && !defined
(STM32F10X_MD) && !defined (STM32F10X_HD)
/* #define STM32F10X_LD */ /*!< STM32 Low density
devices */…
#endif
…
/* STM32F10x Interrupt Number Definition*/
EXTI0_IRQn
= 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn
= 7, /*!< EXTI Line1 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */

main.c
#include "stm32f10x.h“
int main(void)
{
...
GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET);
…
}

stm32f10x_It.h
/* Exported functions ----------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
…

stm32f10x_It.c
#include "stm32f10x_it.h"
…
void EXTI1_IRQHandler(void)
{
GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET);
}
77
PART - III
STM32 Value line Discovery Kit
78
STM32 Value line Discovery Kit
Microcontroller Division of MMS Group
June, 2010
79
The cheapest and quickest way to
discover the STM32
 Everything included for a quick start with the STM32 Value Line
 Price: $9.90 (RRP)
 Order code: STM32VLDISCOVERY
 Available NOW from ST and Distributors
 In circuit ST-LINK debugger / programmer included to debug
Discovery kit applications or other target board applications.
 Ideal for quick evaluation, learning or prototyping
 Dedicated web site www.st.com/stm32-discovery
 Examples ready to run
 Schematics
 Forums and more…
80
STM32 Value line Discovery Board

A compact “all in one board”

The debugger “ST-link” is on
the board itself

Few leds and button for
immediate usage
ST-LINK
SWD connector
84mm


The extension connector will all
STM32 pins enable building
more complex applications by
using an extension board
STM32F100RBT6B
User button
Led Blue
Led Green
The board can be used as an
independent ST-link for your
own board if needed
42mm
Extension connector
On each side
81
Tools and Software
 Development Toolchain support
 Free Atollic TrueSTUDIO® lite version with
unlimited code-size and usage-time.
 IAR EWARM
 KEIL MDK-ARM
 Software examples available at www.st.com/stm32-discovery for
a quick start to evaluate and develop with the STM32 Value line
82
Features and Benefits
Feature
Benefit
STM32F100RBT6B microcontroller
Discover STM32 with STM32 Value line,
including 128-Kbyte Flash, 8-Kbyte RAM in a 64pin LQFP
Self powered by USB cable between PC and
STM32 Value line Discovery
Immediate plug-and-play demonstration
Can supply target application with 5 V and 3 V
Adapts the demo to the future application
environment
On-board ST-Link with USB interface for
programming and debugging
Non-intrusive debug with the in-circuit debugger
present on STM32 Value line Discovery.
Selection mode switch to use the kit as a
standalone ST-Link (with SWD connector)
The kit can be used as an ST-link for your own
board
Extension header for all QFP64 I/Os
Ideal for prototyping and easy probing. Enable
quick connection to a prototyping board
Development toolchains from partners
Complete kit enabling full software development,
no need for additional software.
Large number of free, downloadable ready-touse software examples
Fast startup, accelerate your developments.
More than 37 Videos are available on YouTube web site.
example: link : http://www.youtube.com/watch?v=5Si0tgqrAd0
83
STM32F100xx Value Line necessary docs

RM0041 (Reference Manual): Peripherals description…

PM0063 (Flash Programming Manual): Flash description…

Product Datasheet STM32F100x468B-B: Electrical parameters…

STM32F10x Standard Peripheral Library V3.3.0: STM32 value Line Firmware
library, examples…

AN3268 (STM32VLDISCOVERY firmware package): STM32 discovery
Firmware library…

UM0919 (STM32VLDISCOVERY STM32 value line Discovery): STM32
discovery board description, schematics…

UM0985 (Developing your STM32VLDISCOVERY application using the IAR
Embedded Workbench software): Tools description...
All docs are available from www.st.com/mcu
84
Now you are able to…
Develop your application around
STM32F100 device
85
Thank you
86