MAKING A “MODEL”
BOB PEDDENPOHL
MODELING MANAGER
CYPRESS MODELING CENTER
LEXINGTON, KY
OUTLINE
WHAT DOES CY KENTUCKY DO?
WHAT IS A BSIM SPICE MODEL?
HOW TO MAKE A MOS SPICE MODEL?
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DESIGN KIT MAKES MONEY
DESIGN KIT (CAD, R&D)
PRODUCT ($)
PRE-SILICON WORK
SILICON
QUAL
MODELS
CIRCUIT
DESIGN
SCHEMATICS
LAYOUTS
DRC
LVS
E-TEST MODULES
TEST CHIP TAPEOUT
PRODUCT PLANS
MEAS.
VTH
IDS
METAL THICK
ILD THICK
SPICE
RCX
MARKET
NEEDS
PRODUCT
SPECS
CIRCUIT
SCHEMATIC
LAYOUT
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DESIGN KIT MAKES MONEY
DESIGN KIT (CAD, R&D)
PRODUCT ($)
PRE-SILICON WORK
SILICON
QUAL
MODELS
CIRCUIT
DESIGN
SCHEMATICS
LAYOUTS
DRC
LVS
E-TEST MODULES
TEST CHIP TAPEOUT
PRODUCT PLANS
MEAS.
VTH
IDS
METAL THICK
ILD THICK
SPICE
RCX
MARKET
NEEDS
PRODUCT
SPECS
CIRCUIT
SCHEMATIC
LAYOUT
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OUTLINE
WHAT DOES CY KENTUCKY DO?
WHAT IS A BSIM SPICE MODEL?
HOW TO MAKE A MOS SPICE MODEL?
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INTRODUCTION: MODELS
GENERIC DEFINITION
MAN MADE EXPRESSIONS TO REPRESENT MOTHER NATURE
VLSI DESIGN DEFINITION
MODELS = DESIGNERS PERCEPTION OF TECHNOLOGY
ENGINEERING DEFINITION
MODELS = PHYSICAL EQUATIONS + PARAMETERS
Ids = BETA (Vgs-VT)^2
where VT = 0.6 BETA = w/l*COX*MOBILITY = 1E-6
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INTRODUCTION:TYPES OF MODELS
SIMULATION MODELS
NUMERICAL
NUMERICAL
SOLUTION OF
DEVICE
CHARACTERISTIC
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TABLE LOOKUP
ANALYTICAL (OR COMPACT)
SIMULATORS
ACCESS MEASURED
DC/AC DATA IN A
TABULAR FORM
ANALYTICAL OR COMPACT DEVICE
MODELS BASED PRIMARILY ON
DEVICE PHYSICS. FITTING
PARAMETERS INTRODUCED TO
IMPROVE ACCURACY
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SCHEMATICS USE BSIM COMPACT MODELS
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INTRODUCTION: MODELS LIMITATIONS
IDEAL VS REALITY
IDEAL
DESIGN SIMULATIONS EXACTLY EQUAL SILICON MEASUREMENTS
REALITY
MODEL NOT PERFECT
MODEL HAS ACCURACY LIMITATIONS
GOOD DESIGNER UNDERSTANDS MODEL LIMITATIONS
NEED TO MODEL PROCESS VARIATIONS
NEED MODELS QUICKLY TO ENABLE DESIGNERS
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OUTLINE
WHAT DOES CY KENTUCKY DO?
WHAT IS A BSIM SPICE MODEL?
HOW TO MAKE A MOS SPICE MODEL?
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WHAT MODELS USED AT UK?
WHAT CY TECHNOLOGY DID YOU USE?
RAM7: Wmin/Lmin = 0.42/0.20um, Vcc=1.8V, Idrive = 9.99 mA
WHEN WAS TECHNOLOGY QUALIFIED?
MODEL FROZEN Q302
WHAT TYPE OF MOSFETS?
LV MOS (NSHORT/PSHORT), LVT PMOS (PLOWVT)
CELL FETS (NPASS, NPD, PPU)
WHAT’S NSHORT ELECTRICAL TOX? JUNCTION DEPTH?
TOX= 41 A, XJ = 0.1um
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MODEL DEVELOPMENT PROCESS
SELECT “GOLDEN” WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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SELECT “GOLDEN” WAFER
IDEAL: MODELING SILICON CLOSE TO NOMINAL
REALITY: ~400+ PARAMETERS, ONLY MOST IMPORTANT ON TARGET
MIN
NOMINAL
WAFER
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MAX
MODEL DEVELOPMENT PROCESS
SELECT “GOLDEN” WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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MEASUREMENTS: HARDWARE & SOFTWARE
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MEASUREMENTS: COMPLETE MOS
FET DC (VTH0, RDSW)
FET AC (CGDO,DLC)
DIODE DC (JS,JSW)
DIODE AC (CJ, CJSW)
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MEASUREMENTS: FET DC
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MEASUREMENTS: FET DC
MODEL NEEDS SCALE WITHIN ALL GEOMETRY, TEMP
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MEASUREMENTS: DC FET QA, VTH VS. L
MODEL ACCURACY <=> MEASUREMENT ACCURACY
CONDENSED DATA TRENDS
Threshold Voltage vs Length
0.6
0.5
VTH
Strong Halo , L dependence
Vth
Normal SCE
0.4
Halo with SCE
0.3
0.1
1
10
Length (L) in microns
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100
MEASUREMENTS: DC FET QA, VTH VS. W
MODEL ACCURACY <=> MEASUREMENT ACCURACY
CONDENSED DATA TRENDS
Threshold Voltage vs Width
0.6
LOCOS (+k3)
VTH
0.5
Vth
0.4
STI (-k3)
0.3
0.1
1
10
100
Width (W) in microns
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MEASUREMENTS: FET AC
BSIMPro
NCGG_GC.CV W/L=16800.00/0.15 T=25C
C  
26.7
23.56
TOX
Cgg (pF)
20.42

C
TOX  X DEP (v)
17.28
14.14
11.0
-2.0
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-1.2
-0.4
0.4
Vgate (V)
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1.2
2.0
MEASUREMENTS: DIODE DC/AC
BSIMPro
N09A_H.IV A/P=5.58E+03/299.0 T=155C
1.0e-2
N09A_R.CV P/A=2.99E-04/5.58E-09 T=25.0C
9.1
REVERSE BIAS DC CHARACTERISTIC
REVERSE BIAS AC CHAR.= f(CJA, CJP, EX,)
I_FORWARD ~mA
1.0e-3
8.08
1.0e-4
1.0e-5
1.0e-7
Cjc (pF)
1.0e-6
7.06
I_Reverse ~ pA
6.04
1.0e-8
1.0e-9
5.02
1.0e-10
1.0e-11
-5.0
Max.Err%= 25.4
22
-3.8
-2.6
-1.4
V (V)
-0.2
1.0
4.0
0.0
Rms Err%=Max.Err%=
4.58
0.22
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0.4
0.8
1.2
Vbias (V)
1.6
2.0
Rms Err%=
MEASUREMENTS: TRANSIENT
RING OSCILLATOR VALIDATION OF MODEL
O/P
IN
RO _ DELAY  2  d  N
WHERE
  RINTERCONNECT  C FET  C INTERCONNECT 
R10
TECH
C9
R10
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C9
DESCRIPTION
DELAY (PS/STAGE)
143 stages WP/WN=4/2 FanOut=1
55.7
143 stages WP/WN=4/2 FanOut=1
31.0
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SPEC
55.0
31.0
MODEL DEVELOPMENT PROCESS
SELECT “GOLDEN” WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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WAFER CASE: DC MOS EXTRACTION
MODEL = EQUATIONS + PARAMETERS
EQUATIONS (BSIM3V3) + MODEL PARAMETERS = WAFER CASE MODEL
Short
Channel
Effects
Mobility Model
Drive
Current
Channel
Length
Modulation
Threshold Model
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Short Channel Effects
(HALO/DIBL)
WAFER CASE: MOS MODEL BINNING
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Long/Wide
Constant Vt
Narrow Width Effects
(STI/LOCOS)
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WAFER CASE: AC FET + DIODE
MODEL EXTRACTION
MODEL = EQUATIONS + PARAMETERS
EQUATIONS (BSIM3V3) + PARAMETERS (EXTRACTED FROM
MEASUREMENTS) = MODEL (WAFER CASE)
BSIMPro
N09A_H.IV A/P=5.58E+03/299.0 T=155C
1.0e-2
MOSFET CV MODEL
Accumulation
1.0e-3
1.0e-4
MOS DIODE IV MODEL
I (A)
1.0e-5
1.0e-6
BSIMPro
1.0e-7
N09A_R.CV
P/A=2.99E-04/5.58E-09 T=25.0C
Inversion
1.0e-8
9.1
1.0e-9
1.0e-10
8.08
1.0e-11
-5.0
Intrinsic Cap for
Analog Design
Cjc (pF)
BSIM3
Limitation
7.06
-3.8
-2.6
-1.4
-0.2
V (V)
Max.Err%= 25.4
Rms Err%= 4.58
6.04
5.02
MOS DIODE CV MODEL
4.0
0.0
Max.Err%= 0.22
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0.4
0.8
1.2
Vbias (V)
1.6
1.0
2.0
Rms Err%= 0.15
MODEL DEVELOPMENT PROCESS
SELECT “GOLDEN” WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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RO CAL: LAYOUT EXTRACTED SIMULATION
VALIDATE CAD EXTRACTION RULES + MOS BSIM MODELS
O/P
IN
RO _ DELAY  2    N
d
WHERE
  RINTERCONNECT  C FET  C INTERCONNECT 
LAYOUT (DESIGN DEP.)
LAYOUT MODEL: (ILD, METAL THICK)
CALIBRE RCX
R10
SPICE MODELS
C9
CIRCUIT: FET DELAY +
Rinterconnect + Cinterconnect
RO SIMS = RO MEAS
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MODEL DEVELOPMENT PROCESS
SELECT “GOLDEN” WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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CORNER MODELS
WAFER CASE SIMULATIONS = WAFER MEASUREMENTS
WHAT ABOUT PROCESS VARIATIONS?
WILL MY DESIGN YIELD?
MIN
NOMINAL
MAX
WAFER
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CORNER MODELS
REALITY
EVERY SITE/WAFER/LOT/SPLIT IS DIFFERENT
( PROCESS VARIATIONS)
MIN
NOMINAL
MAX
tt.cor wafer.cor
WORKING WITH REALITY
CORNERS: MODELING SPACE TO COVER ALL
POSSIBILITIES (STATISTICALLY) IN PROCESS
ss.cor
TEAM EFFORT TO GET GOOD YIELD
FAB: +/-4 SIGMA E-TEST  99.99% WAFERS INSIDE MIN/MAX
MODELING: MIN/MAX MODELS MATCH FAB LIMITS
DESIGN: SIMULATE DESIGN WORKING AT MIN/MAX LIMITS
ALL 3 GROUPS WORKING = GOOD PRODUCT YIELD
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ff.cor
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.8
0.79
0.78
0.77
0.76
0.75
0.74
0.73
0.72
0.71
0.7
0.69
0.68
0.67
0.66
-1.05 -1.03
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fs
ss
11
sf
ff
10
idsns15
vtxns15
WHY 5 MOS CORNERS?
tt
9
sf
-1.01
tt
ff
8
-0.99
-0.97
-0.95
-0.93
-0.91
-0.89
-0.87
-0.85 -0.83
vtxps15
VTXNS15 vs. VTXPS15 (V)
(Vth @ W/L=25/0.15um)
ss
fs
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2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7
idsps15
IDSNS15 vs. IDSPS15 (mA)
Idrive (Vgs=Vds=Vcc)
W/L=25/0.15um
VTs AT SS & FF = 70% SPEC RANGE
VTs AT FS/SF = 100% SPEC RANGE
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WHY CORNER METHODOLOGY IMPORTANT
MODEL MUST MATCH DESIGN/FAB AGREED LIMITS
FAB WANTS WIDE MIN/MAX LIMITS
STATISTICAL PROCESS CONTROL (SPC)
HOW GOOD DOES A PROCESS RUN WITHIN IT’S NOM/MIN/MAX
DESIGN WANTS NARROW MIN/MAX LIMITS
EASIER TO DESIGN
SMALL PROCESS VARIATION  SMALLER SI AREA
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MODEL DEVELOPMENT PROCESS
SELECT “GOLDEN” WAFER
MEASUREMENT (DC, AC, TRAN)
EXTRACT WAFER CASE MODEL
RO MEAS = RO SIMS
CENTER TO EDR NOMINAL (TT)
SKEW MODELS (FF, SS, FS, SF)
QA & RELEASE TO DESIGN
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QA: MODEL DOCUMENTATION
MODEL SUMMARY TABLE
MODEL ACCURACY IN SUB-THRESHOLD, GM ACCURACY
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APPENDIX
BOB PEDDENPOHL (PED)
CYPRESS MODELING CENTER
Applying the Corner Models
Design
FET Corners
CellFET Corners
Interconnects/Passives
tt, ff, ss, sf, fs
ttcell, ffcell, sscell
trtc, hrlc, lrhc
Nmos/Pmos
Npass
Nthick/Pthick (HV)
Nlatch
Diode
Platch
PNP
Interconnect R
Interconnect C
r+c.mod
tres, fres, sres
tpar, fpar, spar
Temp coef of R
metal/contact/poly/diff
Sheet resistances
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C for various line/space