R&D for
Embedded Analogue
Testing
TAMES2-Workshop
Diego Vázquez García de la Vega
Instituto de Microelectrónica de Sevilla (IMSE-CNM)
dgarcia@imse.cnm.es
Outline
TAMES2-Workshop
• A panoramic view
• Analogue and MS Test. Current
Status
• External Testing. Fundamental
Problems
• Solutions
• Conclusions
Diego Vázquez
IMSE-CNM
A Panoramic View
FROM ASICs to SOCs
Application
Specific Logic
Glue Logic
DSP
Digital SoC (90’s)
Processor
Memory
Memory
MS SoC (00’s)
Wired
Communication
Wireless
Communication
Audio & Video
RF circuitry
Power
Management
Passive
Components
ASIC (80’s)
TAMES2-Workshop
Next SOCs
And… increased performance in terms of
speed, bandwidth, accuracy, power, voltage supply, etc…
Diego Vázquez
IMSE-CNM
A Panoramic View
System-On-Board (SOB)
Memory
Tester
Functional
Tester
uP
digital
Memory
Mixed
Signal
Mixed-Signal
Tester
TAMES2-Workshop
RF
Logic
Tester
• Dedicated technologies
RF
• Pre-tested ICs (dedicated tester)
Tester
• Board level test
Diego Vázquez IMSE-CNM
A Panoramic View
System-On-Board (SOB)
System-On-Chip (SOC)
uP
digital
Memory
uP
Mixed
Signal
TAMES2-Workshop
RF
digital
Memory
Mixed
RF
Signal
• Dedicated technologies
• Mixed technologies on the same chip
• Pre-tested blocks
• Pre-designed blocks (not tested)
• Board level test
• Core and IC level Test required
Diego Vázquez
IMSE-CNM
A Panoramic View
System-On-Chip (SOC)
Functional
Tester
uP
digital
Memory
Memory
Tester
Mixed
RF
Signal
RF
Tester
TAMES2-Workshop
Logic
Tester
Std Blocks
IP Blocks
Mixed-Signal
Tester
Different cores with different modeling, different test requirements,
different tester languages, etc.
Diego Vázquez
IMSE-CNM
A Panoramic View
Mixed
RF
Signal
 Core Provider may not know:
Which test method, tolerance
margins, etc. to use.
 System integrator may have:
Very limited knowledge of the
adopted core.
 Test of embedded IP cores:
Joint responsibility of both core
provider and system integrator.
System integrator
TAMES2-Workshop
digital
Memory
Design and
Test Development
Design and
Test Development
Manufacturing
IP-Core-Based approach
uP
Core provider
IP Core-Based System
Test
Diego Vázquez
IMSE-CNM
A Panoramic View
Source: SIA Roadmap
System-On-Chip (SOC)
1,2E+08
1,0E+08
8,0E+07
uP
Memory
6,0E+07
4,0E+07
digital
Mixed
RF
Signal
2,0E+07
0,0E+00
1997 1999 2001 2003 2006 2009 2012
TAMES2-Workshop
# Trans/Sq cm
More to Test !!!!!
Diego Vázquez
IMSE-CNM
A Panoramic View
Source: SIA Roadmap
System-On-Chip (SOC)
1000000
100000
uP
Memory
10000
1000
digital
Mixed
RF
Signal
100
1997 1999 2001 2003 2006 2009 2012
TAMES2-Workshop
#Trans/pin
Less Test Access !!!!!
Diego Vázquez
IMSE-CNM
A Panoramic View
Source: SIA Roadmap
System-On-Chip (SOC)
140
120
100
uP
Memory
80
60
40
digital
Mixed
RF
Signal
20
0
1997
1999
2001
2003
2006
2009
2012
TAMES2-Workshop
fT Device (GHz)
Increased Bandwidth !!!
Diego Vázquez
IMSE-CNM
Analogue and MS Test
Current Status
FUNCTIONAL TEST
Specification-Based Test
I/O Behavior
The Circuit Complies Specs
Stimuli
Generator
CUT
Response
Interpreter
• The CUT is considered as a black box
•All interesting I/O relationship must be
TAMES2-Workshop
checked out
•Tests may overlap and be redundant
• It takes long time
• It requires different instrumentation
•Tests do not guarantee defect-free ICs
Diego Vázquez
IMSE-CNM
Analogue and MS Test
Current Status
TAMES2-Workshop
• Analog Circuit classes:
– Filters
– ADCs
– DACs
– PLLs
– RF Transceivers
– Signal Conditioners
– etc
Combined into an IC requires
different test techniques:
Test stimuli
 Response analysis
• Testing methods is
circuit dependent:
– Filters
• Frequency domain,
Passband, Rejection
band, Distortion, Dynamic
Range, etc.
– Data Converters
• Time domain, Linearity
(INL, DNL), SNR, ENB,
etc.
– PLLs
• Frequency Domain,
Stability, Capture Range,
Jitter, etc.
– Basic Blocks (OTAs,
Opamps, etc)
• DC, AC, Transient, etc.
Diego Vázquez
IMSE-CNM
Analogue and MS Test
Current Status
• Specification-based (functional) tests:
Tractable and does not need an analog fault model.
– Long test development time
– Expensive ATE
– Long test time.
• Test stimuli:
– Multiple types
– Dependence wrt to the involved circuit
TAMES2-Workshop
• Test evaluation:
– Multiple types (DC, AC, Transient, etc.)
– Requires accurate and complex post-processing
• Separate test for functionality and timing impossible.
Diego Vázquez
IMSE-CNM
Analogue and MS Test
Current Status
SUPER TESTER
uP
TAMES2-Workshop
digital
•
•
•
•
•
Memory
Mixed
RF
Signal
Large Pin-Count
Large Data Volume
High Frequency Features
High Accuracy Features
etc
 Stimuli generation
 Precision timing
 Diagnostic
Test control
 Power management
 Large deep memory
 Slow throughput
 etc.
Diego Vázquez
IMSE-CNM
Analogue and MS Test
Alternative Approach
STRUCTURAL TEST
Defect-Oriented Test
There are no defects
CUT
Defect Effects
Stimuli
Generator
Response
Interpreter
• The CUT structure must be known
TAMES2-Workshop
• Minimal test showing up defects
• It takes shorter times
• It requires simple instrumentation
• Tests do not guarantee Specs
Diego Vázquez
IMSE-CNM
Analogue and MS Test
Alternative Approaches
FUNCTIONAL TEST
Specification-Based Test
Stimuli
Generator
• The CUT is considered as a black box
•All interesting I/O relationship must be
TAMES2-Workshop
checked out
•Tests may overlap and be redundant
• It takes long time
CUT
STRUCTURAL TEST
Defect-Oriented Test
There are no defects
Defect Effects
I/O Behavior
The Circuit Complies Specs
Both
approaches
are
complementary
Response
Interpreter
• The CUT structure must be known
• Minimal test showing up defects
• It takes shorter times
• It requires simple instrumentation
• Tests do not guarantee Specs
• It requires different instrumentation
•Tests do not guarantee defect-free ICs
Diego Vázquez
IMSE-CNM
Fundamental problems
with External Testing
More to Test but Less Test Access
More Devices and less Pin/Device
uP
TAMES2-Workshop
digital
Memory
Mixed
RF
Signal
Diego Vázquez
IMSE-CNM
Fundamental problems
with External Testing
More to Test but Less Test Access
Yield Losses
Source: SIA Roadmap
Projected
Yield losses
TAMES2-Workshop
If current trends continue,
in less than ten years,
tester timing errors will
approach the cycle time
of the fastest devices.
Device speed
+30% per year
Tester accuracy
12% per year
Diego Vázquez
IMSE-CNM
Fundamental problems
with External Testing
More to Test but Less
Test Access
Yield Losses
ATE Cost
TAMES2-Workshop
Accuracy, Bandwidth,
noise, pin-count, socket
performance, memory,
etc. accordingly to CUT.
If current trends continue, it may cost more to test a transistor than to
manufacture the transistor (by 2014).
Diego Vázquez
IMSE-CNM
Solutions
Lines of interest
• Standardized Test Access Mechanism
» 1149.4
» P1500*
• Structured Test planning
»
»
»
»
Enable hierarchical testing
Enable the re-use of on-chip resources (DSP, uP, etc.)
Facilitate parallel testing
etc.
TAMES2-Workshop
• Re-usable and structured DfT & BIST techniques
»
»
»
»
Provide accessing to embedded cores,
Reduce I/O data rate requirements,
Enable low pin count testing, and
Reduce the dependence on expensive instruments.
Diego Vázquez
IMSE-CNM
Solutions
Standard Test Access efforts
1149.4 (started at the end of 1991)
– Standard Mixed-Signal test bus to be used at device,
sub-assembly and system levels.
» Aims to increase the observability and controllability of
Mixed-Signal designs and support MS-BIST structures.
TAMES2-Workshop
P1500 (started in 1995)
– Standard test method for embedded cores.
» Focused on Standardized Core Test Language (CTL) and
configurable & scalable test wrapper for easy test access
to the core.
» Need extension to mixed-signal.
Diego Vázquez
IMSE-CNM
Solutions
DfT & BIST
• Re-usable and structured DfT & BIST techniques.
 A DfT Technique is not a Test Technique.
 An optimum strategy requires a synthesis of different
DFT & BIST techniques.
TAMES2-Workshop
Layout Rules & guidelines
Physical
Support for specif. meas.
Electrical
isolation & accessing
Block
Pre/Post processing tech.
System
Partial / full BIST
General
Circuit
Specific
On-line Test
Hierarchy
Techniques
Diego Vázquez
IMSE-CNM
Solutions
DfT & BIST
• Re-usable and structured DfT & BIST
techniques.
 An optimum strategy requires a synthesis of different
DFT & BIST techniques.
Layout Optimization
Layout Rules & guidelines
TAMES2-Workshop
Design for Iddq
Physical
Support for specif. meas.
Electrical
isolation & accessing
Block
On-Chip techniques
ADCBIST, PLLBIST
MADBIST, HBIST
System
Partial / full Self-Test
Circuit Reconfiguration
Concurrent Test
Self-Checking archit.
Hierarchy
Techniques
Sw-opamp
Standard Test Bus (1149.4)
On-Line Archit.
Examples
Diego Vázquez
IMSE-CNM
Solutions
DfT & BIST
• Re-usable and structured DfT & BIST
Accessing
techniques.
Functional
Layout Optimization
Layout Rules & guidelines
TAMES2-Workshop
Design for Iddq
Physical
Support for specif. meas.
Electrical
isolation & accessing
Block
On-Chip techniques
ADCBIST, PLLBIST
MADBIST, HBIST
System
Partial / full Self-Test
Circuit Reconfiguration
Concurrent Test
Self-Checking archit.
Hierarchy
Techniques
Structural
Sw-opamp
Standard Test Bus (1149.4)
On-Line Archit.
Examples
Diego Vázquez
IMSE-CNM
Solutions
BIST
MAIN ADVANTAGES
– Test the untestable:
• Embedded cores
• Measure functions faster
than ATE
– IP protection
– Re-usability:
TAMES2-Workshop
• Along IC life cycles:
wafer, board, field
– Reduce ATE
requirements
– Reduce test
develop.&Applic. time
REQUIREMENTS
– Put ATE functions into
the chip:
• Test stimuli generation
• Output response
analysis
• Test control
– Support for Board and
System levels.
– Extra Area
– Design Efforts
Diego Vázquez
IMSE-CNM
Solutions
BIST
• TECHNIQUES:
TAMES2-Workshop
– Functional:
Meas Specs. Params
– Structural:
Signature analysis to
detect faults and predict
yield problems.
•
•
•
•
•
EXAMPLES
HBIST [Ohletz91]
MADBIST[Toner&Roberts,93]
adcBIST [LogicVision]
PLLBIST [LogicVision]
adcBISTmaxx [Opmaxx]
– OBIST (filters, ADCs,
DACs, SD-mod, etc.)
– Reconfiguration (filters,
SD-mod, Pipeline ADCs,
etc.)
– Etc.
Diego Vázquez
IMSE-CNM
Solutions
Test Stimuli Generators
Available techniques
TAMES2-Workshop
–
–
–
–
Sinusoidal oscillators
Relaxation oscillators
Digital synthesizers
SD–based Bit-streams
generators
– White noise generators
– PWM generators
– Etc.
Constrains
– Precission &
Resolution
– Frequency range
– Multi-tone capability
– Linearity (ramps)
– Calibration
– Programmability
– Area
– Etc.
Diego Vázquez
IMSE-CNM
Solutions
Output Response Analyzers
Available
techniques
GLOBAL RESULTS
TAMES2-Workshop
Histograms
FFT
Bandpass digital filters
SD Signature analyzer
Sinewave correlation
Etc.
-10.0
AD
DSP
(FFT)
-30.0
-50.0
dBV
–
–
–
–
–
–
-70.0
-90.0
-110.0
-130.0
-150.0
0.0
519.5
1039.1 1558.6 2078.1 2597.6 3117.2
Frequency (Hz)
Passband
Signal Power
AD
DIGITAL
FILTER
Reject Band
Noise Power
Diego Vázquez
IMSE-CNM
Conclusions
DfT&BIST vs External ATE
TAMES2-Workshop
Reasons for DfT&BIST
– Portable: reusable along
IC life cycle
– The only solution for
embedded blocks
– Reduce cost of external
ATE
– At-Speed Test
– Solves SOCs problems
(accessing, IP protection)
– Simplifies Test Program
Development
– External accessing to
embedded blocks may
impact performance
Reasons for External ATE
– External ATE can do more
testing
– BIST increase IC
complexity
– BIST may impact
performance
– BIST increase design
efforts & time
– BIST may increase yield
loss.
Diego Vázquez
IMSE-CNM
Conclusions
• Further Research required:
DfT & BIST techniques for analogue embedded cores
 Many companies and researchers are providing since some
years good solutions for a diversity of cores (PLLs, ADCs and
DACs, filters, memories, etc.).
TAMES2-Workshop
 However, the industry has only adopted standards (1149.4) &
functional solutions (adc-BIST, adcBISTmaxx, etc.)
 Structural techniques not widely accepted, but they are a
clear potential solution that need to be further explored.
Diego Vázquez
IMSE-CNM
Conclusions
DfT & BISTed ICs
NEED!!: Dedicate part of the IC area to
include DfT and BIST facilities
Memory
(BISTed)
Logic
(BISTed)
Mixed-Signal
(BISTed)
TAMES2-Workshop
I/O & Interconnects
(BISTed)
Low Bandwidth external
interfaces
On-Chip
Test Manager
External ATE
 Stimuli generation
 Result compression
 Precision timing
 Diagnostic
 Power manager
 Test Control
 Support for board &
system level
Digital Tester
Low cost-per-pin
Limited speed
Limited accuracy
IC
High Bandwidth internal interfaces
Ideal concept:
DfT & BISTed IC
Diego Vázquez
IMSE-CNM