Measurements
on pre-production wafers
at Udine
Presented by M. Cobal
on behalf of the Udine group
Pixel Week December 2001
Measured Wafers
•
CiS
- 4456-21
- 4456-23
- 4457-23
- 4458-21
•
Tesla
- A31-02
- A31-07
- A31-08
- A31-12
Outline
• Tiles and diodes with guard ring
– IV measurements
– CV measurements
– tile conformity
• SC’s and MC’s yield
• Visual inspection
– ID marking correctness
– visual inspection
– mask alignment
IV measurements
• This time, taken with 2-side chuck
• Temperature corrections applied
Diode position
#16
n side
#17
IV meas. on diode #17 (CiS)
IV meas. on diode #17 (Tesla)
Quality Control Parameters
• Tile conformity criteria:
– Vbd(tile)> Vop(diode)
– Slope=I(tile @ Vop)/I(tile @ Vop-50)<2
• Vop=max(Vdep+50,150)
• Need to measure Vdep
Capacitance offset
CV results
CV results
Determination of Vdep and Vop
- Measurements lie within
65 V < Vdep< 100 V
- Procedure specs demanded:
30 V < Vdep < 120 V
- For
all wafers: Vdep <100 V
Vop= max(Vdep+50,150) = 150 V
Determination of Cdep and r
• Cdep is between 1.7-4.2 (4.5-5.6) pF for
CIS (Tesla)
• Determined as:
Cdep=C(Vdep)-Coffset
DCoffset of order of 0.2-0.7 pF (for
positive polarity)
• r lies within 2.1-3.3 kWcm
• conformity range is 2-5 kWcm
Tile results (CiS)
• Results in agreement with CIS
• 2 wafers with 2 good tiles
• 2 wafers with 3 good tiles
wafer 4456-21 with
Slope (Tile 1) = 3.58
SC and MC yield (CiS)
• SC’s: 6 x 4= 24
• MC’s: 4 x 4 = 16
• 5 are bad (Vbd<150)
• 1 is bad (Vbd<150)
• 79% are good
• 94% are good
Tile results (Tesla)
• Disagreement for 1 Wafer out of 4:
Wafer A31-12
Slope(Tile 2):
Our measure
2.08
Tesla
1.85
SC and MC yield (Tesla)
• SC’s: 6 x 4=24
• MC’s: 4 x 4=16
• 1 is bad (Vbd<150)
• 4 are bad (Vbd<150)
• 96% are good
• 75% are good
Scratch pad marking (CIS)
2- and 3-good-tile wafers:
– TILES: all 4 pads marked.
– SC’s: only 1 of the 2 pads marked (lower
one).
– All markings are correct.
Scratch pad marking (Tesla)
2 and 3 good tiles wafers
– TILES: only 2 out of 4 pads marked.
– SC’s: only 1 of the 2 pads marked (lower
one).
– All markings are correct.
Visual Inspection (CiS)
• 4456-21
n-side: Tile 2, small scratch (6 pixels)
#16, extended scratch (superficial)
• 4456-23
n-side: Tile 1, one pixel defective
Tile 2, “
“
Tile 3, three pixels defective
#22, extended scratch (superficial)
MC13, one pixel “larger”
Visual Inspection (Tesla)
• A31-02
p-side: #17, small scratch
#12, small scratch
• A31-08
n-side: #19, extended scratch
p-side: bad end of the three top structures
Scratch
Mask alignment
vernier
Goal: Measure 2 mm misalignment
Use: “Nikon Optiphot 150” @ 200-500 X
Mask alignment (CiS)
•Good contrast
•For vertical vernier, 4 vs 5 bars
Mask alignment (CiS)
• Out of specifications:
Wafer 4457-23: n-side, left pad, 4th hor.
right pad, 4th hor.
p-side, right pad, 4th hor.
Wafer 4456-23: n-side, right pad, 4th hor.
p-side, right pad, 4th hor.
Wafer 4458-21: n-side, left pad, 4th hor.
right pad, 4th hor.
p-side, right pad, 4th hor.
Mask alignment (Tesla)
• Quite bad contrast for all the vernier
• All 3rd vernier are missing
• All the 4th vernier are badly printed
Mask alignment (Tesla)
• Out of specifications:
Wafer A31-02: p-side, right pad, 1st vert.
Wafer A31-07: p-side, right pad, 1st vert.
Wafer A31-12: p-side, left pad, 4th vert.
Database
•The new wafers (both CiS and Tesla) have been
already inserted in the database
• IV measurements will be added very soon
•For CV measurements, needs to understand
better