Workshop Topics - Outline
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Workshop 1 - Introduction
Workshop 2 - module instantiation
Workshop 3 - Lexical conventions
Workshop 4 - Value Logic System
Workshop 5 - Data types A
Workshop 6 - Data types B
Workshop 7 - Operators
Workshop 8 - Signed arithmetic
Workshop 9 - Behavioral modeling A
Workshop 10 - Behavioral modeling B
Workshop 11 - Behavioral modeling C
Workshop 12 - Data flow modeling
Workshop 13 - Coding Styles
1
Structural Hierarchy Description Style
 Module Port/Variable/Data Declarations
 Direct instantiation and connections of modules from a
separate calling module
- From the structural hierarchy of the design
 A module may be declared anywhere in a design
relative to where it is called
 Signals in the higher “calling” module, are connected to
signals in the lower “called” module by either:
- Named association
- Positional association
2
Module Port/Variable/Data Declarations
 Combined Variable Declaration and Initialization -
Variables can be initialized when they are declared:
reg clock = 0 ; // Replaces reg clock ; initial clock = 0 ;
 Combined Port/Data Declaration and Initialization:
output reg [7:0] sum = 0 ; // can be written as sum = 8’b0 ;
output reg co = 0 ;
// can be written as co = 1’b0 ;
 Combined ANSI C Style Port Declaration and Initialization:
module adder(output reg [7:0] sum = 0, output reg co = 0,
input [7:0] a, b, input ci) ;
3
Module interconnections: Ports
Within a Verilog system model, module interconnections
occur at two levels:
 Peer to peer: modules interconnect with each other:
Module A
Module B
 Hierarchical: one module incorporates the other:
Module A
Module B
4
Module Ports
 Ports provide interface for the module to communicate
with its environment.
 Declaration:
<Port direction> <width> <port_name> ;
Port direction can be input, output or inout (bi-directional).
Example:
// Traditional Verilog Syntax
module my_module (in_port, inout_port, output_port) ;
input [4:0] in_port ;
// 5bits input port
inout inout_port ;
// single bit bi-directional port
output wire (or reg) [14:0] out_port ; // 15bits output port
endmodule
// ANSI C Style Port Declarations Syntax
module my_ module(input [4:0] in_port, inout inout_port,
output wire (or reg) [14:0] out_port) ;
endmodule
5
Port Specifications
 An input port specifies an internal name for a vector or
scalar, driven by external entity.
 An output port specifies an internal name for a vector or
scalar, driven by internal entity, available external to the
module.
 An inout bi-directional port specifies an internal name for
a vector or scalar driven either by an internal or external
entity.
 Input or inout port cannot be declared as of type register.
 Port is always considered as net, unless declared
elsewhere as reg (only for output port)
6
Correct Port Connection
net
inout
net
reg or net
net
input
reg or net
output
module
7
net
Module Instantiation - Port connections
 Ports of the instances could be connected by name or by
order list.
 For small # of ports, connect by order list, else, by name.
module fa_tb ;
reg [3:0] A, B ;
reg CIN ;
wire [3:0] SUM ;
wire COUT ;
module FA4 (sum, cout, a, b, cin) ;
output wire [3:0] sum ;
output wire cout ;
input [3:0] a, b ;
input cin ;
// Instantiate/connect by Positional association (order list):
FA4 fa_byorder (SUM, COUT, A, B, CIN) ;
// Instantiate/connect by Named association (port name):
FA4 fa_byname (.cout(COUT), .sum(SUM),.b(B), .cin(CIN), .a(A));
endmodule
8
| endmodule
Test Bench and UUT Instantiation
 Module Test Bench incorporates, hierarchically, the
Unit Under Test (UUT) module
Stimuli
registers
9
Unit Under Test
Monitor
inputs
wires
wires
outputs
wires, regs
D_FF Test Bench
`include “D_FF.v"
// include the UUT Verilog file for simulator parsing
`timescale 1ns / 100ps /* compiler directive.
sets simulation’s time unit and precision */
module D_FF_tb () ;
reg Clk, Nrst, D ;
// Stimuli signals
wire Q ;
// Monitor signal
D_FF UUT(Clk, Nrst, D, Q) ; // instantiation of the D_FF (UUT)
initial
begin
Clk = 1'b0 ; Nrst = 1'b0 ; D = 1'b0 ; // System monitoring function
$monitor($time,"Clk=%b, Nrst=%b, D=%b, Q=%b",Clk, Nrst, D, Q) ;
end
always #1 Clk = ~Clk ; // Clock declaration, toggle clock every half-cycle
initial
begin
#2 Nrst = 1'b1 ;
// Out of reset
#2 D = 1'b1 ;
#2 $finish ;
// System function - end simulation run
end
endmodule
10
D_FF Simulation results
11
4bit Counter
`timescale 1ns / 100ps // result evaluated every 1ns, 100ps resolution
module cntr_4b (clk, nrst, dout) ; // module name and ports list
input clk, nrst ;
output reg [3:0] dout ;
// input ports - clock and active-low reset
// counter output port
always @ (posedge clk or negedge nrst)
// if "or negedge nrst" deleted - synchronous reset
begin
if (!nrst)
// Asynchronous reset
dout = 4'b0 ;
else
// Out of reset - normal operation
dout = dout + 1 ; // if -1, down counter
end
endmodule
12
4bit Counter Test Bench
`include “cntr_4b.v“
// include the UUT Verilog file for simulator parsing
`timescale 1ns / 100ps
module cntr_4b_tb ;
reg Clk, Nrst ;
// System Clock and active-low Reset Stimuli signals
wire [3:0] Dout ;
// Counter Output Monitor
cntr_4b UUT (Clk, Nrst, Dout) ; // instantiation of the 4bits Counter
initial
begin
Clk = 1'b0 ; Nrst = 1'b0 ;
// System monitoring function
$monitor($time, "Clk=%b, Nrst=%b, Dout=%h", Clk, Nrst, Dout) ;
end
always #1 Clk = ~Clk ; // Clock declaration. Clock cycle time = 2nSec
initial
begin
#2 Nrst = 1'b1 ; // Out of reset
#35 $finish ;
// System function - end simulation run
end
endmodule
13
4bit Counter Simulation results
14