SIGGSP: Low-Power Circuit Techniques for iSensors
Monthly Report (February 7, 2013)
1. Team Members
NTU PI:
Tsung-Hsien Lin
Students:
Chun-Yu Lin (PhD), Yi-Chu Chen (MS)
Chang-Hsiang Weng (PhD), Tzu-An Wei (MS)
Intel Champions:
Chang-Tsung Fu and Hasnain Lakdawala
2. Discussion with Intel Champions
a. Face-to-face meeting on Jan. 13, 2013 (Sun.), 10:00 ~ 12:00 AM, Taipei time:
update the progress on the design/simulation of delta-sigma modulator and
measurement result on the wireless transmitter. Have lunch together at Living
One.
3. Progress
a. Employ the class-AB output stage to reduce the power consumption of the loop
filter; Adopt the pseudo cascade technique to enhance the DC gain of the
operational amplifier.
Pseudo cascode
R C CC
VON
VDD
Vbias_p
Vbias_p
CC R C
VCMFB
Vbias_p
VIP
VIN
VIN
VIP
Opamp
VOP
DC gain
62 dB
Ft
1.25 G
Power
615 uW
PM
60
VB
Rbias
Rbias
GND
b. Use dynamic switching technique to reduce the power consumption of the
time-domain comparator
Comparator
Current consumed by comparator
Without dynamic switching
With dynamic switching
Vstop
Power switch
Clk_b
Vop
M1
M3
M5 M13
M2
M4
M6
Vramp
I (mA)
Clk
M14
Clk_b
Time (ns)
1
c. Simulation shows that this design achieves a good FoM in 90-nm CMOS process.
ISSCC 2006
ISSCC 2012
ISSCC 2009
ISSCC 2012
This work
Simulation/Spec.
Process
130-nm CMOS
90-nm CMOS
65-nm CMOS
90-nm CMOS
90-nm CMOS
Supply
1.2 V
1.2 V
1.3 V
1.4 V
1.2 V
Modulator
architecture
CT FF & FB ,
3rd -order, 4
bits
CT FF & FB
3rd-order, 4 bits
CT FB & FF ,
3rd-order, 50
level
CT FB & FF
2nd -order, 6
bits
CT FB & FF
3rd -order, 3 bits
Signal
bandwidth
20 MHz
25 MHz
20 MHz
10 MHz
10 MHz
Sampling
frequency
640 MHz
500 MHz
950 MHz
600 MHz
320 MHz
Power
dissipation
20 mW
8.5 mW
10.5 mW
16 mW
< 4.3 (7 mW)
SNDR
74 dB
67.5 dB (DR)
60 dB
78 dB
> 74 (74 dB)
FOM (pJ/conv)
0.122
0.088
0.319
0.125
< 0.052 (0.085)
d. Complete TX2 measurement. Measurement results successfully demonstrate the
function of calibration. The comparison table of TX1 and TX2 is shown below.
16-QAM Mod.
Tx1 (25Mbps)
16-QAM Mod.
Tx2 (4Mbps)
EVM~ 10%
After PM cal. before AM calibration
EVM~ 10%
Suffer distortion
16-QAM Mod.
Tx2 (4Mbps)
EVM~ 11%
After PM cal. before AM calibration
2
16-QAM Mod.
Tx2 (4 Mbps)
EVM~ 2.5%
After calibration
120 Mbps
EVM: 6 %
Item
TX1
TX2
Tech.
CMOS 90nm
CMOS 90nm
Supply
1.2 V
1V
Freq. Band
2.4 GHz
2.4 GHz
Modulation
HS-OQPSK,
16-QAM
HS-OQPSK
16-QAM
Max. Data Rate
105 Mbps
160 Mbps
Pout
-3 dBm
-3 dBm
16-QAM Mod. Comparison
160 Mbps
EVM: 6.8 %
EVM
@ 25 Mbps
9.3 %
4%
EVM
@ Max. Data Rate
9.3 %
6.8 %
Calibration
N/A
AM and PM
Power Con.
13.77 mW
11.671 mW
FoM (J/bit)
0.551 n
0.073 n
HS-OQPSK Mod. Comparison (802.15.4)
Data Rate
2 Mbps
EVM (Spec < 35 %)
2.9 %
2 Mbps
3.5 %
FIR Spur
-30 dBc
-48 dBc
Power (Modulator)
7.71 mW
7.3 mW
FoM (J/bit)
3.855 n
3.65 n
4. Brief Plan for Next Month
a. Continue on optimizing modulator design; reduce the power consumption of the
pulse width modulator and time-to-digital converter (for CTDSM).
b. Do the modulator floor plan; start to work on circuit layout (for CTDSM).
c. Organize/summarize TX2 measurement results; prepare for paper writing (for
TX2).
d. Design the phase modulator (for TX), and investigate the phase calibration
technique (or mismatch shaping technique).
5. Research Byproducts
N/A
6. References
N/A
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