Notes:
• No Studios This week
• About lab proto-boards and modules
– Must stay in the lab
– You are responsible for your assigned equipment for the entire semester.
– Section 6.1.4-6.1.6 of Katz’s Textbook
– In-class Activity #1
• Section 7.1 of Katz’s Textbook
– In-class Activity #2
1

S
0
0
1
1
R
0
1
0
1
Q hold
0
1 unst able
Truth Table Summary of R-S Latch Behavior
Q Q
0 1
Q Q
0 0
Q Q
1 0
State Behavior of R-S Latch
Q Q
1 1
2

SR = 0 1
SR = 00, 01
Q Q
0 1
SR = 1 1
SR = 00, 10
SR = 1 0
Q Q
1 0
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1
Q Q
0 0
SR = 1 0
SR = 0 0
SR = 0 0, 11
Q Q
1 1
Theoretical R-S Latch State Diagram
3

SR = 00, 01
Q Q
0 1
SR = 1 1
SR = 00, 10
SR = 1 0
Q Q
1 0
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1
Q Q
0 0
SR = 0 0
SR = 0 0
Very difficult to observe R-S Latch in the 1-1 state
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"
4

NEXT STATE TABLE
J K Q Q +
0 0 0 0 HOLD
0 0 1 1
0 1 0 0 RESET
0 1 1 0
1 0 0 1 SET
1 0 1 1
1 1 0 1 TOGGLE
1 1 1 0
Simplify by coupling inputs i.e., one input determines the other
5

NEXT STATE TABLE
J K Q Q +
0 0 0 0 HOLD
0 0 1 1
0 1 0 0 RESET
0 1 1 0
1 0 0 1 SET
1 0 1 1
1 1 0 1 TOGGLE
1 1 1 0
Let J = D, K = D
NEXT STATE TABLE
D Q Q +
0 0 0
0 1 0
1 0 1
1 1 1
RESET
SET
D
Also called D flip-flop if edge-triggered
6

NEXT STATE TABLE
J K Q Q +
0 0 0 0 HOLD
0 0 1 1
0 1 0 0 RESET
0 1 1 0
1 0 0 1 SET
1 0 1 1
1 1 0 1 TOGGLE
1 1 1 0
Let J = T, K = T
NEXT STATE TABLE
T Q Q +
0 0 0
0 1 1
1 0 1
1 1 0
HOLD
TOGGLE
T
Also called T flip-flop if edge-triggered
7

J
K
Q
\ Q
K
J
R
Latch
Q
S Q
Q
Q
Reset
100
Toggle Set
Problem: Keeps on toggling!
8

Two-stage memory element
J
S
Latch
Q
P
S
Latch
Q
Q
K
R Q R Q
P
Q
Clock Clock
Master section - clock high
J-K inputs generate P outputs
Slave section - clock low
Ps are unchanging and generate Qs
Two-phase clock operation Feedback has no effect until next time clock is high
9

J
K
Master Stage Slave Stage
\Q
R
S
R-S
Latc h
\Q
Q
\P
P
R
S
R-S
Latc h
\Q
Q
Q
Clk
Sample inputs while clock high Sample inputs while clock low
Uses time to break feedback path from outputs to inputs!
Set Reset
1's
Catc h T oggle 100
J
K
Clk
P
\ P
Q
\ Q
Master output s
Slav e output s
Correct Toggle
Operation
10

1's Catching problem:
If input = 1 any time during the clock period (even a 0-1-0 glitch), it will be interpreted as a 1 for computing output
 designer must use hazard-free logic
Solution: edge-triggered logic called “Flip-flops”
Built from 3 latches
D
D
0
R
Holds D when cl ock go es l ow
Q
Negative Edge-Triggered
D flipflop
When clock is high:
R=S=0 is the Hold state
Clk=1
S
0
Holds D when cl ock go es l ow
Q
D
D
11

D
Clk=1
Negative Edge-triggered D Flipflops
D
D
D
D
0
R
Holds D when cl ock go es l ow
Q
Clk=0
D
R
Q
Q
D
S
0
Holds D when cl ock go es l ow
Q
D
D
S
D
D
Initially Clk = 1
R = S = 0
(Hold)
When clock goes high-to-low
R = D’, S = D
(new data D is latched)
12

Clk=0
Negative Edge-triggered D Flipflops
0 4
D
D
D
R
3
D
D
R
Q Q
Clk=0
6
Q Q 5
D D
S
D
S
D 2
D
D
When clock goes high-to-low
R = D’, S = D
(new data D is latched)
D'
D' ° D
1 0
If clock remains low, and
D changes,
(Previous value of D is held)
13

Input/Output Behavior of Latches and Flipflops
Type When Inputs are Sampled When Outputs are Valid
Un-clocked always propagation delay from latch input change level clock high propagation delay from
-sensitive (T su
, T h around input change latch falling clock edge) positive edge clock lo-to-hi transition propagation delay from flipflop (T su
, T h around rising edge of clock rising clock edge) negative edge clock hi-to-lo transition propagation delay from flipflop (T su
, T h around falling edge of clock falling clock edge) master/slave clock hi-to-lo transition propagation delay from flipflop (T su
, T h around falling edge of clock falling clock edge)
14

R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended!
however, fundamental building block for other flipflop types
J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ƒ(in,Q,Q+) but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist
D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers
T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters
Preset and Clear inputs highly desirable!!
15

7474
D Q
Clk
Pos itive edge-triggered f lip-f lop
Edge triggered device sample inputs on the event edge
Transparent latches sample inputs as long as the clock is asserted
Timing Diagram:
7476
D Q
C
Clk
Lev el-sens itive latc h
Bubble here for negative edge triggered device
D
Clk
Q
7474
Q
7476
Behavior the same unless input changes while the clock is high
16

TYPO!!: For Part (a) start with circle (0, 1)
D
Clk
D
S
D
D
D’
R
Holds D when clock goes low
Q
D
Holds D when clock goes low
Q
J-K NEXT STATE TABLE
J K Q Q +
0 0 0 0 HOLD
0 0 1 1
0 1 0 0 RESET
0 1 1 0
1 0 0 1 SET
1 0 1 1
1 1 0 1 TOGGLE
1 1 1 0
17

• Flipflops: most primitive "packaged" sequential circuits
• More complex sequential building blocks:
– Storage registers, Shift registers, Counters
– Available as components in the TTL Catalog
– Registers
» Store a word (4 to 64 bits)
» E.g.: Pentium has several registers
– Counters
» Count thru a sequence of states
» E.g., the seconds display on a clock.
– Both of these have many variations.
18

• Storage registers store data, without changing it.
– A D F/F is a 1-bit storage register.
• A Register File stores a group of words of data.
– You specify which word to read or write.
• A Random-Access Memory is like a large register file. It may store 32MB of data or more.
19

use D F/Fs in groups to make a multibit register
Clocks in 4 bits in parallel, or resets to 0.
20

Triangle indicates clock input
No bubble indicates positive edge triggered
The /CLR clears all 4 bits
171
12
13
CLK
CLR
11
5
4
14
D3
D2
D1
D0
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
10
6
3
15
9
7
2
1
This stores 4 bits in parallel
21

• Sometimes there’s also a LOAD input.
– When LOAD is false, the F/F doesn’t change.
– When LOAD is true during the clock edge, the
F/F updates itself.
• Sometimes the outputs are 3-state or open collector .
– This allows several registers to be connected to the same output wire
22

Positive edge triggered
... but only when
/EN is active LO
11
1
18
17
14
13
8
7
4
3
D7
D6
D5
D4
D3
D2
D1
D0
CLK
EN 377
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
19
16
15
5
2
12
9
6
Stores an 8 bit number
23

Positive edge triggered
Stores an 8 bit number
/OE is active LO output enable
Determines when register contents are visible at the outputs
CLK
18
17
14
13
8
7
4
3
H
G
F
E
D
C
B
A
374
19
QH
QG
16
15
QF
12
QE
QD
9
6
QC
QB
OE
QA
5
2
Note: LW uses different labels from the 377, and from Katz!
24

Store several words
• You read or write one word at a time.
• 74670 4-by-4 Register File with 3-State Outputs
4 words of 4 bits each
Data in: D1,D2,D3,D4 Data out: Q1,Q2,Q3,Q4
Read selects: RB,RA Write selects: WB,WA
Active low read enable /GR, write enable /GW
Can read and write simultaneously .
No clock.
Read or write when enables asserted.
Watch out for glitches!
11
4
5
GR
RB
RA
12
13
14
GW
WB
WA
3
2
1
15
D4
D3
D2
D1
670
Q4
Q3
Q2
Q1
6
7
9
10
To write Word 1, set GW = 0 and (WB, WA) to (0,1)
To read Word 2, set GR = 0 and (RB, RA) to (1,0)
25

• Same idea as a register file, but optimized for very many words.
• Small RAM: 256 4-bit words.
• Larger RAM: 4 million 8-bit words.
• More details later.
26

• Some registers are designed to change their stored data.
• Shift registers shift their bits left or right.
For example, right shift:
Original contents
Shift right:
1000
0100
Shift again:
…and again:
0010
0001
… once more, wrapping: 1000
• Application: send a word to a modem bit-by-bit.
• We need some way to initialize the shift register.
27

• Serial input
The shift register doesn’t wrap around from right to left.
Instead, the user provides the new leftmost bit.
• Parallel input
You can specify the whole word at once.
• Serial output
The bit just shifted off the right is visible at a pin.
• Parallel output
Every stored bit is visible at an output pin.
This uses more pins, which can be a problem.
28

4 bit bidirectional universal shift register
4 modes set by S1,S0
00: hold data (QA,QB,QC,QD)
01: shift right (SR,QA,QB,QC)
10: shift left (QB,QC,QD,SL)
11: parallel load
SL (aka LSI): left shift input
SR (aka RSI): right shift input
Positive edge triggered
10
9
S1
S0
7
SL
4
3
6
5
D
C
B
A
2
SR
11
CLK
1
CLR
194
QD
QC
QB
QA
12
13
14
15
/CLR: asynchronous clear
29

• Notation conflicts:
– LogicWorks uses SL, SR. Katz uses LSI, RSI.
– LW uses A,B,C,D for inputs and QA,QB,QC,QD for outputs.
– Motorola uses P0,P1,P2,P3 for inputs, Q0,Q1,Q2,Q3 for outputs and D
SR
& D
SL for serial inputs.
• Note that the normal LW convention is that A is the lo-order bit. This is the way you normally connect the hex keyboard and the hex display. For the 194, A and QA are the hi-order bits . It's confusing.
• Right shift in more detail. All together on the rising clock:
SR

QA, QA

QB, QB

QC, QC

QD, QD is lost .
Connecting QD to SR makes a circular shift register.
• Left shift in more detail.
SL

QD, QD

QC, QC

QB, QB

QA, QA is lost .
30

TYPO: Question b, part 2, WB, WA = 11
Due: End of Class Today
RETAIN THE LAST PAGES (#3 & #4)!!
• Bring Randy Katz Textbook, & TTL Data Book
• Required Reading:
– Sec 7.2, 7.3 of Katz
• This reading is necessary for getting points in the Studio Activity!
31