Flip Flops, Registers
Today:
• First Hour: Types of Latches, Flip Flips
– Section 6.1.4-6.1.6 of Katz’s Textbook
– In-class Activity #1
• Second Hour: Storage and Shift Registers
• Section 7.1 of Katz’s Textbook
– In-class Activity #2
1
State Diagrams for Latches
S R
Q
0 0
hold
0 1
0
1 0
1
1 1 unst able
Truth Table Summary
of R-S Latch Behavior
QQ
01
QQ
10
QQ
00
State Behavior of R-S Latch
QQ
11
2
State Diagram: R-S Latch
SR = 00, 10
SR = 00, 01
SR = 1 0
QQ
01
QQ
10
SR = 0 1
SR = 0 1
SR = 1 0
SR = 11
SR = 1 1
SR = 1 1
QQ
00
SR = 0 1
SR = 1 0
SR = 0 0
SR = 0 0, 11
QQ
11
Theoretical R-S Latch State Diagram
3
Observed R-S Behavior
SR = 00, 10
SR = 00, 01
SR = 1 0
QQ
01
QQ
10
SR = 0 1
SR = 0 1
SR = 1 0
SR = 11
SR = 1 1
SR = 1 1
QQ
00
SR = 0 0
SR = 0 0
Very difficult to observe R-S Latch in the 1-1 state
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"
4
Making Other Latches
NEXT STATE TABLE
J
0
0
0
0
1
1
1
1
K
0
0
1
1
0
0
1
1
Q
0
1
0
1
0
1
0
1
Q+
0
HOLD
1
0 RESET
0
1
SET
1
1 TOGGLE
0
Simplify by coupling
inputs
i.e., one input
determines the other
5
D Latch
NEXT STATE TABLE
J
0
0
0
0
1
1
1
1
K
0
0
1
1
0
0
1
1
Q
0
1
0
1
0
1
0
1
Q+
0
HOLD
1
0 RESET
0
1
SET
1
1 TOGGLE
0
Let J = D, K = D
NEXT STATE TABLE
D
0
0
1
1
Q+
0
0
1
1
Q
0
1
0
1
RESET
SET
D
Also called D flip-flop if edge-triggered
6
T Latch
NEXT STATE TABLE
J
0
0
0
0
1
1
1
1
K
0
0
1
1
0
0
1
1
Q
0
1
0
1
0
1
0
1
Q+
0
HOLD
1
0 RESET
0
1
SET
1
1 TOGGLE
0
Let J = T, K = T
NEXT STATE TABLE
T
0
0
1
1
Q
0
1
0
1
Q+
0
1
1
0
HOLD
TOGGLE
T
Also called T flip-flop if edge-triggered
7
Comparison of FFs
R-S Clocked Latch:
used as storage element in narrow width clocked systems
its use is not recommended!
however, fundamental building block of other flipflop types
J-K Flipflop:
versatile building block
can be used to implement D and T FFs
usually requires least amount of logic to implement ƒ(In,Q,Q+)
but has two inputs with increased wiring complexity
because of 1's catching, never use master/slave J-K FFs
edge-triggered varieties exist
D Flipflop:
minimizes wires, much preferred in VLSI technologies
simplest design technique
best choice for storage registers
T Flipflops:
don't really exist, constructed from J-K FFs
usually best choice for implementing counters
Preset and Clear inputs highly desirable!!
8
Timing issues revisited
Latch
K
R
J
S
Set
Reset
Q
Q
Q
Q
100
Toggle
J
K
Q
\Q
Problem: Keeps toggling!
9
J-K Master/Slave F-F
Two-stage memory element
Latch
J
K
S
Q
R
Q
Latch
P
P
S
Q
R
Q
Q
Q
Clock
Clock
Master section - clock high
Slave section - clock low
J-K inputs generate P outputs
Ps are unchanging and generate Qs
Two-phase clock operation - Feedback has no effect until next time clock is high
10
Timing: master-slave
Master Stage
K
\Q
R
Slave Stage
\P
R
S
\Q
R-S
Latc h
R-S
Latc h
J
\Q
Q
S
P
Q
Q
Clk
Sample inputs while clock low
Sample inputs while clock high
Uses time to break feedback path from outputs to inputs!
Set
Reset
1's
Catc h
Toggle
100
J
K
Clk
P
\P
Q
\Q
Master
outputs
Correct Toggle
Operation
Slav e
outputs
11
Edge-triggered FFs
1's Catching problem:
- a 0-1-0 glitch on the J or K inputs leads to a state change!
- I.e. If input 1 any time during the clock period, it will be
interpreted as a 1 for computing output
=> forces designer to use hazard-free logic
Solution: edge-triggered logic called “Flip-flops”
D
Negative Edge-Triggered
D flipflop
D
Hold s D when
clock g oes low
0
R
Q
Clk=1
Schematic when clock is high:
R=S=0 I.e. Hold state
Q
S
0
Hold s D when
clock g oes low
D
D
12
Step-by-Step Analysis
Edge-triggered Flipflops
D
0
D
4
3
D
R
D
D
R
Q
Clk=0
Q
5
Q
Clk=0
Q
D
D
S
D
S
2
D
D
6
D'
1
D
0
D' ° D
Negative edge-triggered D FF
when clock goes high-to-low
new data (D) is latched
Negative edge-triggered D FF
when clock remains low
data is held
13
Latches vs Flip-Flops
Input/Output Behavior of Latches and Flipflops
Type
unclocked
latch
When Inputs are Sampled
always
When Outputs are Valid
propagation delay from
input change
level
sensitive
latch
clock high
(Tsu, Th around
falling clock edge)
propagation delay from
input change
positive edge
flipflop
clock lo-to-hi transition
(Tsu, Th around
rising clock edge)
propagation delay from
rising edge of clock
negative edge
flipflop
clock hi-to-lo transition
(Tsu, Th around
falling clock edge)
propagation delay from
falling edge of clock
master/slave
flipflop
clock hi-to-lo transition
(Tsu, Th around
falling clock edge)
propagation delay from
falling edge of clock
14
TTL schematics
7474
D
Q
Clk
Pos itive edge-triggered
flip-flop
Edge triggered device sample inputs on the event
edge
Transparent latches sample inputs as long as the
clock is asserted
Timing Diagram:
7476
D
Q
D
C
Clk
Lev el-sens itive
latc h
Bubble here
for negative
edge triggered
device
Clk
Q
7474
Q 7476
Behavior the same unless input changes
while the clock is high
15
Do Activity #1 Now
Edge-triggered D-flipflop
J-K NEXT STATE TABLE
D
D
Holds D when
clock goes low
D’
R
Q
Clk
Q
S
D
Holds D when
clock goes low
D
D
J
0
0
0
0
1
1
1
1
K
0
0
1
1
0
0
1
1
Q
0
1
0
1
0
1
0
1
Q+
0
HOLD
1
0 RESET
0
1
SET
1
1 TOGGLE
0
16
Sequential Logic Components
• Flipflops: most primitive "packaged" sequential circuits
• More complex sequential building blocks:
– Storage registers, Shift registers, Counters
– Available as components in the TTL Catalog
– Registers
» Store a word (4 to 64 bits)
» E.g.: Pentium has several registers
– Counters
» Count thru a sequence of states
» E.g., the seconds display on a clock.
– Both of these have many variations.
17
Storage Registers
• Storage registers store data, without changing it.
– A D F/F is a 1-bit storage register.
• A Register File stores a group of words of data.
– You specify which word to read or write.
• A Random-Access Memory is like a large register
file. It may store 32MB of data or more.
18
Multibit Storage Registers
use D F/Fs in groups to make a multibit register
Clocks in 4 bits in parallel, or resets to 0.
19
74171 Quadruple D F/F with Clear
Triangle indicates clock input
171
No bubble indicates
positive edge
triggered
The /CLR
clears all 4 bits
12
13
CLK
CLR
11
D3
5 D2
4 D1
14
D0
Q3
Q2
Q1
Q0
9
7
2
1
10
Q3
Q2 6
Q1 3
Q0 15
This stores 4
bits in parallel
20
Register Variants
• Sometimes there’s also a LOAD input.
– When LOAD is false, the F/F doesn’t change.
– When LOAD is true during the clock edge, the
F/F updates itself.
• Sometimes the outputs are 3-state or open
collector.
– This allows several registers to be connected
to the same output wire
21
74377 Octal D F/Fs with Enable
Positive edge triggered
... but only when
/EN is active LO
11
1
18
17
14
13
8
7
4
3
CLK
EN 377
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
19
16
15
12
9
6
5
2
Stores an 8 bit
number
22
74374 Octal D F/Fs with 3-State
Outputs
11
Positive edge triggered
CLK
/OE is active LO output
enable
Determines when register
contents are visible at the
outputs
18
17
14
13
8
7
4
3
374
H
G
F
E
D
C
B
A
19
QH
16
QG
15
QF
12
QE
9
QD
6
QC
5
QB
2
QA
OE
1
Stores an 8 bit
number
Note: LW uses different labels from the 377, and from Katz!
23
Register Files
Store several words
• You read or write one word at a time.
• 74670 4-by-4 Register File with 3-State Outputs
4 words of 4 bits each
Data in: D1,D2,D3,D4 Data out: Q1,Q2,Q3,Q4
Read selects: RB,RA Write selects: WB,WA
Active low read enable /GR, write enable /GW
Can read and write simultaneously.
No clock. Read or write when enables asserted.
Watch out for glitches!
11
GR
4
RB
5
RA
670
12
GW
13
WB
14
WA
3
D4
2
D3
1
D2
15
D1
6
Q4
7
Q3
9
Q2
10
Q1
To write Word 1, set GW = 0 and (WB, WA) to (0,1)
To read Word 2, set GR = 0 and (RB, RA) to (1,0)
24
Random Access Memories
• Same idea as a register file, but optimized for very
many words.
• Small RAM: 256 4-bit words.
• Larger RAM: 4 million 8-bit words.
• More details later.
25
Shift Registers
• Some registers are designed to change their
stored data.
• Shift registers shift their bits left or right.
For example, right shift:
Original contents
1000
Shift right:
0100
Shift again:
0010
…and again:
0001
… once more, wrapping:
1000
• Application: send a word to a modem bit-by-bit.
• We need some way to initialize the shift register.
26
Input and Output
• Serial input
The shift register doesn’t wrap around from right
to left.
Instead, the user provides the new leftmost bit.
• Parallel input
You can specify the whole word at once.
• Serial output
The bit just shifted off the right is visible at a pin.
• Parallel output
Every stored bit is visible at an output pin.
This uses more pins, which can be a problem.
27
74194 -more4 bit bidirectional universal
shift register
10
S1
9
S0
7
4 modes set by S1,S0
00: hold data (QA,QB,QC,QD)
01: shift right (SR,QA,QB,QC)
10: shift left (QB,QC,QD,SL)
11: parallel load
SL (aka LSI): left shift input
SR (aka RSI): right shift input
Positive edge triggered
194
SL
6
D
5
C
4
B
3
A
2
11
1
QD
QC
QB
QA
12
13
14
15
SR
CLK
CLR
/CLR: asynchronous clear
28
74194 continued
• Notation conflicts:
– LogicWorks uses SL, SR. Katz uses LSI, RSI.
– LW uses A,B,C,D for inputs and QA,QB,QC,QD for outputs.
– Motorola uses P0,P1,P2,P3 for inputs, Q0,Q1,Q2,Q3 for outputs
and DSR & DSL for serial inputs.
• Note that the normal LW convention is that A is the lo-order bit. This
is the way you normally connect the hex keyboard and the hex
display. For the 194, A and QA are the hi-order bits. It's confusing.
• Right shift in more detail. All together on the rising clock:
SR  QA, QA  QB, QB  QC, QC  QD, QD is lost.
Connecting QD to SR makes a circular shift register.
• Left shift in more detail.
SL  QD, QD  QC, QC  QB, QB  QA, QA is lost.
29
Do Activity #2 Now
Due: End of Class Today
RETAIN THE LAST PAGE (#3)!!
For Next Class:
• Bring Randy Katz Textbook, & TTL Data Book
• Required Reading:
– Sec 7.2, 7.3 of Katz
• This reading is necessary for getting points in
the Studio Activity!
30