EX 4
DIGITAL ELECTRONICS (GROUP 1BT4)
G________
After completing the task and studying units from 1.8 to 1.12, students will be able to: (check all that apply):
 Design and use standard combinational circuit building blocks: multiplexers (or data selectors),
demultiplexers (or distributors), binary decoders and encoders, decoders for hexadecimal to seven-segment
LED displays, code converters
 Simplify or minimize logic function using software like Minilog
 Design and use standard arithmetic combinational circuits: Arithmetic combinational modules and networks:
1-bit half adder and full adder; ripple-carry and fast carry-lookahead adder modules, adder and subtractor
unit of signed integers in two’s complement, overflow and zero detection capabilities, comparators, array
multipliers for unsigned numbers, one-digit and larger BCD adders, parity generators and checkers,
arithmetic logic units (ALU)
 Implement logic functions by the method of decoder
 Implement logic functions by the method of multiplexers (Shannon’s Expansion Theorem)
 Plan and organise in the basic 3 blocks (input, output and control) an application project
 Apply the application project template for writing a quality document
 Produce a written solution for the exercise using the instructions from:
http://epsc.upc.edu/projectes/ed/unitats/unitat_1_1/Criteris_Correccio_Exercici.pdf
 Work cooperatively in a team of 3 members using the method described in:
http://epsc.upc.edu/projectes/ed/problemes/metode_resolucio_cooperativa_recomanat.pdf
Write down the most significative doubts or questions you have had while or after completing the task:
STATEMENT:
My signature below indicates that I have (1) made equitable contribution to EX 4 as a member of the group, (2) read
and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3)
acknowledged by name anyone outside this group who assisted this learning team or any individual member in
completing this document.
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Today’s date: __________________
Active members
Roles: (reporter, simulator, etc.)
(1) ___________________________
_______________
(2) ___________________________
_______________
(3) ___________________________
_______________
Acknowledgement of individual(s) who assisted this group in completing this document:
(1) _______________________
(2) _______________________
Group work
Study time
Sessions
TGA, TGB
Sessions
TGC
Individual
Student 1
(in hours)
Student 2
Student 3
Let’s start the design of a simple calculator.......
Planning the general calculator’s block diagram
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Our aim is the design of a simple 2-digit calculator, capable of performing, with signed or unsigned numbers, the
addition, subtraction and multiplication operations. First of all, explain the block diagram in Fig. 1 where the
keypad and the display subsystem are shown.
thousands
3
4
5
6
7
8
9
+/-
0
C
+
x
VI-402-DP
K_L[9..0]
Sign
Clear_key
=
Function_keys
CALCULATOR
Fig. 1 Input, output and control modules of the digital clock to be designed
2
units
U1
APPLICATION PROJECT
Display
_
tens
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
2
1,40
1
hundreds
2
With respect to the block diagram in Fig. 2, which has been largely discussed in class, determine the input and
output range for every block in the circuit, so that all the operations can be performed without overflowing the
machine.
Designing the keyboard encoder
Let’s begin with the design of the data keyboard encoder and the remaining keys interface.
Cascading standard blocks
3
Use a cascadable COD4:2 block to produce the numeric keyboard encoder COD10:4 needed in Fig. 3 for encoding
the number keys. Group select data output (GSD) is high when any numeric key is pressed. Compare your design
with the one you will obtain when using the standard chip 74LS147 (see Fig. 4).
Designing the display subsystem
As shown in Fig. 2, a multiplexed quadruple BCD to 7-segment display subsystem system has to be implemented in
order to represent both, the operands A and B, and the calculator result.
4
Implement the dual 4MUX4 cascading basic MUX2 (and demonstrate their operability producing a Proteus
project and verifying it.
Implementing logic functions using the method of decoders
5
Deduce the truth table for an active-high (for common cathode) hexadecimal to 7-segment display decoder
(HEX-7SEG). The block must have a ripple blanking input and output. Implement the decoder block considering
these 4 design options:
a) Simplifying by Minilog (or Karnaugh) and using NAND gates only
b) Using the method of decoders
c) Using a standard commercial BCD-7SEG chip. Produce the Proteus circuit to verify your design.
d) Readapting this already operative chip:
http://epsc.upc.edu/projectes/ed/problemes/problemes_PA/problema_1_1_HEX_7SEG_portes.DSN
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NUMERIC DATA
DATA REGISTER
K_L[9..0]
K_L[9..0]
data[3..0]
GS
Sign_key
COD[3..0] AT[3..0]
AU[3..0]
LDB
LDA
BT[3..0]
BU[3..0]
CD
CLK
GSD
NUM_KEY
DATA_REG
FUNCTION KEYBOARD
F_L[3..0]
A
S
M
R
K_L[3..0]
Add
Subtract
Multiply
Return
AT[3..0]
AU[3..0]
BT[3..0]
BU[3..0]
SIGN_REG
SIGN
SignA
LDS
SignB
CLK
FUNCT_KEY
SIGN_REG
BCD-TO-BIN
2'S-COMPLEMENT
ARITH
AU[3..0]
AT[3..0]
AT[3..0]
AU[3..0]
A
A
A
A
BU[3..0]
BT[3..0]
BT[3..0]
BU[3..0]
B
B
B
B
SignA
SignB
Op1
Op0
TWOS-COMPLEMENT
Clear_key
Result
SignA
SignB
BCD-BIN_CONVERTER
SignA
SignB
Result
ARITHMETIC-UNIT
DISPLAY MUX AND LCD DECODER
BIN-BCD
AT[3..0]
AU[3..0]
CH0A
CH0B
BT[3..0]
BU[3..0]
CH1A
CH1B
U
T
H
CH2A TH
CH2B
REST
Result RESU
Result
LCD_DRIVER
RESTH
RESH
U[6..0]
T[6..0]
H[6..0]
TH[6..0]
Display
LCD_CLK
TH
H
Disp1
Disp0
BIN-BCD
LCD_DRIVER
DISP_SUBSYSTEM
QUARTZ TIME BASE
CONTROL_UNIT
X1
XTAL
FREQ=1MEGHz
X2
CLK
Add
Subtract
Multiply
Return
LCD_CLK
CLK
A
S
M
R
GSD
CLK
Disp1
Disp0
Op1
Op0
GS
CLK
Clear_key
LDS
LDA
LDB
CD
TIME_BASE_DIVIDER
FSM
Fig. 2 Initial block diagram interconnection for the calculator
0
4
8
1
5
9
K_L0
K_L4
K_L8
K_L1
K_L5
2
6
K_L2
3
7
K_L6
K_L3
K_L7
NUMERIC KEYBOARD
K_L9
CODI[3..0]
K_L[9..0]
COD[3..0]
K_L[9..0]
GS
GSD
NUM_KEY
HSFig. 3
MSencoder for the
SS
Keyboard
dataF_L2
key inputs, TS
whichF_L3
are active low
F_L1
F_L0
FUNCTION KEYBOARD
CODI[1..0]
4
F_L[3..0]
K_L[3..0]
GS
FUNCT_KEY
VCC
FC[1..0]
GSF
Fig. 4 Specifications for the encoder standard chip1 in low power Schottky
technology (LS)
Fig. 5 Standard MUX2 chip in High Speed CMOS TTL logic (HCT) logic family: 74HCT1572
6
Make the necessary circuits for driving a LCD 7-segment display like the VI-402-DP from Varitronix sketched in
Fig. 6 into the Proteus simulation virtual laboratory.
1
http://www.ortodoxism.ro/datasheets/motorola/SN74LS148D.pdf
2
http://www.ortodoxism.ro/datasheets/philips/74HC_HCT157_CNV_2.pdf
5
Fig. 6 Layout for the 4-digit liquid crystal display (LCD) from Varitronix at:
http://www.varitronix.com/Product/LCD/VI-402-DP(R0).pdf
Implementing logic functions using the method of multiplexers
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As an alternative design option, each member of the cooperative group can implement one of the segment
outputs A, B, C, D, E, F, or G using the method of multiplexers and a MUX2 (or a MUX4, or a MUX8, or a MUX16).
Discuss the drawbacks of the multiplexer’s method if, like in this case, many outputs have to be implemented,
and compare with the advantages of the decoder’s method.
Designing arithmetic circuits: the adder-subtractor
8
Accordingly to all the (signed) binary arithmetic developed in EX1, plan and implement the adder – subtractor for
the project by both methods:
a) Cascading 1-bit adders (ripple-carry) and,
b) Using commercial fast carry-lookahead adder modules
Designing arithmetic circuits: the multiplier (for the next EX6)
9
Accordingly to all the (signed) binary arithmetic developed in EX1 and EX2, plan and implement the multiplier for
the project by both methods:
c) Cascading 1-bit multiplier cells adders (hardware array multiplier) and,
d) Sequential multiplier (software multiplier). Discuss the drawbacks and advantages of both methods (speed,
power consumption, number of gates, etc.)
This EX4 is the way to start your application
project........
1. Choose a title for the application project you want to develop (in this case, the
calculator)
2. Read the application project documentation template found in
http://epsc.upc.edu/projectes/ed/projectes_aplicacio/Projectes_aplicacio_ED.
htm
3. Plan the general block diagram specifying clearly the input and output
combinational subsystems and the control block (in this case, Fig. 1 and Fig. 2)
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4. Design the individual combinational blocks of your project considering what
you have learned from EX1 to EX3 and structuring the cooperative work within
the group.
And later on, through EX5, EX6, EX7 and EX8 we’ll
develop the necessary expertise to build the control unit
and the memory blocks
Remember that if in any other occasion through your studies, you are required to
design another project; you must follow a similar proceeding.
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DIGITAL ELECTRONICS
G________
Working plan3 for solving the exercise EX 4
Explain succinctly how the cooperative group has organized the realization of the exercise: i.e., detail your working
plan and the way in which you have divided the task so that more or less all of you have done a similar amount of
work; how have you learned from each other and from other groups; what has been worked out in class time
(sessions A and B) and what has been resolved in sessions C; and so on... Write down also your impressions or
opinions about the subject and how your group work is going by now4 ...
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This document, filled before delivering the exercise, will be included in the group learning portfolio
Check similar documents in http://epsc.upc.edu/projectes/ed/unitats/ED_0506_Q1_Autoavaluacio_Grup_Base.pdf, and
http://epsc.upc.edu/projectes/ed/unitats/que_va_malament_al_grup.pdf
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Active members’ names and signatures
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