EE25266 – ASIC/FPGA Chip Design
Mahdi Shabany
Electrical Engineering Department
Sharif University of Technology
Assignment #6
HW/SW Co-Design, SoC System Builder, NIOS Processor
Introduction
Hardware implementation is the conventional approach to design a system. In some cases, it is
better to design a software and then perform the software on a processor. Hardware Software
Co-design is the way that a part of the design is implemented using some logics in the hardware
such as FPGA and CPLD and the remained parts of the design are implemented using the
software, which should be ran on a processor. In most cases the co-design method will result in
an efficient design compare to the hardware/software designing.
In this assignment you will learn about co-design with ALTERA. You should design a NIOS
processor and run a simple program on it. Then you should connect it to a simple hardware (i.e.
LEDs, 7-Segments, and LCD), which is designed in the Quartus.
Design Flow
1- Please read the NIOS II tutorial carefully, which is uploaded on the course
website.
 After reading this tutorial you can create a new SOPC Builder System and
define the system in SOPC Builder. Also you can integrate the SOPC Builder
System into the Quartus II project and download the hardware design to the
target FPGA. Moreover, you can develop a software using the Nios II IDE and
then run the program on the designed processor.
2- Consider the following important notes and perform the steps of the design
example, which is a simple counter.
Important Notes:
 Some part of your design is different from the design example. Your design is
an extended version of it. So do NOT use the pre-designed files in the web.
 On page 16, it is impossible to run LCD with on chip memory, because there
is no enough space in the Cyclone II chip. The solution to this problem is the
use of off-chip memory of which the DE2 board offers three choice, SDRAM,
SRAM, and Flash Memory. We’re going to go with SDRAM for right now.
Moreover there is no clock to actually run the SDRAM chip. In order to use
SDRAM successfully, it must run off a clock that is 3 ns slower than master
clock driving the processor. If SDRAM_CLK is not created or is connected to
the same clock as the processor then NIOS will encounter run-time errors
when accessing memory. Add the SDRAM controller and a PLL to create its
clock follow the procedure comes at the end of this doc.
 On page 24, please add two 7-segments (i.e. HEX0 and Hex1) and LEDR (i.e.
LEDR[7..0]) to display the output of the design.
 In this step add the LCD to your design. So in the list of available
components, expand Peripherals, expand Display, and then click Character
LCD (See Fig. 1).
 The port names are important for NIOS processor. So choose the same
names with the tutorial. Choose lcd_display for LCD.
 On page 40, before running the program please find the delay function in the
“Counter.c” and increase the delay. Show the difference to the TA.
3- Thus you should display the output of the counter on the red lights, green lights, 7segments, and LCD. Be sure that all of the ports are added to your design and also the
corresponding addresses are assigned to them.
4- In order to perform the pin assignment, please refer to the DE2-70 manual and find
the correct pin locations. If the 7-segments don’t work correctly, then change the pin
assignment of them.
Fig. 1 . Add LCD as a new peripheral.
SDRAM Controller and PLL
1. It is impossible to run LCD with on chip memory, because there is no enough space in the
Cyclone II chip. The solution to this problem is the use of off-chip memory of which the DE2
board offers three choice, SDRAM, SRAM, and Flash Memory. We’re going to go with SDRAM
for right now. Add the SDRAM controller found under external memory interfaces as seen in
Figure 1.
Figure 1 Add the SDRAM Controller
2. In the wizard that appears, none of the preset SDRAM memory devices are used on the DE2
evaluation board so we have to write our own specifications which are elaborated in the
documentation. Select Custom in the Preset pull down and change the data width to 16 bits.
Leave the rest of the options unchanged as seen in Figure 2.
Figure 2 SDRAM wizard as modified for the DE2 board
3. Modify the processors reset and exception vector to use the SDRAM memory in page 18 like
Figure 3.
Figure 3 Modify the Reset and Exception vectors
4. Figure 4 shows LCD pin assignment (green ports needs bidir pins) .
Figure 4 LCD pin assignment
5. Figure 5 shows SDRAM pin assignment (green ports needs bidir pins) .
Figure 5 SDRAM pin assignment
6. At this point the connections that control SDRAM for read/write operation are set; however
there is no clock to actually run the SDRAM chip. In order to use SDRAM successfully, it must
run off a clock that is 3 ns slower than master clock driving the processor. If SDRAM_CLK is not
created or is connected to the same clock as the processor then NIOS will encounter run-time
errors when accessing memory.
7. A "slow clock" will be created to drive SDRAM. Click on Tools -> MegaWizard Plug-In
Manager and click Next.
8. We are going to install a Phase-Locked-Loop circuitry by clicking on I/O and selecting ALTPLL.
Figure 6 Selection and naming the file.
9. On the third page change the device to Cyclone II and the frequency of the inclk0 input to
50.000 MHz and click Next.
Figure 7
10. On page 4 uncheck all the boxes.
Figure 8 Uncheck the options here.
11. Make no changes on page 5 of the wizard.
12. On page 6 change clock frequency to 50 MHz and clock phase shift to 3ns.
Figure 9 Setting the output frequency and phase.
13. Click thru the remaining pages making no changes because they are for other output clocks
and on the summary page, page 10, make sure Quartus II Symbol file is checked then click
Finished.
Figure 10 Check the sdram_pll.bst file in order for the Quartus II symbol file to be generated.
14. After the design is generated it needs to be added to the design.
15. Next we see what the PLL design looks like when added to the top-level. The phase degrees,
54, are the portion of 360 degrees that 3 nanosecond occupy of the 20 nanosecond period.
Figure 11 Here is the PLL inserted into the top-level design.
Figure 12