Booting Excalibur Devices
March 2003, ver. 1.2
Introduction
Application Note 187
The Altera® Excalibur™ devices combines an unparalleled degree of
integration and programmability on a single chip. The advantages of
FPGA flexibility, coupled with a high-performance embedded processor
and integrated on-chip peripherals, provide a powerful platform for
today’s complex, high-bandwidth applications.
To accelerate the development of complex systems, the Quartus® II
software provides an easy-to-use interface for design and implementation
using Excalibur devices. One of the system integration components
included with the Quartus II software is the Excalibur bootloader. When
integrated with the user’s application bootcode using the makeprogfile
utility, the bootloader efficiently starts up the system in boot-from-flash
mode, mapping memory and configuring the FPGA portion of the device
to the user’s specification. When device configuration is complete, the
bootloader branches to the beginning of the user’s code.
Although the Excalibur bootloader has been created to be as universal as
possible, for some applications you might need to control the boot
procedure more tightly than the bootloader allows. The example bootcode
supplied with this document (boot_gnu.s and boot_ads.s) outlines the
steps needed to start up an Excalibur device correctly without using the
bootloader.
1
Configurable
Elements of
Excalibur
Devices
Refer to “Revision History” on page 17 to see the changes made
for this version of the document.
The following list briefly describes the on-chip peripherals and system
definition registers that typically must be initialized and configured
before an Excalibur device is considered to be in user mode.
FPGA Logic
The FPGA portion of an Excalibur device is empty on power-up; it must
be configured before it can be used in the system. In boot-from-flash
mode, you can configure the FPGA logic directly from the embedded
processor via an integrated AMBA™ high-performance bus (AHB) slave
peripheral.
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AN-187-1.2
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AN187: Booting Excalibur Devices
Memory Map
Before you can use the peripherals and memory, you must map them to a
base location in memory space, assign a size, and enable them. Writing
values to a series of memory map registers accomplishes this.
1
This application note sets up registers to boot Excalibur devices
specifically for the example in the document.You can find full
details of the memory map registers and how they govern the
behavior of Excalibur devices in the Excalibur Devices Hardware
Reference Manual.
Embedded Stripe PLLs
The embedded stripe contains two PLLs. PLL1 is used to synthesize the
embedded processor clock and the AHB system clocks. PLL2 is used to
synthesize the SDRAM controller clock. Until the PLLs are configured and
enabled, the system is clocked directly by the input reference clock
CLK_REF.
SDRAM Controller
To use SDRAM, you need to configure the integrated SDRAM controller
to be compatible with the particular SDRAM device chosen. In addition,
you need to initialize the SDRAM device itself before it can be read or
written.
Embedded Stripe I/O
You need to define and enable the embedded stripe’s direct I/O
peripherals prior to use. The available embedded stripe I/O includes a
UART, an expansion bus interface (EBI), an SDRAM controller, and an
embedded trace module (ETM).
Cache Memory
The ARM922T™ embedded processor integrated in Excalibur devices
includes a data and instruction cache to help accelerate system
performance. The cache is disabled at startup. To use it, you must enable
it and define its mode of operation.
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AN187: Booting Excalibur Devices
Boot Process
The process diagram shown in Figure 1 and the following stage-by-stage
description explain one method of booting an Excalibur device. The
process follows the example bootcode in the appendices.
Figure 1. Boot Process Flowchart
Read Chip ID Code
Configure and Start
Stripe PLLs
Configure Memory Map
& Copy Code to SRAM
Configure Embedded
Stripe I/O
Configure & Enable
Cache Memory
Configure & Initialize
SDRAM Controller
Configure PLD Logic
Branch to User Code
Reading the Chip ID Code
Altera recommends that you start the boot process by checking the chip
ID code to ensure that the bootcode is running on the device for which it
was written. It is not obligatory to read the chip ID Code to boot the
device, but it is good practice to check it.
The chip ID code register is located at offset 08H from the memory
registers’ base address. To check the chip ID code, read the proper
memory location and then compare it to the expected chip ID code.
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AN187: Booting Excalibur Devices
1
You will also check the ID code of the chip later on in the boot
process, to ensure that it matches the ID code in the FPGA
configuration file.
Configuring the Embedded Stripe PLLs
This section outlines the configuration process for the embedded stripe
PLLs. For detailed information regarding the operation of the PLLs, refer
to the Clocks section of the Excalibur Devices Hardware Reference Manual.
At power up, each embedded stripe PLL operates in bypass mode,
meaning that both the embedded processor and the SDRAM controller are
clocked directly from the input reference clock CLK_REF. If you wish to
run the embedded stripe at a clock rate different than that of CLK_REF, the
PLLs must be configured appropriately and enabled.
When enabled and locked, PLL1 clocks the ARM922T embedded
processor, the AHB1 peripheral bus, and the AHB2 peripheral bus. AHB1
runs at the same speed as the embedded processor, while AHB2 runs at
half the speed of AHB1. When PLL2 is enabled, its output clocks the
SDRAM controller.
Each PLL contains three counters, M, N, and K, which define its operation.
By writing appropriate values to the registers representing the PLL
counters, you achieve the desired output frequency of the PLLs.
1
Each PLL has the same set of registers, consisting of a register for
each counter, and a control register. There are also registers that
govern the PLLs’ bypass modes and indicate their status.
To configure the PLLs from the embedded processor, perform the
following steps:
4
1.
Determine the M, N, and K values to produce the PLL output
frequencies you require.
2.
Calculate the actual register values for the M, N, and K values. For
details of this process, see PLL Parameter Settings in the Excalibur
Devices Hardware Reference Manual.
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AN187: Booting Excalibur Devices
3.
Write the values to their associated register locations. The register
formats for each counter are shown in Figure 2.
Figure 2. N, M, & K Parameter Registers for PLL1 & PLL2
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_PLL1_NCNT
CT2 CT1 CT0
CLK_PLL1_MCNT
CT2 CT1 CT0
CLK_PLL1_KCNT
CT2 CT1 CT0
CLK_PLL2_NCNT
CT2 CT1 CT0
15..8
CLK_PLL2_MCNT
CLK_PLL2_KCNT
CT2 CT1 CT0
15..8
CT2 CT1 CT0
4.
Address
Base + 300H
15..8
15..8
Base + 304H
1..0 Base + 308H
Base + 310H
10..8
Base + 314H
1..0 Base + 318H
10..8
Write the 14-bit value 00100000011010 to the CTRL field of the
PLL control registers CLK_PLL1_CTRL and CLK_PLL2_CTRL. This
is the optimum value for configuring the locking characteristics of
the PLLs at the frequencies chosen in this example. The optimum
value can change, depending on the frequency you select; refer to the
Excalibur Devices Hardware Reference Manual for details regarding the
CLK_PLLx_CTRL registers. The PLL control register locations are
shown in Figure 3.
Figure 3. Control Registers for PLL1 & PLL2
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address
CLK_PLL1_CTRL
CTRL
P Base + 30CH
CLK_PLL2_CTRL
CTRL
P Base + 31CH
1
Altera strongly recommends that you do not change this
value.
5.
Start the PLLs by setting the P bit in each of their control registers,
CLK_PLL1_CTRL and CLK_PLL2_CTRL. In the example bootcode,
listed in the appendices, the CTRL field and P bit are written
simultaneously as one value to each PLL control register.
6.
Clear the BP1 and BP2 bits in the CLK_DERIVE register to take the
PLLs out of bypass mode. CLK_DERIVE is shown in Figure 4.
Figure 4. Bypass Control for PLL1 & PLL2
Register Name
CLK_DERIVE
Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BP2 BP1
Base + 320H
1
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7.
Wait for the PLLs to lock before continuing. You can do this by
polling the CLK_STATUS register until its 6 least-significant bits, P2,
P1, C2, C1, L2, and L1, are all set to 1. This indicates that both PLLs
are locked and are not in bypass mode. Figure 5 shows the
CLK_STATUS register.
Figure 5. Status Register for PLL1 & PLL2
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_STATUS
8.
Address
P2 P1 C2 C1 L2 L1 Base + 324H
BP2 BP1
Write 1 to the C2 and C1 bits of CLK_STATUS to clear the interrupt
triggered by C1 and C2 when the lock status changes. A change in
the lock status was expected, so it is unnecessary to accept the
interrupt.
Mapping the Peripherals in Memory and Copying Code to SRAM
At this point, the peripherals that you will use must be mapped in
memory to make them addressable. The embedded stripe contains a
group of registers that define each peripheral’s location and size in
memory space. Each peripheral has its own memory map register, and
each memory map register has the same format, as shown in Figure 6.
Figure 6. Memory Map Register
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMAP_xxxxxx
BASE
1
f
SIZE
Address
NP EN Base + offsetH
The address offsets for a memory map register are given in the
mapping method below.
Detailed descriptions of the memory map registers can be found in the
Memory Map section of the Excalibur Devices Hardware Reference Manual.
To map a peripheral in memory, determine its memory map register value
from the peripheral’s size and intended location.
The example bootcode in either appendix maps EBI0, SRAM0, SRAM1,
and SDRAM0 to 40000000H, 20000000H, 20020000H, and 0H
respectively.
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AN187: Booting Excalibur Devices
1
The power-on default boot-from-flash memory map locates EBI0
at address 0H, which is typically where a flash memory resides.
The flash memory is used to hold the bootcode to be executed
when the system powers up. However, fetching instructions
from flash memory is significantly slower than fetching them
from SRAM, so it is common to copy the bootcode from flash
memory to SRAM early in the boot process and run the bootcode
from there.
The following steps describe how the example bootcode in the appendices
maps the memories and copies the bootcode to SRAM0:
1.
EBI0 is mapped at 0H during startup, but because 0H will be the
location of SRAM0, the mapping of EBI0 must be changed so that
there is no overlap. Write the value 40000A83H to the register
MMAP_EBI0 (offset C0H) to re-map EBI0 to 40000000H with a size of
4 Mbytes.
1
2.
Branch to the new mapping of EBI0 by adding 40000000H to the
program counter. Insert an NOP instruction after this branch.
1
3.
Re-mapping EBI0 to 40000000H does not cause the
memory space at 0H (from which the code is currently
running) to become invalid. The boot control register
BOOT_CR controls the default boot mapping. Until the
default boot mapping is turned off, EBI0 is still accessible via
an alias at address 0H even though it has been re-mapped to
40000000H.
Because of the way the embedded processor is pipelined,
the PC always points 2 instructions ahead of the one being
executed. When a branch occurs, the pipeline is flushed, and
the instruction following the branch is not executed.
It is now safe to turn off the default boot mapping, because the
current code is being run from EBI0 mapped at 40000000H. Writing
01H to the boot control register BOOT_CR clears the BM bit, disabling
the default boot mapping. The BOOT_CR register is shown in
Figure 7.
Figure 7. Boot Control Register
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOOT_CR
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9
8
7
6
5
4
3
2
1
0
RE HM BM
Address
Base + 0H
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4.
You now map SRAM0 and SRAM1 at locations 20000000H and
20020000H, and give each a size of 128 Kbytes, by writing
20000803H to MMAP_SRAM0 (offset 90H) and 20020803H to
MMAP_SRAM1 (offset 94H).
5.
Copy the bootcode to SRAM0. An efficient way of doing this is by
setting up pointers and using load-multiple and store-multiple
instructions to copy the data.
6.
Branch to the code that was just copied into SRAM0 by subtracting
40000000H from the program counter. Again, insert an NOP
instruction to avoid skipping an instruction.
7.
Finally, you must map SDRAM0. Write D03H to MMAP_SDRAM0
(offset B0H) to map SDRAM0 to 0H with a size of 128 Mbytes.
Configuring the Embedded Stripe I/O
The embedded stripe I/O includes the UART, EBI, SDRAM, and ETM9
pins. If any pins are to be used in the design, they must be enabled and
configured to use the appropriate I/O standard. If the pins will not be
used by the embedded stripe, they can be used as standard FPGA I/O
pins. The example bootcode in the appendices sets up the device to use the
EBI and SDRAM pins as embedded stripe I/O, both in LVTTL mode; and
the UART and ETM9 pins are configured to be available as FPGA I/O.
To set up the embedded stripe I/O, you write to the appropriate I/O
control register for the device you require. The format for each device’s
I/O control register is the same, and is shown in Figure 8.
Figure 8. I/O Control Register
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOCR_xxxxxx
IC
1
8
OC
Address
IO LK Base + offsetH
The address offsets for the device I/O control registers used in
this example are given in the configuration method below.
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AN187: Booting Excalibur Devices
For the example, you need to carry out the following steps:
1.
Write the value 07H to the SDRAM I/O control register,
IOCR_SDRAM (offset 40H), to configure the SDRAM pins as
embedded stripe I/O with fast slew rate and LVTTL.
2.
Write the value 03H to the EBI I/O control register, IOCR_EBI
(offset 44H), to configure the EBI pins as embedded stripe I/O with
slow slew rate and LVTTL.
3.
Write the value 03H to the UART I/O control register, IOCR_UART
(offset 48H), to configure the UART pins as FPGA I/O with fast slew
rate and LVTTL.
4.
Write the value 05H to the trace I/O control register, IOCR_TRACE
(offset 4CH), to configure the ETM9 pins as FPGA I/O with fast slew
rate and LVTTL.
Turning on the Cache
Cache can be enabled or disabled as required. In this example, you wait
until the final memory map is configured before enabling the cache,
otherwise addresses stored in the cache may become invalid when the
cached memory is mapped to a different address. If the cached addresses
become invalid, the cache must be flushed.
The ARM922T’s memory management unit (MMU) controls instruction
cache and data cache operation. The MMU is implemented as a
coprocessor, which requires the use of special instructions to read and
write its control registers. The example bootcode in the appendices
demonstrates how to activate the instruction cache in round-robin mode.
f
Detailed operation of the MMU is not discussed in this document; see the
ARM922T Technical Reference Manual for details.
To turn on the instruction cache in round-robin mode, perform the
following steps:
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1.
Read register 1 of coprocessor 15 (the MMU) into one of the generalpurpose registers using the MRC instruction.
2.
Set bits 12 and 14 to 1.
3.
Write the value back to register 1 of the MMU using the MCR
instruction.
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Configuring the SDRAM Controller
Not all SDRAM components are built to the same set of parameters. The
SDRAM controller must be made aware of the attached SDRAM’s
characteristics before the SDRAM can be reliably accessed. Configuring
the SDRAM controller as part of the bootcode ensures that when the
application begins, the SDRAM is ready for reading and writing.
The example bootcode in the appendices configures the SDRAM
controller to interface with a Crucial CT16M72S4D75.9T 128-Mbyte
DIMM.
1
The parameters for an SDRAM component can usually be found
in its data sheet. If the characteristics cannot be found in the data
sheet, contact the SDRAM manufacturer.
This section describes the process of configuring the SDRAM controller
for use with a single data rate (SDR) SDRAM device. A brief overview of
the SDRAM controller is given below, but for detailed information about
the SDRAM, refer to the Excalibur Devices Hardware Reference Manual.
To configure the SDRAM controller for SDR SDRAM perform the
following steps:
1.
Ensure that PLL2 has been locked for 100 µs. A software loop can be
used to make sure that this requirement is met.
2.
Load SDRAM_TIMING1 to set the RDC, RAS, RRD, RP, and WR
parameters. Figure 9 shows SDRAM_TIMING1.
Figure 9. SDRAM Timing Control Register
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRAM_TIMING1
RCD
3.
RAS
RRD
RP
WR
Address
Base + 400H
Load SDRAM_TIMING2 to set the RC, CL, BL, and RFC parameters.
Figure 10 shows SDRAM_TIMING2.
Figure 10. SDRAM Latency and Burst Length Control Register
Register Name
SDRAM_TIMING2
10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC
CL
BL
RFC
Address
Base + 400H
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4.
Load SDRAM_CONFIG to set the memory type parameter MT.
Figure 11 shows SDRAM_CONFIG.
Figure 11. SDRAM Memory Type Register
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MT
SDRAM_CONFIG
5.
Address
Base + 408H
Load SDRAM_REFRESH to set the refresh period parameter RFSH.
Figure 12 shows SDRAM_REFRESH.
Figure 12. SDRAM Refresh Period Parameter
Register Name
SDRAM_REFRESH
Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFSH
Base + 40CH
6.
Load SDRAM_ADDR to set the number of row and column address
bits. Figure 13 shows SDRAM_ADDR.
Figure 13. SDRAM Address Register
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRAM_ADDRESS
ROW
7.
COL
10
Address
Base + 410H
Load SDRAM_MODE0 to set the mode register value that will be
written to the SDRAM device. SDRAM_MODE0 is shown in Figure 14.
Figure 14. SDRAM Mode Register
Register Name
SDRAM_MODE0
Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE
Base + 420H
Initializing SDRAM
In addition to configuring the SDRAM controller, the SDRAM device
must be initialized prior to being read or written. Before beginning to
initialize the SDRAM, ensure that PLL2 has been locked for 100 µs. If this
has already been done during the SDRAM controller configuration, you
need not repeat it.
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SDRAM controller initialization must occur within one SDRAM refresh
period. For this reason, you should lock the code that performs the
SDRAM initialization into the instruction cache. The bootcode example in
appendices demonstrates how this can be done.
f
Refer to the Excalibur Devices Hardware Reference Manual for further details
about the instruction cache and the MMU.
To initialize the SDRAM device connected to the SDRAM controller,
perform the following steps:
1.
Enable the controller by setting the SDRAM enable bit, EN, of
SDRAM_INIT. Figure 15 shows SDRAM_INIT.
Figure 15. SDRAM Controller Initialization
Register Name
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRAM_INIT
EN PR LM LEM RF BS SR
2.
Issue a pre-charge all command by setting the perform pre-charge
bit, PR, of SDRAM_INIT.
1
3.
12
Address
Base + 41CH
Be sure to continue writing a logic 1 to the EN bit whenever
you write to the SDRAM_INIT register, or you will disable
the SDRAM controller.
Wait for 50 SDRAM clock periods. To do this, calculate the number
of processor cycles that represent approximately 50 SDRAM clock
periods. Then build a simple software loop that runs for that number
of processor cycles before continuing.
1
Waiting 50 SDRAM clock periods between SDRAM
commands is only necessary for the EPXA10. The delay is
not necessary for EPXA4 and EPXA1 devices; commands
can be written back-to-back.
1
Polling the CLK_AHB1_COUNT register can be an effective
way of accurately measuring AHB1 clock cycles.
1
The delays in this example are determined by the clock
frequencies involved. If different clock frequencies are used,
delays must be re-calculated.
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AN187: Booting Excalibur Devices
4.
Issue a refresh command by setting the perform refresh bit, RF, of
SDRAM_INIT.
1
Again, be careful not to disable the SDRAM controller.
5.
Wait for 50 SDRAM clock periods.
6.
Issue a second refresh command, again by setting the perform
refresh bit, RF, of SDRAM_INIT.
7.
Wait for 50 SDRAM clock periods.
8.
Issue a load mode register command by setting the load mode
register bit, LM, of SDRAM_INIT. The SDRAM’s mode register is
loaded with the value that has been programmed into
SDRAM_MODE0.
1
9.
Steps 1 to 8 must be completed in one SDRAM refresh period, so
this is the section of code that you need to lock into the
instruction cache.
Wait for 50 SDRAM clock periods.
The SDRAM is now ready for reading and writing.
Configuring the FPGA
At this point, you are ready to configure the FPGA portion of the device.
The configuration data used to configure the FPGA from the embedded
processor is created by the Quartus II software. When the Quartus II
software compiles the hardware portion of an Excalibur design, it creates
a configuration data file called a slave-port binary (.sbi) file. The .sbi file
is a binary file that contains the sequence of data that, when written to the
FPGA configuration logic, completely configures the FPGA portion of the
device. Table 1 shows the format of .sbi files.
Table 1. .sbi File Format
Offset
Size
Data
0H
4
Signature “SBI\0”
4H
4
IDCODE for target system
8H
4
Offset to configuration data (coffset)
CH
4
Size of configuration data in bytes (csize). Must be a multiple of 4
coffset
csize
FPGA configuration data. This is a byte stream to be written to the FPGA slave port
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To configure the FPGA, the .sbi file is loaded, word by word, into a FPGA
configuration register by the embedded processor until configuration is
complete. Prior to the configuration process, the .sbi file must be loaded
into memory so that the bootcode can access it, e.g., by incorporating the
.sbi file into the bootcode itself. The bootcode example in the appendices
shows how this works.
The process for configuring the FPGA using the .sbi file is as follows:
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1.
Include the .sbi file in your bootcode as a data table. The ADS
assembler includes an in-line directive called INCBIN that you insert
in the assembly bootcode where you wish to place the .sbi file data.
The binary file that the directive points to is placed directly into the
code as data. By placing labels before and after the INCBIN directive,
the bootcode can access the .sbi file.
2.
Set a suitable value in the CONFIG_CLOCK register. The clock used to
pass the data to the FPGA controller is a division of the AHB2 clock,
and the divide ratio is set by CONFIG_CLOCK. Ensure that the
configuration clock does not exceed its maximum frequency of
16 MHz.
3.
Read the CONFIG_CONTROL register to check whether the
configuration port is locked. If the lock bit, LK, is set, write
554E4C4BH to the CONFIG_UNLOCK register to clear it and unlock
the configuration port.
4.
Set the configuration bit, CO, of the CONFIG_CONTROL register.
5.
Check the signature and IDCODE of the .sbi file. Check that the
signature is “SBI\0” and that the IDCODE matches that in the
IDCODE register.
6.
Determine the address of the first word of configuration data by
reading coffset from the .sbi file and adding it to the base address of
the .sbi file. Then set the end address of the .sbi file by adding the
first address of the .sbi file to csize.
7.
Write the first configuration word from the .sbi file to the
CONFIG_DATA register.
8.
Check the busy bit, B, of the CONFIG_CONTROL register. If it is set,
continue reading it and wait until it is cleared before continuing. If
the next word of data is written to CONFIG_DATA while B is set, wait
states are inserted.
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AN187: Booting Excalibur Devices
9.
Write the next configuration word from the .sbi file to the
CONFIG_DATA register.
10. Repeat steps 8 and 9 until the end of the .sbi file has been reached.
11. Wait for the configuration port to clear the configuration bit, CO, in
CONFIG_CONTROL.
12. Check the error bit, E, of the CONFIG_CONTROL register to see
whether any errors have occurred. If errors have occurred, you can
reconfigure the FPGA by starting at step 3.
13. You may, at this time, choose to lock the configuration by setting the
lock bit, L, in the CONFIG_CONTROL register. This causes any further
writes to CONFIG_CONTROL to result in bus errors until the
configuration port is unlocked (see step 3).
The Excalibur device is now fully configured and booted. You can either
change the embedded processor to user mode, or leave it in supervisor
mode to apply further application-specific boot procedures. See
“Additional Application-Specific Configuration” on page 16 for further
details.
1
Upon reset, all configuration registers return to their default
startup values. If the device is reset, all configurations performed
during the boot process must be performed again.
It is important that, when booting is complete, the interrupt vector table is
located at address 0, otherwise any allowed interrupts branch to whatever
is mapped at address 0, or to undefined memory space if address 0 is
undefined. The example bootcode in the appendices places the vector
table in SRAM, mapped at 0. In the example, the interrupt handler
routines are infinite loop traps that halt code execution. It is the system
designer’s responsibility to design legitimate interrupt handler routines.
At this point, the device components that are essential for basic system
operation have been configured. However, your own application may
require further application-specific peripheral configuration and software
setup. For instance, if your system is programmed in C, stack pointers for
the various embedded processor modes must be initialized before
branching to any code written in C. Similarly, if your application requires
a UART, the embedded stripe UART peripheral must be initialized before
any software tries to access it.
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Resetting the Watchdog Timer
After booting the device, it is advisable to initialize and reset the
watchdog timer by writing the desired trigger value to register WDOG_CR.
This also sets the value that the watchdog timer expects to see written in
WDOG_RELOAD to A5A5A5A5H. When A5A5A5A5H is written to
WDOG_RELOAD, the watchdog timer is reset. Each time the watchdog timer
is reset, the value that needs to be written to WDOG_RELOAD is the inverse
of the value last written to it.
Additional
ApplicationSpecific
Configuration
f
The following list identifies peripherals and settings whose initialization
and configuration procedures are not covered in this document. You must
complete the setup of these items as required for your application.
■
■
■
■
■
■
■
Stack pointers
Dual-port SRAM
UART
Interval timer
Interrupt controller
PLD-to-stripe bridge
Stripe-to-PLD bridge
Refer to the Excalibur Devices Hardware Reference Manual and literature
from ARM Limited for further details about these topics.
Upon reset, all configuration registers return to their default startup
values. If the device is reset, all configurations performed during the boot
process must be performed again.
16
Altera Corporation
AN187: Booting Excalibur Devices
Revision
History
Table 2 shows the document revision history.
Table 2. Revision History
Date
March 2003
Altera Corporation
Description
Removed appendices—code is supplied with pdf.
July 2002
New appendix to accommodate GNUPro Toolset.
October 2001
First publication.
17
AN187: Booting Excalibur Devices
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