Part A Final
FPGA SETTING USING FLASH
Dor Obstbaum
Kami Elbaz
Advisor: Moshe Porian
August 2012
• Introduction
• Top Architecture
• Micro Architecture
• Testability
• GUI
• Conclusions
• Schedule
• Demo in Lab
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Motivation
Software
Hardware
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
- Pre determined
- Static
How can we
make the
connection?
- Constantly updated
- Dynamic
Non Volatile memory
Schedule
Demo
Motivation
• Hardware operates by configuration written
in the registers
• Software writes up to date configuration in
the FLASH memory
• FPGA setting using FLASH system does the
connection
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
FPGA setting using
FLASH system
FLASH memory
registers
Hardware System
Software Host
TOP Architecture
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Project Goals
• Creating Clients configured by registers that
shall be updated using data stored in FLASH.
• Implementing a data structure that will be
used for data storage in FLASH and for data
transmission to clients.
• Setting an option for a host to read data from
FLASH and write new data to it.
• Implementing strong debugging capabilities
including a useful GUI
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Technical Demands
• Hardware is VHDL Implemented and burned
on Altera Cyclone II FPGA on DE2
development board
• FLASH memory is spansion S29AL032D - 4MB
also on DE2 development board
• FPGA – Host communication via UART
protocol
• Internal communication via Wishbone
protocol
• Software GUI is MATLAB implemented
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Message Pack Structure
SOF
Type
Length
Address
•
•
•
•
Start Of Frame 0x3C – 1 byte
Type – Which Client – 1 byte
Length of data bytes – 1 byte
Address in FLASH memory or register
number – 3 bytes
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Length
Data
Data
• Data – min burst 1 byte
- max burst 256 bytes
Data
CRC
EOF
• Cyclic Redundancy Check (CRC)
• End Of Frame 0xA5
Schedule
Demo
Write Transaction
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Read Transaction
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Micro Architecture
Introduction
Quick Reminder:
• RX path
• TX path
• Wishbone units
• Wait Client
• Leds Client
• Clock and Reset
Detailed understanding:
• Display Client
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
RX path
SOF
Type
Length
Type
Length
Introduction
Address
Top
Architecture
Micro
Architecture
Address
SOF
Type
Length
Address
Data
Data
Data
CRC
EOF
CRC
EOF
Testability
GUI
Conclusions
Schedule
Data
Data
Data
Demo
TX path
Type
Length
Address
SOF
EOF
Type
Address
Length
Data
Data
Data
Data
Data
Data
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Type
Address
Length
CRC
Data
Data
Data
Schedule
Demo
Wishbone communication
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Wishbone master and slave
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Wait Client
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
LEDS Client
Introduction
Technical Demands:
•Control 4 leds on DE2 board:
-on/off
-Blinking frequency
•Operates on a 100 MHz clock
•Inputs: Wishbone interface to
configure registers
•Outputs: 4 led_active signals
• Generics:
- clk_freq_g
- timer_freq_g
- active_state_polarity_g
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
LEDS Client
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Clock and Reset
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Display client
1024
Technical Demands:
•VESA protocol
•Operates on a 65 MHz clock
•Produces 3 kinds of pictures: lines, columns, damka
768 squares
• control frame ROI and shape width and color
•Supports any kind of Resolution and timing by
Generics
•Inputs: Wishbone interface to configure registers
Ourvsync,
Configuration
•Outputs: RGB, hsync,
blank
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Display client
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Integrated
from
RunLen
project
100 MHz
65 MHz
Display client
Enable Lines
Line ROI
Line width
Line color
diff
RGB start val
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Enable Lines
Line ROI
Line width
Conclusions
Schedule
RGB
Line color
diff
RGB start val
Demo
Integrated
from
RunLen
project
Display client
Introduction
We Want Our Frames like These:
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
And NOT like these:
How do we keep Synchronization when registers
Are updated?
Schedule
Demo
Synthetic Data Provider
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Waveform
Introduction
Wishbone
transactions
configures
registers
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Register Valid is ‘0’ while
registers are updated
Schedule
Demo
VESA generator
requests data for a
new frame
Valid Data is supplied after 1 cycle
Testability
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Test Plan
•
•
•
•
•
Write Transactions
Read Transactions
Correct Functionality of Clients
System boundaries
System Generics
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Test Environment
Introduction
DUT
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Example: Generating the correct Frame
-Generate a Text File with a write Transaction to Display Client
Introduction
- Run Simulation
Top
Architecture
Micro
Architecture
- Analyze the results
- Fix Bugs if necessary
Testability
-Run and Analyze again
Correct
GUI
Conclusions
Schedule
Demo
DUT
GUI
Build the
Transition
Register
Description
Packet
Window
Text files
control
Change/Remove
CRC, SOF, EOF
RX and TX
debug window
Messages for
user window
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
GUI and Simulations
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Synthesis Results
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Timing Results
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Debugging the hardware
Problem: First programming on FPGA…nothing happens
Source: The reset button on the DE2 board is active low while our
generic for reset is active high
Solution: Change the reset_activity_polarity_g generic to ‘0’.
Conclusion: The ‘Programming indication led’ is found useful.
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Debugging the hardware
Problem: Writes effect only register address 0.
Source: A FF was not implemented by synthesis because ‘clk’ signal
was not mentioned in a process sensitivity list
Solution: Using signaltap found a bug at the address advancer
(inside clients registers)
Conclusion: When a problem occurs at the hardware but not on
simulation, take a look at Quartus warnings and compilation
report
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Debugging the hardware
Problem: No Display
Source: Forgot to allocate one pin in the pin allocation script
Solution: Using signaltap found hardware is OK. Pin allocation script
was repaired
Conclusion: Double check the pin allocation script
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
What have we learned so far?
•
•
•
•
•
Planning and Specifying a Project
Writing reusable generic code
Protocols: UART, Wishbone, VESA
Integration of many components
Verify logic correctness using waveforms,
text files, BMP files and scripts
• Testing our hardware using GUI and debug
with signaltap
• Documentation of the work done
• Code Review and running a project diary
are useful tools
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo
Schedule
Num.
Due Date
To do…
1
done
CCB specification
2
01.09
Implement CCB
Introduction
Top
Architecture
Micro
Architecture
Testability
3
10.09
Test CCB in lab
4
17.09
FLASH control specification
GUI
Conclusions
Schedule
5
10.10
Implement FLASH control
6
30.10
Full system simulation and debug
7
20.11
Extend GUI capabilities
8
10.12
Final debug in lab
9
28.12
Final Presentation
Demo
Introduction
Top
Architecture
Micro
Architecture
Testability
GUI
Conclusions
Schedule
Demo