ATM over
SONET/SDH
Fiksman Evgeny
Gurovich Alexander
DigLab Seminar
Problems to solve
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Each pair of
multiplexors (A - A’) in
the system has to be
manufactured by the
same supplier.
Access to a single
tributary circuit,
demands
demultiplexing the
whole structure and
then remultiplexing.
The multiplexing
structure different in
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There is an enormous
cost benefit in
removing the
multiplexors entirely.
Synchronous Optical
Network
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The basic structure
in Sonet is a frame
of 810 bytes (STS1).
Sent every 125msec
- minimum speed
51.84
Mbps
The first
three columns of every row are used for
administration and control of the multiplexing
system.
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Sonet
Synchronous
Payload
SPE is pointed byEnvelope
H1,
H2.
Small differences in the
clock are
accommodated by H3
pointer.
Multiple STS-1 frames can be
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byte-multiplexed together.
Four STS-1 to STS-4
 phase-aligned with their
payloads. Four STS-1
to STS-4c.
Synchronous Digital
Hierarchy
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STM-1 is STS-3c
Minimum speed 155.52
Mbps
Accommodates both US
and the European line
speeds.
Faster line speeds are obtained in the same way as
in Sonet - by byte interleaving of multiple STM-1
frames. Four STM-1 frames may be multiplexed to
form an STM-4 or STM-4c at 622.08 Mbps.
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Asynchronous Transfer
Mode
Data transferred in small packets called “cells”
Information flow is along paths called “virtual
channels”.
ATM is designed to make hardware switching
simple.
At the edges of the network, user data frames are
broken up into cells.
ATM over SDH physical interface
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Cells are transmitted
row by row without
regard to row or cell
boundaries.
There are a number of
end-to-end TDM
channels across the
link, independent of
the main channel primary function of
SOH & LOH.
Three standards:
 Sonet
STS-3c
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In the early specifications
H4 points to the cell
boundary.
Now cell delineation done
only by the HEC method.
HEC method for cell delineation
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HCS is a CRC-8
calculation over the first 4
octets of the ATM cell
header.
While searching for the
cell boundary location,
the cell delineation circuit
is
the HUNT
Onincorrect
HCSstate.
the cell delineation state machine
locks on the particular cell boundary and enters the
PRESYNC state.
If no HCS errors are detected in this PRESYNC
period then the SYNC state is entered.
Bibliography
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Asynchronous Transfer Mode (ATM) Technical
Overview - IBM, International Technical Support
Organization, SG24-4625-00.
PMC - PM5346 Datasheet.