• These notes are taken from the book:
It’s The Methodology, Stupid! by Pran Kurup, Taher
Abbasi, Ricky Bedi, Publisher ByteK Designs, ( http://www.bytekinc.com (now a defunct link)
• A tool flow describes the method and order (the methodology) in tools are used produce a design
– Different companies can take the same collection of tools and use a different methodology to produce an IC
– Typically, companies will add their own in-house tools to the offthe-shelf tools to tailor the tool flow to their particular needs
– An ECAD group is usually responsible for designing and maintaining the methodology – they are also responsible for training others in the use of this methodology.
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Functional Specifications
RTL Coding
Behavioral Simulation
Logic Synthesis
Test Insertion/ATPG
Statistical Wire load models for constraints
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ASIC – Application
Specific Integrated
Circuit
ATPG – Automated
Test Pattern
Generation
2

IPO – In Place Optimization
Test Insertion/ATPG
IPO/Physical
Hierarchy Gate-level Netlist Simulation
Floor-Planning
Placement & Route
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• “Timing Closure” refers to producing a design that meets timing specifications
– Want to verify that your design has timing closure before you fabricate
• The problem is that with deep submicron, the parasitics
(R,L,C) of the physical layout greatly affect timing
• This leads to the need to produce layout, extract parasitics from the layout, ‘back-annotate’ the parasitics into your timing verification methodology, and then modify logic/layout in order to meet timing specifications and achieve timing closure
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Logic Synthesis
Placement & Route
Parasitic Extraction
Back Annotation
Files (I.e., SDF)
Incremental Place/Route
Timing Verification
(static timing analysis, gate level simulation
Meets timing?
Yes
LVS, DRC, Tapeout
No
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In-Place Optimization,
Incremental Synthesis
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• In-Place Optimization essentially means to tweak transistor sizes without moving cells around
– Moving cells around requires routing to be modified
• If you have to move cells or change the netlist such that different cells are used, then would like to do it in a local area so that you do not have go through the entire Place/Route process again
– Incremental Place/Route tries to accomplish this
• Incremental synthesis means to read in the gate level netlist, and modify the netlist incrementally in order to meet failed timing constraints
– Does NOT START with RTL, starts with gate level netlist produced by first synthesis pass
– Goal is to change as few as gates as possible, and then use incremental place/route to change the layout.
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Behavioral HDL
System Simulators
HDL Simulators
RTL
Gate-Level
Physical
Domain
Verification Methodology
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Code Coverage
Gate Level
Simulators
Static Timing
Analysis
Hardware
Accelerators
Layout vs.
Schematic (LVS)
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Behavioral
RTL
Testbench Simulation
Gate Level
(post Synthesis, pre-layout)
Goal is to use same testbench for all levels of simulation abstraction, and mix different levels
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Gate Level
(post Synthesis, post-layout)
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HDL-Based
(Verilog, VHDL)
Event-Driven
Logic Simulators
Hardware
Cycle-Based
New technology:
Speedsim, IKOS,
Cobra
Interpreted Code
Verilog-XL
Modelsim
Compiled Code
Leapfrog,
NC-Verilog,
Spec-C,
SystemC
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Schematic-based
Gate-Sim
Obsolete
System
DSP Apps,
Tools:
Matlab,
SPW,
COASSAP
HW
Accel
IKOS
FPGA based from
Quickturn,
IKOS
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• Hardware Emulators usually FPGA-based, used to test functionality of design (can’t simulate at speed)
– Very expensive, used because 10x-100x faster than software simulation
• Hardware Acceleration usually means parallel execution of
VHDL/Verilog/C/C++
• Push towards using C/C++ as simulation language
– Compiled code can be faster than VHDL/Verilog simulators
– VHDL/Verilog usually compiled to a ‘byte code’ form, then byte code is interpreted
– Some simulators will convert Verilog/VHDL to C/C++, then compile for extra speed.
• Cycle-based simulations do not compute what is going on inside of a clock, just results from clock-to-clock
– This is a higher level of abstraction, code can be written in either
VHDL/Verilog or C/C++
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•
Formal Verification means that mathematical techniques to prove that the hardware is correct as it progresses from one abstraction level to another (Behavioral to RTL to Gatelevel to Physical), etc.
• Attraction is that circuit does not have to be simulated – no need for test vector generation
– Generation of test vectors, simulation/checking of vectors time consuming
– Test vectors may not cover all possible cases
• Formal Verification is difficult, very much a research area
• Is currently a ‘hot’ area for tool development
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• Equivalence Checking – most widely used, easiest
– Use a mathematical approach to compare a reference design to a revised design (do two netlists implement the same boolean function?)
– Reference design must be correct
• Model Checking – a research area
– Compare a design implementation against a set of properties (the model) that defines the behavior
– Properties define the specifications of the design
– Incorporates elements of Equivalence checking but goes beyond this
• Theorem Proving – most advanced
– Formally prove two designs are correct
– Designs must be represented in a ‘formal’ specification language that incorporates the specifications of the design in addition to the behavior
– VHDL/Verilog does not include this though extensions have been proposed.
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• Static timing traces paths in the design, computes delays along the paths, and checks if delay constraints met
– No need for vector generation
– Cannot detect glitches, timing failure due to dynamic behavior
(such as charge sharing problems)
– Static analysis used to direct synthesis optimization – synthesis tools computes delay paths and tries to produce netlists that meet constraints
– Setup time violations checked for with ‘slow corner’ timing library
– Hold time violations checked for with ‘fast corner’ timing library
• Full Simulation timing is time consuming, requires test vector generation, but only way to detect dynamic timing faults
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• One way to reduce time spent in timing closure iteration is to have a Place/Route tool capable of timing-driven layout
• During Place/Route, tool uses timing constraints to driven generation of layout (primarily routing)
– Must be able to accurately estimate wire delays during place/route procedure
– Goal is to produce layouts that meet timing constraints so that iterations through physical layout are minimized
• Most modern P/R tools support timing driven layout
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High Level Logic
Synthesis Flow
RTL
Logic Synthesis
Test Synthesis
Placement
Back Annotation
Incremental Synthesis
Parasitic Extraction
& Back Annotation
Clock Tree Insertion &
Routing
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Constraints
Logic synthesis
Detailed Logic
Synthesis Flow
Physical Info based
Synthesis (Inc. Syn)
HDL
Test Ready Synthesis
Pre-Scan Test DRC
Scan Insertion
Post Scan Test DRC
JTAG/IO Pads Synth
SDF Path Constraints
Floorplanning (Placement)
SDF, PDEF, set_loads
Clock Tree Synthesis/Routing
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Technology test synthesis
Parasitic
Extraction
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• Synthesis driven by constraints
• Timing Constraints
– Clock period, setup time, hold time constraint
• Area constraints
• Power Constraints
– Gate choices can definitely affect power consumption
– Logic synthesis can generate gating that minimizes the number of transitions during operation
• Design Rule Constraints
– Maximum loading on outputs
– Maximum transition time on outputs
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File
LEF
PLEF
DEF
Expansion Description
Library Exchange Format
Parametric LEF
Format developed by Cadence
Design Exchange Format Format developed by Cadence
SPEF
SDF
PDEF
Standard Parasitic
Exchange Format
Industry standard format
Standard Delay Format Industry standard format giving pin to pin delays
Physical Design
Exchange Format
Industry standard format for physical cluster and placement information (initiated by Synopsys)
SDF files can be read by Synopsys – contains both gate delays and interconnect delays. SDF can also be generated by
Synopsys. VHDL/Verilog simulators can also use SDF.
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Header Information
Min:Typical:Max
Rising Delays Falling Delays
Delay from input pin to output pin
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Setup/Hold constraints
Interconnect Delays
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• Would like to exchange clustering information between front end tools (logic synthesis - Design Compiler) and back end tools (physical layout)
– ‘clustering’ means that the layout tool needs to place a group of cells (a cluster) close together because they are related
– This will hopefully minimize routing delays between these cells
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Cluster Definition
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Info in logic synthesis tool
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Placement by floorplanner
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• Exchange parasitics between layout tools and delay calculators - delay calculators use parasitics to produce
SDF files
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LEF files describe physical information for layout libraries – used by external place/route tools
Header contains information for technology (layers, spacing, etc).
Macro statements define each cell (pins and obstructions – timing info needed for timing driven layout)
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DEF files contains final placed/routed design
Produced by Silicon
Ensemble after placement/routing, imported back into
Cadence layout editor
(Virtuoso).
Contains physical information for routes, pin placement, cell placement
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