Electro-thermal simulation
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Electro-thermal simulation Methods, tools, examples by: András Poppe poppe@eet.bme.hu BUTE, Department of Electron Devices ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Heat, like gravity, penetrates every substance of the universe; its rays occupy all parts of space. The theory of heat will hereafter form one of the most important branches of general physics. Joseph Fourier, 1824 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Outline • GENERAL INTRODUCTION – role of circuit simulation – electro-thermal simulation – simulation methods • SIMULTANEOUS SIMULATION – operation of a circuit simulator • structure of a simulator • the nodal solution method • generating the equations to be solved – linear DC - admittance matrix – non-linear DC - the Jacobian matrix • device models – electro-thermal device models – thermal model of the chip • BREAK ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Outline (cont.) • THERMAL MODELING for simultaneous electro-thermal simulation – 3D RC model of the chip – Example for an electro-thermal simulation system using 3D RC circuit model • CHARACTERIZATION AND COMPACT MODELING OF THERMAL SYSTEMS – – – – – What is compact? Steady-state model, dynamic model The unit-step response & time-constant spectrum concept Convolution calculus, network models Fast calculation & modeling method • BREAK ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Outline (cont.) • IMPLEMENTATION EXAMPLE of simultaneous electrothermal simulation: SISSI (BUTE) – Introduction, design flows – History of implementations, snapshots of operation – Future extension • SIMULATION EXAMPLES WITH SISSI – Typical examples highlighting the importance of electro-thermal simulation • OTA, micro hot-plate, layout/packaging dependent OpAmp behavior – Experimental validation • Early program version integrated into Cadence Opus ECPD10 design kit • Reverse engineered mA741 variants simulated with the recent solver & measured • Study of micromachined RMS meter • OUTLOOK, SUMMARY, LITERATURE – Logi-thermal simulation • ANS’04 THEInternational ENDSummer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary GENERAL INTRODUCTION: role of circuit simulation electro-thermal simulation simulation methods ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary CAD tools in VLSI design Simulator: Representation: Abstraction level Behavioral description System simulator System level design Specification in VHDL or in Verilog Synthesis Logic level design Logic simulation Timing parameters Circuit simulator Schematic editor Structural description Layout generation Transistor level design Layout description Device parameters Layout editor Design rules Physical device simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASONOptimization IST-2000-30193 project of the EU Process simulation Electro-Thermal Simulation By A. Poppe, BUTE, Hungary CAD tools in VLSI design Simulator: Representation: Behavioral description System simulator Abstraction level System level design Specification in VHDL or in Verilog Synthesis Logic level design Logic simulation Timing parameters Circuit simulator Structural description Layout generation Layout description Device parameters Schematic editor Transistor level design Layout editor Design rules Physical device simulation Process simulation Process and device design: TCAD tools used in silicon Electro-Thermal Simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, foundries. Ordinary designers do not use tools. Optimization Bysuch A. Poppe, BUTE, Hungary Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU CAD tools in VLSI design Simulator: Representation: Abstraction level Behavioral description System simulator System level design Specification in VHDL or in Verilog Synthesis Logic level design Logic simulation Schematic editor Structural description Layout generation Transistor level design Details of actual realization are hidden from most of the designers Circuit simulator Layout description Device parameters Layout editor Design rules Physical device simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASONOptimization IST-2000-30193 project of the EU Process simulation Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The role of circuit simulation Simulator: Representation: Abstraction level Behavioral description System simulator System level design Specification in VHDL or in Verilog Synthesis Logic level design Logic simulation Timing parameters Circuit simulator Schematic editor Structural description Layout generation Transistor level design Layout description Device parameters Layout editor Design rules Physical device simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASONOptimization IST-2000-30193 project of the EU Process simulation Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The role of circuit simulation When design is done on transistor level circuit simulation is a verification tool. That is in case of – design of standard cells, – analog circuit design, i.e. in all cases when the circuit is designed in form of – transistor level schematic, or – “manual” layout (or both). ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The role of circuit simulation • In case of digital design: We do not meet it, since the designer does not need circuit simulation on these abstraction levels (system design, logic level design). • Design of standard cells: A cell is designed on transistor level, thus circuit simulation is needed. • Analog design is performed on transistor level, an important tool of verification is always a circuit simulator: • Pre-layout verification • Post-layout verification ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The role of circuit simulation netlist Circuit simulator Transistor level schematic Schematic editor Pre-layout simulation: functional verification ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The role of circuit simulation netlist Transistor level schematic Schematic editor Pre-layout simulation: functional verification Circuit simulator Layout synthesis Layout extraction Layout Layout editor netlist Circuit simulator Post-layout simulation: verification of the realization ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Other tools of verification Transistor level schematic Schematic editor LVS: layout vs. schematic Layout DRC: design rule check ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary But… Still, lots of details of physical realization or effects during circuit operation are not considered in this design flow: • the chip itself (e.g. bulk MOS or SOI) • the effect of the packaging (die attach, bonding, the leads) • etc. The chip itself and the packaging play important role in • high frequency behavior • thermal behavior ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Electro-thermal simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Electro-thermal simulation • Besides electrical behavior thermal behavior is considered • All semiconductor devices – are sensitive to temperature I = I [exp(U /U )-1] F 0 F t – dissipate heat (self-heating) – There is a thermal drift of device and circuit parameters due to • self heating and • heating of other dissipators on the chip • The electrical and thermal behavior of the chip needs to be simulated in a self-consistent manner • Electro-thermal simulation might be needed even in case of digital circuits ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Thermal behavior of a diode Temperature dependence of device parameters: IF = I0 [exp(UF/Ut)-1] I0 exp(UF/Ut) UF = Ut ln(IF/I0) IF UF → ΔUF / ΔT 2mV/oC ΔUF IF IF Hot device Cool device Dissipation: Self-heating: PD = IF UF Tj = PD Rthja How to obtain? ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU UF Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The core of the problem: • The electrical behavior of semiconductor devices is well described by compact (lumped) models The semiconductor equations (PDE-s) are replaced by analytical models (lumped/compact) – these are the device characteristics: J n qmn n E qDn grad n J p qm p p E qDp grad p I id I 0 exp U / UT 1 Dn Dp 2 I 0 Aq ni L N L N n a p d W 2 ni const T 3 exp F kT • Thermal behavior is described by the differential equation of heat transfer p grad T – description is on physical level • Two different abstraction levels have to be treated ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Simulation methods ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Possible simulation methods • Neglect thermal effects – that is the practice now in most cases: – problems remain hidden • Physical level simulation – OK for a single device but can not be used in VLSI design • Simulator coupling: – Circuit simulator that calculates dissipation values and semiconductor model parameters can be recalculated for any temperature – Thermal simulator to provide temperature distribution from the dissipation data ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Possible simulation methods • Simulator coupling: – Problems: • Double iteration – Inside a simulator – Between the simulators ANSYS SPICE • Can not treat circuits with strong thermal coupling • Dynamic electro-thermal behavior (ac, transient) improperly treated • Simultaneous solution (direct method, fully coupled) – Difficult to implement • El.-th. device models? • Efficient thermal model? – Gives correct solutions • For thermal feed-back, • Strong couplings • Dynamic behavior TRANS-TRAN ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Electro-thermal simulation – physical level • Let us consider the flow of carriers in a piece of n-type semiconductor J n qmn n E qDn grad n or D grad J n qm n n E n mn n n General driving force of carriers 1 WF WF n n exp grad n n exp and grad WF 0 Let us substitute: 0 kT kT kT Dn kT Furthermore: E grad U and mn q W With these substitutions we end up with: J n qm n n grad F U q ' WF ' ' U and E grad U and e qm n n Let us further substitute: U q J n e grad U ' Differential Ohm’s law ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Electro-thermal simulation – physical level • Let us consider the heat-flow p grad T Heat-flow equation analogous to the ' differential Ohm’s law J n e grad U current density – heat flux electrical conductivity – thermal conductivity potential – temperature • Coupled flow of charge carriers and energy: ' J n e E S e grad T ' p TS e E TS 2 e grad T S – Seebeck coefficient Electro-thermal cross terms accounting for Seebeck- & Peltier-effect. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Electro-thermal simulation – physical level • Seebeck-effect: Let us assume J n 0 ' ' J n e E S e grad T e E S e grad T E ' S grad T After integrating both sides: U S (T1 T2 ) Might be important in analog IC/MEMS design Thermo potential: proportional to the temperature difference of two locations • Peltier-effect: Let us assume grad T 0 ' J n e E S e grad T ' p TS e E TS 2 e grad T Neglected in analog IC design ' Jn e E ' p TS e E p TS J ' Jn E e Electrically pumped heat-flow ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Electro-thermal simulation – physical level • Tools solving the joint system of partial differential equations (plus Poission’s eq.) ' J n e E S e grad T ' p TS e E TS 2 e grad T are called physical device simulators. • They are suitable for single devices (such as power semiconductors) but can not be used in analog IC design where there are multiples of semiconductors. (execution times, amount of data, difficult problem input) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary SIMULTANEOUS SIMULATION: operation of a circuit simulator electro-thermal device models thermal model of the chip ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Simultaneous simulation • Simultaneous simulation is a method that allows fast and accurate electro-thermal CIRCUIT simulation • Requirements: – Circuit simulation engine with electro-thermal device models – Method of generating electrical model of the thermal system, suitable for circuit simulation – Efficient handling the model of the thermal subsystem during the simultaneous electro-thermal simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Simultaneous simulation Analogy between electrical and thermal systems is used again: dissipator / heat source temperature temperature difference ambient temperature thermal resistance thermal capacitance current generator nodal voltage (potential) voltage electrical ground resistor capacitor ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Circuit simulation programs • The most widely known program is SPICE – Berkeley SPICE – PSPICE – other commercial versions • BUTE Dept. of Electron Devices: TRANS-TRAN (1969…2003) – Many versions for many platforms – First electro-thermal version: 1972. Now it is called SISSI • Helsinki University of Technology: APLAC • SABER, ELDO • etc. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Operation of a circuit simulator ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Structure of a circuit simulator ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Structure of a circuit simulator Preprocessor netlist Input deck (stimuli, control cards, options) Solver (simulation engine or algorithmic core) Library of device parameters Result files Postprocessor GUI ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The (graphical) user interface • Can be realized using the services of the actual design framework – see e.g. Cadence Opus – composer – waveform display program • Can be part of the circuit simulator system like in – PSPICE – TRANZ-TRAN (DOS, SISSI) – Microcap – etc. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Structure of a circuit simulator ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The simulation engine netlist Generation of the network equation Mathematical solution algorithms Device models Library of device parameters ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The simulation engine • Generation of network equations: Automatic generation of the Kirchhoff-equations • Mathematical solution algorithms: Solution of the Kirchhoff-equations • Device models: Semiconductor devices, passive components, generators, etc. The accuracy of these models determines the accuracy of the simulation. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Different types of analysis The most important types of analysis are: • Non-linear DC (determination of the operating point) • Calculation of the DC transfer characteristics (DC simulations in series) • Non-linear transient analysis – time domain analysis • Small signal AC analysis (linearization in the operating point) – frequency domain analysis – at a single frequency – Bode-plot calculation The actual mathematical solution algorithm is determined by the type of analysis in question. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The nodal solution method • The primary properties are the nodal voltages of the network (potentials with respect to the reference point – the “ground”) • Easy to implement • Semiconductor device models fit best the nodal method since most of the models supply branch currents as function of branch voltages • This is the most popular solution method • Inductivity (+transformer) and voltage generators can be described only with non-ideal models (with internal resistance) • The method is based on the nodal admittance matrix ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The nodal admittance matrix • We shall have a look how to create the admittance matrix of a linear n-port: n-1 n 1 I j Y jsU s s 1 n-port j+2 j+1 Ij j 2 Uj 1 0 Y js Definite admittance matrix ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The nodal admittance matrix – a) • The admittance matrix of an “empty circuit” Y js ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The nodal admittance matrix – b) • The admittance matrix of a circuit containing a G conductance Ik k v +G -G k -G +G v k Y js G Iv v Vk Vv ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The nodal admittance matrix – c) • The admittance matrix of a circuit containing a voltage controlled current source with transconductance S vk vv -S +S ik +S -S iv vk ik Ux vv S·Ux Y js iv ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The nodal admittance matrix – d) • The admittance matrix two circuits connected in parallel Yjs= Y1js + Y2js Using rules a) .. d) the admittance matrix can be directly generated from the netlist. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The nodal incidence matrix, Kirchhoff’s equations • Kij – the incidence matrix 3 2 N 3 4 1 2 5 4 7 1 6 0 M=4 N=7 0 if branch i and node j are not connected +1 if branch i starts at node j -1 if branch i ends at node j Nodal currents: I j K ij J i i 1 Ij – nodal currents Ji – branch currents N – number of branches M Branch voltages: U r K rsVs s 1 Ur – branch voltages Vs – nodal voltages M – number of nodes ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Generating the equations to be solved for linear DC simulation • The general branch determines the nature of branch equations, thus, the analysis options – One of the simplest branch equation is Ohm’s law • General branch for linear steady-state analysis: The branch equation is: Ji N J i GirU r JGi r 1 Gii – own conductance Gir – transconductance (i r) Branch current is due to the internal branch current JG and to the own branch voltage or to any other branch voltage. Ui Gii ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU JGi Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Generating the equations to be solved for linear DC simulation • The branch equation is substituted into the nodal current equation: I j K ij J i J i GirU r JGi i 1 r 1 N Ji N N N N I j K ij J i GirU r K ij JGi i 1 r 1 Ui Gii JGi i 1 • The branch voltages are expressed from the voltage equation M U r K rsVs N N N i 1 r 1 i 1 I j K ij J i GirU r K ij JGi s 1 N N M N i 1 r 1 s 1 i 1 I j K ij J i Gir K rsVs K ij JGi N N N I j K ijGir K rs Vs K ij JGi s 1 i 1 r 1 i 1 M ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Generating the equations to be solved for linear DC simulation N N N I j K ijGir K rs Vs K ij JGi s 1 i 1 r 1 i 1 M Y js M N s 1 i 1 Ji Ui I j Y js Vs K ij JGi Gir JGi • We switch off external voltages – thus nodal currents will be 0: M N s 1 i 1 0 Y js Vs K ij JGi • The only unknown is the vector of the Vs nodal voltages. This is a linear equation system of M unknowns. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Equations to be solved for non-linear DC simulation • The general branch: Now the JG own branch current is a (non-linear) function of any Ur branch voltage. Ji Ui Gir JGi(Ur) • This results in a non-linear equation system to be solved: N N N M 0 K ijGir K rs Vs K ij JGi K rsVs s 1 i 1 r 1 i 1 s 1 M This is a non-linear equation system of M unknowns which can be solved e.g. by the Newton-Raphson method. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Equations to be solved in one iteration step (non-linear DC simulation, N-R method) • During iteration the error function hj has to be minimized (must tend to 0) N N N M h j K ijGir K rs Vs K ij JGi K rsVs s 1 i 1 r 1 i 1 s 1 M • hj is the negative of the error of the nodal currents. The N N N N dhj/dVs Jacobian matrix is as follows: KijGir K rs Kij JGi U r i 1 r 1 JGi K G K K K rs ij ir rs ij i 1 r 1 i 1 r 1 U r N N • To be solved: N N i 1 r 1 U r Vs JGi K rs K G ij ir U r i 1 r 1 N N N M N N JG i K rs Vs K ij JGi K rsVs 0 K ij Gir U r s 1 i 1 r 1 i 1 s 1 M For the non-linear DC simulation all elements of the Electro-Thermal Simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Jacobian matrix need to be calculated By A. Poppe, BUTE, Hungary Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Mathematical solution methods • Linear DC simulation (for M nodes) – Solution of a linear equation system of M unknowns (e.g. with Gaussian elimination) • Non-linear DC simulation (for M nodes) – Solution of a non-linear equation system of M unknowns (e.g. with Newton-Raphson iteration) • Small signal AC simulation (for M nodes) – Solution of a linear equation system with complex coefficients of M unknowns (e.g. with Gaussian elimination) • Nonlinear transient simulation (for M nodes) – Solution of a non-linear differential equation system of M unknowns (e.g. with the reverse-Euler method) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Requirements against the solution algorithms • Results of different types of simulation must be consistent, i.e.: – AC(f 0 Hz) DC – Transient results at t = 0 s should be equal to the DC results – Very slow transient DC transfer characteristics • Must be fast and RAM saving – Sparse matrix techniques must be used – For large circuits using advanced equation solvers must be considered • Numerical stability, good convergence properties – modified Newton-Raphson iteration – Adaptive step-size control for transient simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Typical set of component models • Passive components – linear elements – lumped R, C (ideal), L (non-ideal), – transmission line models • Built-in macro models: transformer, linear OpAmp • Generators – linear elements – voltage generator (with loss due to inner resistance) – current generator (ideal, with infinite inner resistance) – controlled sources (voltage controlled I, U) • Semiconductor devices – non-linear elements – Diode, BJT, JFET, MOSFET • User defined models – macro models = parameterized subcircuits – models given by a subroutine (equations) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Component (device) models • Model equations built into the simulation engine: builtin models – they are based on the general branches E.g. model of an ideal diode: J = JG(U)= Io [exp(U/mUt)-1] G = dJ/dU J U JG (U) G • Model parameters In SPICE the set of model parameters is also referred to as model Model topology of a diode for DC simulation • Model topology – the presented diode model consists of one general branch ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Requirements against the device models • Models should match the simulation method E.g. in case of the nodal method models providing I-V characteristics are preferred • input: • output: branch voltage(s) branch current(s), (differential) self-conductance, transconductance(s) if any, branch capacitance(s) • The real devices should be described as accurately as possible • Models should be as simple as possible with small execution time (e.g. EKV vs. BSIM3 MOS models): Explicit, analytical expressions are preferred, internal iterations must be avoided; Number of parameters should be kept low (EKV: 50 vs. BSIM3: cca. 200) • Numerical stability (no crash for extreme inputs) • Easy-to-extract model parameters ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Model topology of a BJT C • Abstract topology with general branches: B B’ transconductances • Details of the model (Ebers-Moll): E IC C ai UB’C B’ B UB’E an E IE For advanced designs more sophisticated models are suggested. The Gummel-Poon model is widely accepted as a good trade-off. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Electro-thermal device models ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Constructing electro-thermal component models Electro-thermal resistor model The constitutive equations: Model topology (terminals, branches) I U / R P I U I A dI/dT R (T) U B U VA VB R R0 exp( (T T0 )) T P T dP/dU transconductances The derivatives are needed for the Newton-Raphson solution algorithm: The derivatives: self conductances dI / dU 1/ R dI / dT I γ dP / dU I U / R 2I dP / dT U dI / dT P ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal These are ALL the elements of the Jacobian matrix of that model Simulation By A. Poppe, BUTE, Hungary Constructing electro-thermal component models Electro-thermal BJT model (simple Ebers-Moll) Model topology (terminals, branches) The constitutive equations: I E f e (U B 'E , U B 'C , T ) IC I C f c (U B ' E , U B 'C , T ) C ai UB’C P T The derivatives: B’ B UB’E P I E U B 'E I C U B 'C T an E IE 2 electrical self conductances 1 thermal self conductance 2 electrical transconductances 4 electro-thermal transconductances dI E/dUB'E dI E/dUB'C dI E /dT dI C /dUB'E dI C /dUB'C dI C /dT dP/dU B'E dP/dU B'C dP/dT ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal These are ALL the elements of the Jacobian matrix of that model Simulation By A. Poppe, BUTE, Hungary Constructing electro-thermal component models Electro-thermal *EKV MOS model Original core electrical-only model (EKV model 2.6): IEKV Two parasitic diodes Thermal branch G T S D IB1 Extensions: Power equation P T IB2 B P I DS VDS I B1VBS I B 2VBD *EKV = Enz-Krummenacher-Vittoz Swiss Federal Institute of Technology ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Constructing electro-thermal component models Electro-thermal EKV MOS model IEKV G T The Jacobian of derivatives is needed again: Delivered by the original model ? dI DS /dV SB dI DS /dV GB dI DS /dV DB dI DS /dT dI B1 /dV SB dI B1 /dV GB dI B1 /dV DB dI B1 /dT dI B2 /dV SB dI B2 /dV GB dI B2 /dV DB dI B2 /dT dP/dV SB dP/dV GB dP/dV DB dP/dT Derivatives of P I DS VDS I B1VBS I B 2VBD S P T D IB1 IB2 B Numerical derivation: dI DS I DS dT T T I DS T T T=1oC ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Constructing electro-thermal component models Electro-thermal EKV MOS model IEKV The price of this simplified solution: the model routine has to run twice for each call. This way the original model code remained unchanged. The thermal extension is done in additional program code. G T S P T D IB1 IB2 B dI DS I DS dT T T I DS T T T=1oC ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Constructing electro-thermal component models Modeling of Si-Al contacts T T U1 S U=ST U2 Due to the Seebeck-effect Si-Al contacts act as small thermocouples (thermoelements). They can be modeled as temperature controlled voltage sources (TCVS). S – Seebeck coefficient: 1..1.5 mV/oC for Si-Al Tricky layout extraction rules: TCVS-s need to be inserted into the nets! Si-Al contacts form pairs (e.g. diffused resistor): THERMOPILES ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Constructing electro-thermal component models Model of (integrated) thermopiles H The constitutive equation: U R C T1 U OUT S (TH TC ) T1 I (U S (T1 T2 )) / R ST1 ST2 S S T2 T2 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Constructing electro-thermal component models Model of (integrated) thermopiles H U OUT C This structure is called gradient (temperature) sensor When connected in series, sensitivity is increased: S (TH TC ) TC TH U OUT 3S (TH TC ) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Thermal model of the chip ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Complete electro-thermal model of a chip • Thermal nodes of the electro-thermal device models must be terminated by an appropriate thermal model. • This model must be the thermal model of the chip. C IC ai UB’C T Thermal model of the chip T I B’ B UB’E an E IE A P1 T1 T2 P2 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU U B Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Complete electro-thermal model of a chip There are many options to account for the thermal model of the chip. One example is given here: Electrical subcircuit with devices having thermal nodes Thermal subcircuit ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Comment • When simulator coupling is used for electro-thermal simulation, the electrical-only derivatives (electrical self conductances and transconductances) are all calculated by the circuit simulator, • but there is no means for the calculation of the electrothermal transconductances of type dP/dU and dI/dT • These elements of the Jacobian of the electro-thermal system will be missing, thus, it is impossible to treat problems with strong thermal coupling, or AC problems. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Break! ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary THERMAL MODELING for simultaneous electro-thermal simulation Modeling guidelines 3D RC model Example ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Modeling guidelines ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Modeling the thermal side The thermal subsystem is considered to be linear. It can be considered as a thermal N-port. Ports are the thermal nodes in the electrical device models IDENTICAL TO the footprints (layout shapes) of these devices on the substrate (IC chip). ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Modeling the thermal side The chip (+ package) thermal structure is considered as a thermal N-port whose ports are the layout shapes of the components. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Modeling the thermal side – guidelines • The thermal behavior of the structure has to be modeled such, that it must be – suitable to be linked to the electrical solution algorithm and – is compact enough to provide a reasonably fast solution. • The thermal model appears in the form of an electrical circuit, where – electrical resistances and capacitances model the thermal resistances and capacitances, – current models the heat flow and – the voltage values represent the temperatures. • Such a model is to be obtained using a thermal simulator. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Thermal modeling and simulation • A thermal model of the substrate (IC chip) is to be created in a thermal simulator. – detailed thermal model of substrate + layout of the dissipating/temperature sensitive elements • The actual physical arrangement must be turned into a thermal RC model • The thermal RC model obtained this way must be handled efficiently in the circuit simulator while the simultaneous electro-thermal simulation is performed. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary 3D RC model of the chip ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Modeling the thermal part: 3D RC network 3D finite difference mesh 3D RC model: chip 3D solid model + layout T I A P U T B ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Modeling the thermal part: 3D RC network 3D finite difference mesh 3D RC model: chip 3D solid model + layout The circuit simulator handles the 3D thermal RC model. T I A P Circuit Simulator U T ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU B Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Modeling the thermal part: 3D RC network Advantage of the approach: relatively easy to implement with advanced solvers the large RC network can be simulated fast (see Napieralski et al., MIXDES 2004) in case of dense layouts (large circuits) its efficiency can be better then that of the NID-based approach temperature distribution is always calculated at any location Disadvantage of the approach: the full thermal model has to be treated always, when the network is simulated with different electrical stimuli – this may result in a large simulation overhead ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example for an electrothermal simulation system using 3D RC circuit model: THERMSIM (Bosch) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation examples: THERMSIM In-house electro-thermal design system of Robert Bosch GmbH using the direct method (simultaneous simulation) G. Diegele, J. Willemen et al. THERMINIC Workshops ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation examples: THERMSIM 3D RC network model is used ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation examples: THERMSIM ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary CHARACTERIZATION AND COMPACT MODELING OF THERMAL SYSTEMS Compact modeling of the IC chip for electro-thermal simulation What is compact? Steady-state model Dynamic model ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Modeling the thermal part: set of thermal impedances by the NID method Instead of the detailed model of the physical chip+layout structure a compact model of the thermal side is created. A modeling method will be described. The method is called Network Identification by Deconvolution = NID ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary What is compact? Models of (thermal) RC systems • Distributed systems - the reality: – detailed models of geometry and material properties • mathematical model: PDE • simulation tools: FEM, FD solvers • computer resource need: HUGE • Compact (lumped) models - abstraction: – details of geometry and material properties neglected • • • • model: circuit (network) composed of a few resistors and capacitors mathematical model: circuit equations (in time domain: differential) simulation tools: circuit simulators (like SPICE) computer resource need: SMALL – a few elements and nodes: COMPACT ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Classification of compact thermal models • Steady-state / dynamic • Behavioral / reflecting physics – Eg. Foster / Cauer This is what we need in case of electro-thermal simulation • Boundary condition independent / setup dependent – BCI models can be used e.g. in package model libraries – setup dependent models (e.g. a Cauer ladder) can be used to replace parts of a detailed model of a complex system ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Compact modeling of the IC chip for electro-thermal simulation 1st approach: steady-state model ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip steady-state Rth matrix model For the sake of easy understanding we start with a steady-state model: R12 2 R13 1 R1 R2 R32 3 R3 R1 R12 R13 Ideal heat-sink at Tamb (thermal ground) Rth R12 R2 R32 R13 R32 R3 For the stead-state case the Rth thermal resistance matrix fully describes the thermal behavior of the chip. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip steady-state Rth matrix model Identification of the elements of the Rth thermal resistance matrix of the chip: T2=R12 T3=R13 T1=R1 For each shape a nominal 1W R R13 1 1W dissipation is forced. 2 12 3 R1 Calculated temperatures on the shapes provide the elements of the thermal resistance matrix: R1 R21 R31 13 Ideal heat-sink at Tamb (thermal ground) R12 R2 R32 R13 R23 R3 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip steady-state Rth matrix model Identification of the elements of the Rth thermal resistance matrix of the chip: T2=R2 1W T3=R23 For each shape a nominal R12 2 R13 1 R1 R23 3 R2 1W dissipation is forced. Calculated temperatures on the shapes provide the elements of the thermal resistance matrix: R1 R21 R31 Ideal heat-sink at Tamb (thermal ground) R12 R2 R32 R13 R23 R3 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip steady-state Rth matrix model Identification of the elements of the Rth thermal resistance matrix of the chip: T3=R3 R12 R13 1 R1 1W 2 R2 3 R3 For each shape a nominal 1W dissipation is forced. Calculated temperatures on the shapes provide the elements of the thermal resistance matrix: R1 R21 R31 Ideal heat-sink at Tamb (thermal ground) R12 R2 R32 R13 R23 R3 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip steady-state Rth matrix model 1 R1 R12 2 R13 R2 3 R3 R23 The number of extra nodes is equal to the number of thermal nodes of the electro-thermal device models. The circuit model of the thermal part does not introduce any extra nodes. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip steady-state Rth matrix model Advantage of the approach: Relatively easy to implement since many thermal simulators can be scripted to apply 1W dissipation on each layout shape and extract temperature data. Compared to electrical-only circuit simulation the number of extra nodes is equal to the number of dissipating/temperature sensitive elements – that is the number of the thermal nodes of the electrical part. This way re-simulation of the system (with unchanged physical structure) is very fast. Disadvantage of the approach: The thermal characterization of the physical structure may take considerable time even with fast thermal simulators, if there are many dissipating/temperature sensitive elements. So far we discussed the steady-state simulation only… Dynamic case comes now. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Compact modeling of the IC chip for electro-thermal simulation 2nd approach: dynamic case ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case Dynamic characterization of the IC chip: Z12 2 Z13 1 Z32 3 Z1 Z21 Z31 Z1 Z2 Z3 Z th Z12 Z2 Z32 Z13 Z23 Z3 Ideal heat-sink at Tamb (thermal ground) The Zth thermal impedance matrix fully describes the dynamic thermal behavior of the chip. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case Dynamic characterization of the IC chip: a12(t) a(t) P(t) a1(t) 1W t Z12 2 Z13 1 a13(t) ln t 3 For each shape a 1W dissipation step (unit step) is applied. The unit step response functions (temperature responses) at the shapes describe the corresponding thermal impedances Z1 Z1 Z21 Z31 Z12 Z2 Z32 Z1 Z12, Z13 is called driving point thermal impedances Z13 Z23 Z3 diagonal elements of the impedance matrix are called transfer thermal impedances off-diagonal elements of the impedance matrix ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case Dynamic characterization of the IC chip: a12(t) a(t) P(t) a1(t) 1W t 2 Z13 1 a13(t) ln t Z12 a(z) z = ln t 3 Z1 Z1 Z21 Z31 Z12 Z2 Z32 Elements of the thermal impedance matrix can be obtained by any thermal simulator in form of dynamic (e.g. unit-step) response functions. Z13 Z23 Z3 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case Identification of the elements of the Zth thermal impedance matrix of the chip: Z12 2 Z13 1 Z1 Z2 Z32 3 Z3 Z1 Z21 Z31 Z th Ideal heat-sink at Tamb (thermal ground) Z12 Z2 Z32 Z13 Z23 Z3 From the dynamic response functions (e.g. unit step responses) compact models can be identified with the NID method. NID = network identification by deconvolution ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary DESCRIPTION AND COMPACT MODELING OF THERMAL SYSTEMS Compact modeling of the IC chip for electro-thermal simulation with the NID method ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The unit-step response and the time-constant spectrum concept ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Unit step response functions • The form of the step-response function – for a single RC stage: R C a(t ) R 1 exp( t / ) R C R characteristic values: R magnitude and time-constant – for a chain of n RC stages: C C C n 1 2 n R1 R2 Rn a (t ) Ri 1 exp( t / i ) i 1 t i Ri Ci R1 R2 1 2 Rn n characteristic values: set of Ri magnitudes and i time-constants If we know the Ri and i values, we know the system. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary t Unit step response functions – for a distributed RC system: n i 1 0 n n a (t ) Ri 1 exp( t / i ) i 1 a(t ) R( )1 exp( t / )d 0 characteristic: R( time-constant spectrum: R() R1 R2 Rn t 1 2 n discrete set of Ri and i values continuous R( spectrum If we know the R(t) function, we know the distributed RC system. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Characteristic functions: step-response Practical problem T3Ster Master: Smoothed response 70 a(t) Unit-step response of an MCM shown in linear time-scale Temperature rise [°C] 60 50 40 30 20 10 t 0 0 200 400 600 800 1000 1200 Time [s] Nothing can be seen below the 10s range Solution: equidistant sampling on logarithmic time scale ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Characteristic functions: step-response Using logarithmic time-scale T3Ster Master: Smoothed response 70 Unit-step response of an MCM shown in logarithmic time-scale a(z) Temperature rise [°C] 60 50 40 30 20 10 z = ln(t) 0 1e-6 1e-4 0.01 1 100 10000 Time [s] Details in all time-constant ranges are seen Instead of t time we use z = ln(t) logarithmic time ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Characteristic functions: time-constant spectrum Discrete RC stages Distributed RC system discrete set of Ri and i values continuous R() function R() a(t ) R( )1 exp( t / )d 0 If we know the R() function, we know the system. R() is called the time-constant spectrum. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Convolution calculus for obtaining time-constant spectra, network models ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Step-response in log. time • Switch to logarithmic time scale: a(t) a(z) where z = ln(t) a(z) is called* – heating curve or – thermal impedance curve • Using the z = ln(t) transformation it can be proven that d a( z ) R( )exp( z exp( z )) d dz 0 *Sometimes Pa(z) is called heating curve in the literature. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Step-response in log. time • Note, that da(z)/dz is in a form of a convolution integral: d a( z ) R( )exp( z exp( z )) d dz 0 Introducing the wz ( z) exp( z exp( z)) function: d a( z ) R( ) wz ( z )d dz 0 d a ( z ) R ( z ) wz ( z ) dz • From a(z) R(z) is obtained as: d R( z ) a ( z ) 1 wz ( z ) dz ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Extracting the time-constant spectrum T3Ster Master: Smoothed response 60 VIPER1-2 - Ch. 0 d Numerical dz derivation Temperature rise [°C] 50 40 a (z ) T3Ster Master: Derivative 30 18 VIPER1-2 - Ch. 0 16 1 wz ( z ) 20 0 1e-6 1e-4 0.01 1 Time [s] Measured thermal impedance curve 100 12 Numerical deconvolution T3Ster Master: Tau intensity 10 10000 d a (z ) dz 8 6 4 2 0 1e-6 1e-4 0.01 1 Time [s] 18 VIPER1-2 - 0 16 14 Time constant intensity [K/W/-] 10 Derivative of temp. rise [K/-] 14 100 12 10 8 10000 6 R (z ) 4 Derivative of the thermal impedance curve 2 0 1e-6 1e-4 0.01 1 100 10000 Time [s] Time-constant spectrum ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Models obtained from time-constant spectra • Discretization • Foster-Cauer conversion • Problems – what strategy to use for discretization? – How to relate elements to physical structures? – Problem of the Foster-Cauer conversion: 100-200 decimal digits of accuracy is needed – Do we always need to convert? • Behavioral models sometimes will do: e.g. electro-thermal sim. – Boundary condition dependent • Good for a given physical arrangement: e.g. electro-thermal sim. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Compact modeling of the IC chip for electro-thermal simulation 3rd approach: fast calculation of time-constant spectra, efficient handling of the RC model ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Calculus of the time constant spectrum It can be proven that the the time-constant spectrum can be calculated directly from the complex Z(s) thermal impedance by the expression below: R( z ) 1 Im Z(s exp( z )) To avoid singularities on the - axis in practice we deviate from the axis by a small angle d, as shown in the figure: Calculation on a line deviated by a small d angle from the - axis. s (cos d j sin d ) exp( z ) 30 2 degree 4 degree 25 er(z) The calculated Rc(z) spectrum is the convolution of the real one with a known er(z) function: RC ( z ) R( z ) er ( z ) sin d exp( z ) er ( z ) 1 2 cos d exp( z ) exp( 2 z )) 20 15 10 5 0 -1 -0.8 -0.6 -0.4 -0.2 0 z 0.2 0.4 0.6 0.8 1 Width of the er(z) function at different d values. The er(z) function is a narrow pulse (see the figure) which can be diminished by setting d to any small value. The e half value with is the measure of resolution: e 2 ln( 2 cos d ( 2 cos d ) 2 1) 2d ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Calculus of the time constant spectrum If a thermal simulator is capable of simulating a detailed thermal model in the frequency domain – thus, providing Z(s) impedances – then with a little modification of the simulation algorithm time-constant spectra can be directly calculated. This sort of calculation has been implemented e.g. in the THERMAN program. R( z ) 1 Im Z(s exp( z )) See Székely et al. (SEMI-THERM 2000, MIXDES 2000) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case Z12 2 Z13 1 Z1 Z2 Z32 3 Z3 Instead of simulating unit-step responses or thermal Bode plots and extracting time-constant spectra from them using the NID method, the THERMAN program directly calculates the time-constant spectra for every thermal impedance. Compact RC models of the impedance matrix elements are created from these time-constant spectra ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case • Direct calculation of time-constant spectra inside the thermal simulator – no deconvolution is involved. See Székely et al. (SEMI-THERM 2000, MIXDES 2000) • Foster model of 3..4 stages created from time constant spectrum. – In case of transfer impedances negative R values are obtained – Formerly twin Cauer-ladders were created to have “physical” model • Since the thermal model of a given physical arrangement remains hidden, Foster models are not converted to Cauerladders – behavioral description of thermal impedances ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case Thermal simulator Layout: Set of time-constant spectra: Thermal model generator Thermal impedances are modeled by Foster networks: C1 C2 C3 R1 R2 R3 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case C1 C2 C3 The time discretized resistive equivalent of a complete Foster chain inside the circuit simulator: R1 R2 R3 Circuit simulator JE1 JE2 JE3 JEk g1 g2 g3 gk 1 The time discredited resistive equivalent of a capacitor: 2 1/R1 3 1/R2 k 1/R3 1/Rk g1 = C1 / t JE1 = C1 (UC1-UC2)/ t C UC g = C / t C UCe/ t The set of these resistive networks is solved in a pre-processing step separately, resulting in the impedance matrix of the thermal part (for every possible t time-step). ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip Dynamic case Modeled by an NN impedance matrix Each impedance is modeled by a set of time-constants and by the equivalent Foster model After having solved the thermal part separately, the number of extra nodes is equal to the number of thermal nodes of the electro-thermal device models. Like in case of the Rth matrix model, the dynamic compact model of the thermal part does not introduce any extra nodes. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Overview of the simulation system Optional ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The compact model of the IC chip dynamic compact model Advantage of the approach: Compared to electrical-only circuit simulation the number of extra nodes is equal to the number of dissipating/temperature sensitive elements – that is the number of the thermal nodes of the electrical part. This way re-simulation of the system (with unchanged physical structure) is very fast. Disadvantage of the approach: The thermal characterization of the physical structure may take considerable time even with fast thermal simulators, if there are many dissipating/temperature sensitive elements. Implementation is not easy: direct calculation of time-constant spectra in the thermal solver special pre-processing of Foster models inside the circuit simulator ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Break! ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary IMPLEMENTATION EXAMPLE of simultaneous electro-thermal simulation SISSI (BUTE) – details, examples ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Introduction, design flows ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Introduction • SISSI: Simulator for Integrated Structures by Simultaneous Iteration – Experimental software package on top of a particular design kit within Cadence Opus • Glued by scripts in the SKILL language of Cadence Opus • Schematic entry, layout extraction, results visualization - system services of Opus • Benchmark problems simulated with success • The package became obsolete since the design kit was abandoned – Second experimental package in C++/FLTK, independent of any design environment – Based on tools of our own development: TRANS-TRAN (BUTE), THERMAN, MODGEN (MicReD-BUTE) • The latest version: original solvers running on a solver server + GUI in Java – also available as applet ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Operation of SISSI • Method of simultaneous simulation • New GUI in Java • Two design flows supported by the applied solver programs – Schematic + draft layout for initial designs – Layout-based simulation for final designs • Layout-based electro-thermal netlist extraction: – simulation of the thermal dynamics of the IC – thermal network identification by deconvolution special nodereduction of the N-port RC ladder of the thermal subsystem • Semiconductor models extended with thermal phenomena and with a thermal port ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Some features of SISSI • The applied thermal modeling method allows to consider the effect of the chip encapsulation. • Due to the simultaneous solution for both the electrical and thermal problems, electro-thermal and thermo-electrical cross-derivatives of the coupled system are generated and used (complete Jacobian). • This allows self-consistent dynamic electro-thermal simulation both in time-domain and in frequencydomain. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Design flows Verification of initial designs Preparation of circuit schematic and draft layout ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Design flows Verification of final designs To be re-implemented Layout-based electrothermal simulation: ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary History of implementations, snapshots of operation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementations of SISSI • 1995: – Cadence Opus + ECPD15 design kit – Layout-based – DC model only based on ThRM • 1996-1997: – Still Cadence Opus – Dynamic compact model of the chip • Characterization in frequency domain • Cauer RC ladders created from thermal Bode-plots • Black-box solution of the thermal N-port in a pre-processing step • 2000-2002: – New, platform independent GUI prototype in C++/FLTK – Thermal model based on direct calculation of time-constant spectra • 2003: – Extended set of electro-thermal device models – Dynamic compact model of chip based on Foster RC models – Verification of the new system (thermal modeling, electro-thermal device models) • 2004: – Latest GUI in Java (work in progress) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The algorithmic core of the recent SISSI system Three separate programs, running subsequently ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The model set of the circuit simulator R,L,C, constant & controlled sources, opamp el-th resistor model el-th diode model el-th BJT model (Ebers-Moll) el-th BJT model (Gummel-Poon) el-th MOS model (simple quadratic) el-th MOS model (substrate effect, Lch modulation, etc) el-th MOS model (EKV=Enz-Krummenacher-Vittoz)* el-th thermocouple model ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for initial design verification Pre-processing C++/FLTK version Schematic entry + draft layout: Simultaneous editing of schematics and layout (for components relevant from thermal point of view) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for initial design verification Pre-processing C++/FLTK version Schematic entry + draft layout ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for initial design verification Post-processing of the results Layout ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU C++/FLTK version Circuit Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for initial design verification Post-processing of the results C++/FLTK version Nodal voltages, device temperatures, Device dissipations, Function plots: • transient, • transfer • Bode Temperature maps • 2D or axonometric • profile cross-sections ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for initial design verification Post-processing of the results ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU C++/FLTK version Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for final design verification Problem input C++/FLTK version Layout-based electro-thermal simulation: layout extractor ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for final design verification Layout extractor – editing the rules ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU C++/FLTK version Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for final design verification Layout extractor – defining the include mask SIAL layer: for extracting Si-Al contacts to consider the Seebeck-effect if needed ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The GUI – for final design verification Layout extractor – results Layout of dissipating & temperature sensitive elements (THERMAN & CIF formats) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Snapshots of the Java version Problem description ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Snapshots of the Java version Simulation log: calculation of time-constant spectra Boundary condition setting for the thermal solver ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Snapshots of the Java version DC temperature distribution Results in the schematic ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Snapshots of the Java version DC temperature distribution ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Future extension ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Work in progress • Extension for PCB problems – Discrete components with package models described with compact models – XML based package model library (emerging new standard in JEDEC) • Solver Server available on the Web + GUI as Java applet ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example of representing PGA package with a compact model Geometry, model netlist TOP 2 4 PINS 20 TOP Chip J 10 X 20 PWR J 0.02 BOTC Board Underfill @SUBCIRCUIT PGAPACK(TOP,BOTC,PINS)=PWR; R1: THRES(X,TOP)=10.0; R2: THRES(X,BOTC)=20.0; R3: THRES(X,PINS)=20.0; R4: THRES(X,J)=4.0; C1: THCAP(X,GND)=2.0; C2: THCAP(J,GND)=0.02; S1: HEATFLUX(GND,J)= PWR; @END; ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary SIMULATION EXAMPLES WITH SISSI typical examples experimental validation MEMS examples ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Typical examples highlighting the importance of electrothermal simulation OTA Micro hot-plate Layout/pacakaging dependent OpAmp behavior ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: operational transconductance amplifier Verification of the extended EKV MOS model and the whole simulation flow ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: operational transconductance amplifier Response of the OTA for 1 mV step-function input ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: operational transconductance amplifier Frequency-domain response of the OTA ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: Micro hot-plate with controlled temperature Heating resistor and sensing resistor on a micromachined membrane: ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: Micro hot-plate with controlled temperature Switching transients on the hot-plate ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Thermal feedback in an OpAmp Steady-state, VOUT > 0 Dissipation of transistor T14: PT 14 VCC VOUT VR OUT L Temperature difference between transistors T1 and T2 of the input differential pair: T Z141 Z142 PT 14 where Z141 and Z14 2 are the T14–T1 and T14–T2 thermal impedances, respectively. This temperature difference results in an access equivalent voltage at the input: Vekv γ( Z141 Z142 ) VCC VOUT VOUT RL -2 mV/oC ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Thermal feedback in an OpAmp Steady-state Effect on the open loop transfer characteristics ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: OpAmp – mA741 Benchmark example of Solomon demonstrating the effect of the thermal feedback on operational amplifiers. Two layout arrangements with different package structures have been simulated. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: OpAmp – mA741 Effect of layout arrangement symmetric layout - symmetric x-fer char. asymmetric layout - asymmetric x-fer char. DC transfer characteristics depend on the layout ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: OpAmp – mA741 Effect of the package structure DC transfer characteristics depend on the package structure Frequency-domain behavior depends on the package structure ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: OpAmp – mA741 Effect of the package structure Transient behavior also depends on the package structure ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Experimental validation Early program version integrated into Cadence Opus ECPD10 design kit ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation in Cadence Opus Electro-thermal simulation: CMOS OpAmp An amplifier with a power output stage has been designed and investigated. The ciucuit has been designed in the Cadence Opus/ECPD10 environment. Different layout variants have been designed for the same schematic. The question was: how does the relative placement of the input and output stages influence the electrical characteristics? Layout dependent thermal feedback was suspected. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation in Cadence Opus Electro-thermal simulation: CMOS OpAmp Different layout versions have been designed and realized by the ECPD10 technology of Atmel-ES2. A layout variant in Cadence Opus ... and realized at Atmel-ES2 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation in Cadence Opus Electro-thermal simulation: CMOS OpAmp DC simulation; good agreement between simulation and measurement, frequency domain simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation in Cadence Opus Electro-thermal simulation: CMOS OpAmp Time-domain behavior: simulation Transient simulation for two layout variants has been performed. Due to different geometries of thermal feedback path different electrical behavior was expected. a) b) In layout version a) thermal feedback is of negative sign. When the feedback path is built up, the output voltage drops. Layout version b) realizes a positive thermal feedback: when the feedback path builds up, the gain of the amplifier is increased. Square wave excitation was applied at the input. Feedback: electrical + thermal. The above plots show the output waveforms. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation in Cadence Opus Electro-thermal simulation: CMOS OpAmp Time-domain behavior: simulation Good agreement between and measurement Load = 0.5 kW Vdd = 6V a) a) b) b) The time constant of the changes in the output signals due thermal feedback is also close to the simulation results. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation in Cadence Opus Micro thermostat Tight thermal coupling, effect of the encapsulation. Good agreement between simulation and measurement Range of ambient temperature where the substrate temperature was stabilized ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Implementation in Cadence Opus Thermal delay line Transient response to square wave; good agreement between simulation and measurement Model of the Si-Al contacts was used. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Experimental validation Reverse engineered mA741 variants simulated with the recent solver & measured ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Thermal feedback in an OpAmp Steady-state Effect on the open loop transfer characteristics ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Methodology of the verification • A commercially available circuit has been investigated: the mA741 operational amplifier. • Both the steady-state and the dynamic behaviour has been simulated and measured. • Two versions from different manufacturers have been studied. – The different designs realise the same electrical network but with different layout arrangement of the components. • The layout of the IC-s has was reverse engineered, based on the microscopic images of the chips. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary OpAmp mA741 in two variants Modeling considerations Circuit schematics Model of the chip packaging Transistors marked with colors were considered by electro-thermal models ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary OpAmp mA741 in two variants Reverse engineered layouts Layout version A Layout version B ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary OpAmp mA741 in two variants Open loop transfer curves (simulated, measured) Layout version A ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary OpAmp mA741 in two variants Open loop transfer curves (simulated, measured) Layout version B ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary OpAmp mA741 in two variants Frequency domain behavior Thermal effects on the output impedance Re – open loop electrical resistance Gv(w) – open loop gain b = R2/(R1+R2) – electrical feedback factor Re Gv (ω) Z OUT (ω) (VCC VOUT )γ( Z141 Z142 ) 1 βGv (ω) 1 βGv (ω) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary OpAmp mA741 in two variants Frequency domain behavior Thermal effects on the output impedance Layout A, transistor T14 operates, G=104 This effect appears in the unloaded opamp! ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary OpAmp mA741 in two variants Frequency domain behavior Thermal effects on the output impedance Layout version A Layout version B These chips differ only in the component arrangement! ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Experimental validation Study of micromachined RMS meter ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: An electro-thermal converter (RMS meter) Heater Thermopile ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: An electro-thermal converter (RMS meter) Steady state results ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: An electro-thermal converter (RMS meter) Frequency domain results ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Example: An electro-thermal converter (RMS meter) Transient results The transient simulation shows the characteristic frequency doubling feature of the electro-thermal converter ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary OUTLOOK, SUMMARY, LITERATURE ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Outlook: logi-thermal simulation ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Logi-thermal simulation Logic level simulation + thermal effects • Gate delays may depend on temperature • Dissipation of one switching event may depend on temperature • Switching density dissipation density temperature distribution Temperature measured on test chip (320mW dissipation in a corner of a 6x6mm2 chip) Temperature gradients observed on a digital VLSI chip, both by simulation and LC imaging (1.5 micron CMOS @ 25 MHz) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Logi-thermal simulation Test Bench 1 Customized PLI Experimental setup: • THERMAN • Verilog • Design framework (Cadnece Opus) Inte rac tiv e Toggle count file .tcf Backannot at ed Netlist + Timin g (.sdf ) Verilog-XL Simulator Waveforms VCD Syst em Task VCD D um p file .vcd Vcd2Tcf TLF Libra ry LEF Libra ry • Initial work: Sign-o ff Test bench Physical Representation Post- Processor Power Calculation Tim ing Fil e .sdf – G. Hajas (BUTE), 1997 • Recent experiments: SKILL Pro ced ure THERMA N input .thc – K. Torki (TIMA), 2003 • See also: K. Skadron et al, Univ. of Virginia, USA Virt uoso Cad ence layout Cells T her mal Map THERMAN Circuit Thermal Map ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU IC Tota l Powe r Stimuli File HD L-A pack age Mode l HDL- A Simulato r Package Thermal Respon se Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Logi-thermal simulation examples Design layout Digital circuit with 2 RAM blocks (0.6µm CMOS, 20k gates, 40 MHz, 15mm2). Maximum temperature gradient was 14 degrees. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Logi-thermal simulation examples Design layout Temperature profile of a 32x32 bits combinational multiplier, (0.18µm CMOS, 7k gates, 200MHz, 0.085 mm2) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Other problems • many wire layers (contacts) • self-heating of the wires ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Summary & literature ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Summary • Electro-thermal simulation in IC/MEMS design is needed if – parasitic effects due to thermal phenomena are present • undesired thermal feedback – the goal is the design of systems utilizing some thermal principle • sensors, other converters • Electro-thermal simulation is an extension of ordinary circuit simulation. There are two usual methods: – simulator coupling – direct method or simultaneous simulation – this is the preferred one ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Summary (cont.) • In case of electro-thermal simulation real electrothermal device models are needed – – – – thermal node / thermal branch temperature dependence of model parameters dissipation equation thermal derivatives: all elements of the Jacobian are needed • Thermal nodes of electro-thermal device models are terminated by the ports of the thermal model of the IC chip. • The thermal model of the IC chip must be correct and must be handled by the network solver efficiently ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Summary (cont.) • Different simulation case studies have been presented – OTA: • difference between electrical-only and electro-thermal simulation • layout dependent behavior (thermal feedback path) – OpAmp: • • • • • • effect of the thermal feedback – DC offset voltage effect of the layout – symmetrical layout: symmetrical characteristics output impedance is also influenced frequency domain behavior differs for different layouts symmetry considerations in layout design are very important even the packaging structure influences electrical behavior via thermal effects (coupling) Symmetrical layout is needed – not only for matching rules but for thermal REASONs, too ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Summary (cont.) • Different simulation case studies have been presented – some MEMS devices / thermal functional circuits have been studied with success • RMS meter: Seebeck-effect was used for sensing (simulated, measured) • micro hot-plate: temperature dependent resistor was used for sensing • micro thermostate: CMOS temp. sensor + strong coupling, effect of packaging was properly simulated (simulated, measured) ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Some literature [1] W.V. Petegem et al. “Electro-thermal simulation and design of integrated circuits” IEEE Journal of. Solid State Circuits, SSC-29(2):143, 1994. [2] W.H. Kao, W.K. Chu. “ATLAS: An Integrated Thermal Layout and Simulation System of IC-s” In Proc. of ED&TC’94, Paris, France, March 1994. [3] Y-K. Cheng et al. “ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits” In Proc. of ED&TC’96, pp. 566-570, Paris, France, March 1996. [4] T. Li, C.H. Tsai, S.M. Kang: “Efficient Transient Electrothermal Simulation of CMOS VLSI Circuits under Electrical Overstress” In Proc. of ICCAD’98,San Jose, CA, USA, 1998, pp.6-10 [5] S.S. Lee, D.J. Allstot: Electrothermal simulation of integrated circuits, IEEE Journal of Solid-State Circuits, SSC-28(12):1283-1293, 1993 [6] G. Digele et al. “Fully coupled Dynamic Electro-Thermal Simulation” IEEE Transactions on VLSI Systems, 5(3):250-257, 1997 [7] M.N. Sabry et al. “Realistic and Efficient Simulation of Electro-Thermal Effects in VLSI Circuits” IEEE Tr. on VLSI Systems, 5(3):283-289, 1997. [8] S. Wunsche, C. Claub, P. Schwarz: “Electro-Thermal Circuit Simulation Using Simulator Coupling”, IEEE Trans. On VLSI Systems, Vol.5,No.3, ,pp 277-282, 1997 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Some literature (cont.) [9] V. Székely et al. “Self-consistent electro-thermal simulation: fundamentals and practice” Microelectronics Journal, 28:247-262, 1997. [10] V. Székely et.al.: Electro-thermal and logi-thermal simulation of VLSI designs, IEEE Transactions on VLSI Systems, 5(3):258-269, 1997 [11] T. Veijola et al. “An implementation of electro-thermal component models in a general purpose circuit simulation program” In Proc. of the 3rd THERMINIC Workshop, pp. 96-100, Cannes, France, September 1997 [12] V. Székely: “Accurate calculation of device heat dynamics: a special feature of the Trans–Tran circuit analysis program”, Electronics Letters,Vol 9,no.6,pp.132-134 (1973) [13] V. Székely et al. “SISSSI - a tool for dynamic electro-thermal simulation of analog VLSI cells” Proc. of ED&TC’97, p. 617, Paris, France, March 1997. [14] M. Rencz et al: “An alternative method for electro-thermal circuit simulation” In Proc. of SSMSD’99, pp 117-122, Tucson, AZ, USA, 1999. [15] L. T. Pillage, R. A. Rohrer: Asymptotic waveform evaluation for timing analysis, IEEE Transactions on Computer-Aided Design, CAD-.9(4):352-366, 1990 [16] V. Székely: Identification of RC Networks by Deconvolution: Chances and Limits, IEEE Transactions on Circuits and Systems-I. Theory and Applications, CAS-45(3):244258, 1998 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Some literature (cont.) [17] V. Székely, A. Poppe, M. Rencz, M. Rosental, T. Teszéri: THERMAN: a thermal simulation tool for IC chips, microstructures and PW boards. Microelectronics Reliability, Vol. 40, pp. 517-524, 2000 [18] J.E. Solomon: “The monolithic Op Amp: A tutorial”, IEEE Journal of Solidstate circuits, Vol.SC-9, No. 6,Dec. 1974, pp 314-332 [19] M. Rencz, V. Székely, A. Poppe: A fast algorithm for the layout based electrothermal simulation, DATE 2003, March 3-7 2003 Munich, proc. pp. 1032-1037 [20] C. Enz, F. Krummenacher, E. Vittoz, 'An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications', Journal on Analog Integrated Circuits and Signal Processsing, Kluwer Academic Publishers, pp. 83-114, July 1995 [21] http://legwww.epfl.ch/ekv [22] V. Székely, S.Török: Verification of an electro-thermal simulation algorithm, 9th Therminic Workshop, 24-26 September 2003, Aix-en-Provence, France, pp.233-238 ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Acknowledgements ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary Acknowledgement The work of the following colleagues at BUTE and TIMA Laboratory (Grenoble, France) is acknowledged V. Székely, M. Rencz project leadership, development of algorithms & models A. Páhi programming, layout design G. Hajas, G. Mezei, Gy. Horváth programming S. Török, I. Hajas, T. Unyatinszki, G. Végh measurements B. Courtois, B. Charlot, K. Torki support of our initial work, manufacturing benchmark circuits and MEMS structures The support of the THERMINIC, DETERMIN, PROFIT and REASON projects of the EU, and different OTKA projects of the Hungarian National Scientific Research Fund is also acknowledged. ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary The End Thanks for your attention ANS’04 International Summer School on Selected Topics in Analog IC Design, Cracow, 13-18 September 2004 Supported by the REASON IST-2000-30193 project of the EU Electro-Thermal Simulation By A. Poppe, BUTE, Hungary
