EE 201A/EE298
Modeling and Optimization
for VLSI Layout
Instructor:
Lei He
Email:
LHE@ee.ucla.edu
Outline

Course logistics
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Overview
 What
are covered in the course
 What are interesting trends for physical design
Instructor Info
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Email: LHE@ee.ucla.edu
Phone: 310-206-2037
Office: Engineering IV 68-117
Office hours: Tu/Th 2-3pm or by
appointment
The best way to reach me:
 Email
with EE201 in subject line
About this Course

One of selective course for EE’s ECS Major Field Students
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Question in M.S. comprehensive exam / PhD prelims
Offered every other spring
Will be under another course number (EE205B)
Related courses
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Mani’s EE202A Embedded Computing Systems (Fall)
Ingrid’s EE201A on Advanced VLSI (Spring)
Bill M-S’s EE204A on Compilers (Winter)
My EE205A Fundamental to CAD (Winter)
Mani’s EE206A Wireless Systems (Spring)
My EE205B (every other Spring)
Course Prerequisites

Official prerequisite
 EE116B
VLSI System Design
 But mainly self-contained
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Knowledge to help you appreciate more
 CS180
Introduction to algorithms
EE205A and EE205B
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EE205A Fundamental to CAD of embedded systems
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System level performance/power/thermal modeling and
optimization
Synthesis – scheduling and allocation, logic optimization
and technology mapping
FPGA circuits and architectures and placement and routing
for FPGA
EE205B Modeling and Optimization for VLSI layout
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Advanced algorithms for physical design
 Fundamentals of combinatorial algorithm
Detailed performance, signal integrity, power and thermal
models
Incorporating physical design into system design
VLSI Design Cycle
System Specification
Functional Design
X=(AB*CD)+(A+D)+(A(B+C))
Logic Design
Circuit Design
Y=(A(B+C))+AC+D+A(BC+D))
VLSI Design Cycle (cont.)
Physical Design
Fabrication
Packaging
Simplified Physical Design Cycle
Partition
Front-end
physical design
Floorplanning
Placement
Routing
Back-end
physical design
Extraction and
Verification
Course Outline and Schedule
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Front-end physical design (4.5 weeks)
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Partitioning, floorplanning and placement
Power and thermal modeling
Algorithms: divided and conquer, simulated annealing, genetic
algorithm
Project proposal due by end of fifth week
Back-end physical design (4.5 weeks)
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Interconnect extraction and modeling
Interconnect synthesis
Noise modeling and avoidance
Clock and power supply design **
Algorithms: dynamic programming, linear programming
Project report due the last day of the quarter
Related VLSI CAD Conferences
 ACM IEEE Design Automation Conference (DAC)
http://www.dac.com (San Diego, Young student program)
 International Conference on Computer Aided Design(ICCAD)
 Design, Automation and Test in Europe (DATE)
 Asia and South Pacific Design Automation Conference (ASPDAC)
 International symposium on physical design (ISPD)
 International symposium on low power electronics and design
 International symposium on field programmable gate array
 IEEE International Symposium on Circuits and Systems (ISCAS)
Related VLSI CAD Journals
 IEEE Transactions on CAD of Circuits and systems (TCAD)
 ACM Trans. on Design Automation of Electronic Systems
(TODAES)
 IEEE Transactions on Circuits and Systems (TCAS)
 IEEE Trans. on VLSI Systems (TVLSI)
 IEEE Trans. on Computer
 Integration
 Algorithmica
 SIAM journal of Discrete and Applied Mathematics
Money Talk for VLSI CAD
 Synposys, Cadence, Magma, Mentor Graphics, …
 Over hundreds companies have booths at DAC
 Two of them are among the ten biggest software companies in
the world
But they are smaller than the biggest spin-off of EDA
 EDA is regarded as A-graded bonds for Venture Capitalists
 One of few IT segments still recruits heavily and offers salary
higher than Intel/IBM
EDA system is regarded as one of the most complicated
software systems mankind ever built
References for this Course
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Selected papers from TCAD, TODAES, and major CAD
conferences such as DAC, ICCAD and ISPD
Naveed A. Sherwani, "Algorithms for VLSI Physical Design
Automation", 3rd Edition, 1998.
H. Cormen, et al “Introduction to Algorithms” MIT Electrical
Engineering and Computer Science Series 1990.
H. Bakoglu, Circuits, Interconnects, and Packaging for VLSI,
Addison Wesley
Cong et al., Performance Optimization of VLSI Interconnect
Layout, Integration, the VLSI Journal 21 (1996) 1--94.
Grading Policy
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Homework
Midterm (7th week)
Course presentation
Term project
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A  score > 85 and programming project
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15%
20%
15%
50%
Course Presentation (15%)
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2~3 student a team
Survey an area (topics and resources specified by me on
a continual basis)
Prepare slides and do a 30-35 minute presentation in
the class
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slides prepared jointly
either all students share the presentation or I will select the
speaker randomly at the presentation time
Prepare a web site that should contain a report based
on your survey, a bibliography, and links to resources
and of course your slides
Term Project (50%)
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One of the following two:
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One-person survey and critic of selected topic (at most 35%)
Individual programming project for a team of 2 to 3 persons
 Coupled system design and physical design
 Floorplanning with thermal constraints
 3D modeling and physical design
 Or any topic agreed by instructor
Up to 30 minute presentation during the finals week,
like a conference talk
Up to 12 page report in the style of a technical
conference paper

ACM style
http://www.acm.org/sigs/pubs/proceed/template.htm
Who should take this course

It is another course
 Discuss
wide scope of knowledge
 But research (presentation + project) on your
own focus

For students who are motivated to
 Learn
SI, power/thermal for advanced designs
 Learn algorithm basics without taking CS280
 Understand CAD better
 Become a CAD professional
Complexities of Physical Design
 More than 10 million transistor
 Performance driven designs
 Time-to-Market
Design cycle
…...
High performance, high cost
Moore’s Law and NTRS
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Moore’s Law
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The min. transistor feature size decreases by 0.7X every three
years (Electronics Magazine, Vol. 38, April 1965)
True in the past 30 years, and expected to hold for another 1015 years
National Technology Roadmap for Semiconductors
(NTRS’97)
Technology (um)
Year
# transistors
On-Chip Clock (MHz)
Area (mm2)
Wiring Levels
0.25
1997
11M
750
300
6
0.18
1999
21M
1200
340
6-7
0.15
2001
40M
1400
385
7
0.13
2003
76M
1600
430
7
0.10
2006
200M
2000
520
7-8
0.07
2009
520M
2500
620
8-9
10,000,000
100,000,000
1,000,000
100,000
10,000
10,000,000
58%/Yr. Complexity
growth rate
1,000,000
100,000
1,000
10,000
xx
10
21%/Yr.
Productivity growth rate
x
100
xx
x
x
x
1,000
100
1
10
1998
2003
Chip Capacity and Designer Productivity
Source: NTRS’97
Transistor/Staff-Month
Logic Transistors/Chip (K)
Productivity Gap
Design Challenges in Nanometer Technologies
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Interconnect-limited designs
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Small feature size
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Interconnect performance limitation
Interconnect modeling complexity
Interconnect reliability
Impact of new interconnect materials
Process variations
Leakage (~50% of total power)
High degree of on-chip integration
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Complexity and productivity
Limitation of current design abstraction and hierarchy
System on a chip and system in package or 3D technology
Power/thermal barrier
Design Styles
Complexity of
VLSI circuits
Performance
Size
Cost
Market time
Different design styles
Full custom
Standard Cell
Gate Array
Cost ,Flexibility,Performance
FPGA
Full Custom Design Style
Pad
Metal
Via
Data Path
PLA
ROM/RAM
Random logic
A/D Converter
Metal 2
I/O
Standard Cell Design Style
Cell
Feedthrough
VDD Metal 1
GND
Metal 2
D
C
A
D
C
Cell A
Cell C
C
B
C
C
C
D
C
C
B
B
Cell B
Cell D
Feedthrough cell
Gate Array Design Style (or Structured ASIC)
A
C
B
VDD
Metal1 Metal2
C
A
B
Field-Programmable Gate-Arrays (FPGAs)
 Programmable logic
 Programmable interconnects
 Programmable inputs/outputs
FPGA Design Style
Comparisons of Design Styles
style
full-custom standard cell
gate array
FPGA
cell size
variable
fixed height *
fixed
fixed
cell type
variable
variable
fixed
programmable
cell placement
variable
in row
fixed
fixed
interconnections
variable
variable
variable
programmable
* uneven height cells are also used
Comparisons of Design Styles
style
full-custom standard cell
compact
gate array
FPGA
moderate
large
Area
compact
Performance
high
high
to moderate
moderate
low
Fabrication
layers
ALL
ALL
routing
layers
none
to moderate
Packaging Styles
Packaging
Printed Circuit Board
PCB
Multi-Chip Module
MCM
Wafer Scale Integration
WSI or 3D
Area
Performance, cost
The increasing complexity and density of the semiconductor devices
are driving the development of more advanced VLSI packaging and
interconnection approaches.
Printed Circuit Board Model
Plated
through
holes
Package
IC
(a)
(b)
 Large number of layers (150a pitch)
 Larger area
 Low performance
 Low cost
MCM Model
IC
(a)
(b)
 Up to 36 layers ( 75a pitch)
 Moderate to small area
 Moderate to high performance
 High cost
 Heat dissipation problems
Wafer Scale Integration
 Small number of layers (VLSI technology- 6a pitch)
 Smallest area
 Significant yield problems
 Very high performance
 Significant heat dissipation problems
Comparisons of Packaging Styles
Technology
Figure of Merit
(inches/psec. density inches/sq in)
WSI
MCM
PCB
28.0
14.6
2.2
Merit = propagation speed (inches/psec.) * interconnection
density (inches/sq. in).
 Interconnect resistance was not considered

Increasingly on the Same Chip or in the
Same Package (SoC and SiP)
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SC3001 DIRAC chip (Sirius Communications)
History of VLSI Layout Tools
Year
1950 - 1965
Design Tools
Manual Design
1965 - 1975
Layout editors
Automatic routers( for PCB)
Efficient partitioning algorithm
1975 - 1985
Automatic placement tools
Well Defined phases of design of circuits
Significant theoretical development in all phases
1985 – 1995
Performance driven placement and routing tools
Parallel algorithms for physical design
Significant development in underlying graph theory
Combinatorial optimization problems for layout
1995 -- present Interconnect layout optimization, Interconnectcentric design, physical-logical codesign
One of the new trends:
SoC and SiP for 3D technology
Summary
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Physical design is the most complicated step in the VLSI
design cycle
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Physical design is further divided into clustering,
partitioning, floorplanning, placement, global and detailed
routing. Extraction and verification is an important aspect.
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There are four major design styles -- full custom, standard
cell, gate array (structured ASIC), and FPGAs.
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There are three alternatives for packaging of chips -- PCB,
MCM and WSI. But increasingly, we design for SoC and SiP
and will use 3D technology
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Automation reduces cost, increases chip density, reduces
time-to-market, and improves performance.
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CAD tools currently lag behind fabrication technology,
which is hindering the progress of IC technology
Homework (due April 14th)
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Read ITRS roadmap executive summary and write one page
summary and critic on one aspect related to your research
or field
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http://public.itrs.net/Files/2001ITRS/Home.htm
Search literature or web related to SoC, SiP and 3D
technology, summarize five papers on a coherent topic
(e.g., technology, design, or CAD) and speculate potential
need of CAD research
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Following style of conference paper
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With course project proposal in mind
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Submit homework in PDF via email
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Check out course website for notes of future lectures
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http://eda.ee.ucla.edu/EE201A-04Spring