Engineering 43
Chp 3.1b
Nodal Analysis
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Ckts with Voltage Sources
 Need Only
ONE KCL Eqn
V2 V2  V3 V2  V1


0
6k
12k
12k
 The Remaining Eqns
From the Indep Srcs
 3 Nodes Plus the
Reference. In Principle
Need 3 Equations...
V1  12[V ]
V3  6[V ]
 Solving The Eqns
2V2  (V2  V3 )  (V2  V1 )  0
• But two nodes are connected
to GND through voltage
4V2  6[V ]  V2  1.5[V ]
sources. Hence those node
voltages are KNOWN
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Example
 Find Vo
 To Start
I S1
V1
• Identify & Label All Nodes
• Write Node Equations
• Examine Ckt to Determine
Best Solution Strategy
 Notice
V0  V1  V2
 Need Only V1 and V2
to Find Vo
 Known Node Potential
@V3 : V3  VS1  12[V ]
Engineering-43: Engineering Circuit Analysis
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V4
R1
IS2
R2
V2
 VO 
V3
R3
R4
IS3
+

VS 1
R1 = 1k; R2 = 2k, R3 = 1k, R4 = 2k
Is1 =2mA, Is2 = 4mA, Is3 = 4mA,
Vs1 = 12 V
 Now KCL at Node 1
V1  V2 V1
@ V1 :  I S1 

0
R1
R4
V1  V2 V1
 2[mA] 

0
1k
2k
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Example cont.
 At Node 2
V4
I S1
V V V V V V
V
@ V2 :  I S 3  2 1  2 3  2 4  0 1
R1
R3
R2
V  V V  12 V2  V4
 4[mA]  2 1  2

0
1k
1k
2k
IS2
R2
R1
V2
 VO 
V3
R3
R4
IS3
+

VS 1
 At Node 4
V4  V2
@ V4 : I S1  I S 2 
0
R2
R1 = 1k; R2 = 2k, R3 = 1k, R4 = 2k
Is1 =2mA, Is2 = 4mA, Is3 = 4mA,
Vs = 12 V
V4  V2
2[mA]  4[mA] 
0
2k
 To Solve the System of Equations Use
LCD-multiplication and Gaussian Elimination
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Example cont.
 The LCDs
*2k
V1  V2 V1
 2[mA] 

0
1k
2k
*2k
V2  V1 V2  12 V2  V4
 4[mA] 


0
1k
1k
2k
V4  V2
2[mA]  4[mA] 
0
2k
3V1  2V2  4[V ]
(1)
 2V1  5V2  V4  32V ]
*2k
 V2  V4  4[V ]
(2)
(3)
 Now Add Eqns (2) & (3) To Eliminate V4
 2V1  4V2  36[V ]  V1  2V2  18[V ]
(4)
 Now Add Eqns (4) & (1) To Eliminate V2
2V1  22[V ]  V1  11[V ]  BackSub into (4) To Find V2
11[V ]  2V2  18[V ]  V2  14.5[V ]  Find Vo by Difference Eqn
V0  V1  V2  11[V ]  14.5[V ]  3.5[V ]
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
SuperNode Technique
SUPERNODE
 Consider This
Example
 Conventional Node
Analysis Requires All
Currents At A Node
@ V1
@ V2
V1
 IS  0
6k
V
 I S  4mA  2  0
12k
 6mA 
 2 eqns, 3 unknowns...
Not Good
• Recall: The Current thru the
Vsrc is NOT related to the
Potential Across it
Engineering-43: Engineering Circuit Analysis
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IS
 But Have Ckt V-Src Reln
V1  V2  6[V ]
 More Efficient solution:
• Enclose The Source, And
All Elements In Parallel,
Inside A Surface.
– Call That a SuperNode
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Supernode cont.
SUPERNODE
 Apply KCL to the
Surface
V1 V2
 6mA 

 4mA  0
6k 12k
• The Source Current
Is interior To The Surface
And Is NOT Required
 Still Need 1 More
Equation – Look INSIDE
the Surface to Relate
V1 & V2
IS
 Now Have 2 Equations
in 2 Unknowns
 Then The Ckt Solution
Using LCD Technique
• See Next Slide
V1  V2  6[V ]
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Now Apply Gaussian Elim
 The Equations
V1 V2

 6mA  4mA  0
6k 12k
(2) V1  V2  6[V ]
(1)
 Mult Eqn-1 by
LCD (12 kΩ)
2V1  V2  24[V ]
 Use The V-Source
Rln Eqn to Find V2
V2  V1  6[V ]  4[V ]
SUPERNODE
IS
V1  V2  6[V ]
 Add Eqns to Elim V2
3V1  30[V ]  V1  10[V ]
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Is2
Find the node voltages
And the power supplied
By the voltage source
R3 I
V1
V2

R1
VS
V
R2
I s1
R1  R2  10k, R3  4k
VS  20[V ], I s1  10[mA], I s 2  6[mA]
V2 V1  20
V1
V
 2  10mA  0
10k 10k
  V1  V2  20[V ]
*10k  V1  V2  100[V ]
adding : 2V2  120[V ]
V1  100  V2  40[V ]
To compute the power supplied by the voltage
source We must know the current through it: @ node-1
IV 
Engineering-43: Engineering Circuit Analysis
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V1
V V
 6mA  1 2  5mA
10k
4k
P  20[V ]  5[mA]  100mW
BASED ON PASSIVE SIGN CONVENTION THE
Bruce Mayer, PE
POWER IS ABSORBED BY THE SOURCE!!
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Illustration using Conductances
 Write the Node Equations
• KCL At v1

 At The SuperNode
Have V-Constraint
•
v2 − v3 = vA 
 KCL Leaving Supernode

 Now Have 3 Eqns
in 3 Unknowns
• Solve Using Normal Techniques
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Example
SUPERNODE
V3  12
 Find Io
 Known Node Voltages
V2  6V ,V4  12V
 The SuperNode
V-Constraint
V1  V3  12V
 Now KCL at SuperNode
 Or
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Student Exercise
 Lets Turn on the Lights for 5-7 min
 Students are invited to Analyze the
following Ckt
 Determine
• Hint: Use SuperNode
the OutPut
Current, IO
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Numerical Example
 Find Io Using
Nodal Analysis
 Known Voltages for
Sources Connected
to GND
V1  6V , V4  4V
 The Constraint Eqn
V3  V2  12V
 Now KCL at SuperNode
V2  6 V2 V3 V3  (4)





0
 2k
  2k
1
k
2
k
2
k


Engineering-43: Engineering Circuit Analysis
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SUPERNODE
 Now Notice That V2 is
NOT Needed to Find Io
• 2 Eqns in 2 Unknowns
3V2  2V3  2V
 V2  V3  12V  3
and add eqns
-----------------5V3  38V  V3  7.6V
 By Ohm’s Law
IO 
V3
7.6V

 3.8mA
2k 2k
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Complex SuperNode
supernode
 Write the Node Eqns
 Set UP
V2
 Voltage Sources In
Between Nodes And
Possible Supernodes
V3
R5
+
-
R1
• Identify all nodes
• Select a reference
• Label All nodes
 Nodes Connected To
Reference Through A
Voltage Source
R4
R2
V1
+ +
-
V4
V5
R3
R6
 Eqn Bookkeeping:
•
•
•
•
KCL@ V3
KCL@ SuperNode,
2 Constraint Equations
One Known Node
• Choose to Connect V2 & V4
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
R7
Complex SuperNode cont.
 Now KCL at Node-3
V3  V2 V3  V4 V3


0
R4
R5
R7
 Now KCL at Supernode
• Take Care Not to Omit
Any Currents
supernode
V2
Vs2
R1
+
-
R2
V1
Vs1
R4
V3
Vs3
+ -
+
-
R5
V4
V5
R3
R6
V2  V1 V5  V1 V5 V4 V4  V3 V2  V3





0
R1
R2
R3 R6
R5
R4
 Constraints Due to Voltage Sources
V1  VS1
V2  V5  VS 2
V5  V4  VS 3
 5 Equations 5 Unknowns → Have to Sweat Details
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
R7
Dependent Sources
 Circuits With Dependent Sources
Present No Significant Additional
Complexity
 The Dependent Sources Are
Treated As Regular Sources
 As With Dependent CURRENT Sources
Must Add One
Equation For Each
Controlling Variable
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Numerical Example – Dep Isrc
 Find Io by Nodal
Analysis
 Notice V-Source
Connected to the
Reference Node
V1  3V
 KCL At Node-2
V2  V1 V2

 2I x  0
3k
6k
 Controlling Variable
In Terms of
V2
I 
Node Potential x 6k
Engineering-43: Engineering Circuit Analysis
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 Sub Ix into KCL Eqn
V2  V1 V2
V2

2
0
3k
6k
6k
 Mult By 6 kΩ LCD
V2  2V1  0  V2  6V
 Then Io
V1  V2
IO 
 1mA
3k
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Dep V-Source Example
 Find Io by Nodal Analysis
 Notice V-Source
Connected to the
Reference Node
V3  6V
 SuperNode Constraint
V1  V2  2Vx
 Controlling Variable in
Terms of Node Voltage
Vx  V2  V1  3V2
Engineering-43: Engineering Circuit Analysis
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 KCL at SuperNode
 Mult By 12 kΩ LCD
2(V1  6)  V1  2V2  V2  6  0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Dep V-Source Example cont
 Simplify the LCD Eqn
3V1  3V2  18V
and 3V2  V1
 4V1  18V
V1  4.5V
 By Ohm’s Law
V1
9V
3
Io 

 mA
12k 24k 8
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
Current Controlled V-Source
 Find Io
 Supernode Constraint
V2  V1  2kIx
 Controlling Variable in
Terms of Node Voltage
V1
Ix 
2k
 V1  2kIx  V2  2V1
 KCL at SuperNode
 4mA 
V1
V
 2mA  2  0
2k
2k
Engineering-43: Engineering Circuit Analysis
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 Multiply by LCD of 2 kΩ
V1  V2  4[V ]
 Recall  2V1  V2  0
 Then
3V2  8V
 So Finally
IO 
V2 4
 mA
2k 3
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt
WhiteBoard Work
 Let’s Work This
Problem
1K
+
12V
1K
2IX
1K
1K
IO
IX
VO
-
 Find the OutPut
Voltage, VO
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-03-1b_Nodal_Analysis.ppt