Engineering 43
Chp 6.4
RC OpAmps Ckts
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Circuits
 Introduce Two Very
Important Practical
Circuits Based On
Operational Amplifiers
 Recall the OpAmp
 The “Ideal” Model That
we Use
• RO = 0
• Ri = ∞
• Av = ∞
Engineering-43: Engineering Circuit Analysis
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 Consequences of Ideality
• RO = 0  vO = Av(v+−v−)
• Ri = ∞  i+ = i− = 0
• Av = ∞  v+ = v−
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Ckt  Integrator
v+ = 0
 KCL At v- node
 By Ideal OpAmp
• Ri = ∞  i+ = i- = 0
• Av = ∞  v+ = v- = 0
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Integrator cont
 Separating the Variables
and Integrating Yields
the Solution for vo(t)
 By the Ideal OpAmp
Assumptions
 A simple Differential Eqn
Engineering-43: Engineering Circuit Analysis
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 Thus the Output is a
(negative) SCALED
TIME INTEGRAL of the
input Signal
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Ckt  Differentiator
+ vC1 
i2
R1
i1
KVL
v+ = 0
 By Ideal OpAmp
• v- = GND = 0V
• i- = 0
Engineering-43: Engineering Circuit Analysis
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 KCL at v- i1 + i2
 Now the KVL
= i
 v1 + R1i1 + vC1 = 0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Differentiator cont.
R1
i2
i1
1 t
vC t  =  i  x dx
C 
 Recall Ideal OpAmp
Assumptions
 Thus the KVL
t
1
v1 (t ) = R1i1 +
i1 ( x)dx

C1 
• Ri = ∞  i+ = i- = 0
• Av = ∞  v+ = v- = 0
 Taking the Time
Derivative of the above
 Then the KCL
vO
i1 + i2 = i1 +
=0
R2
Engineering-43: Engineering Circuit Analysis
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 Recall the Capacitor
Integral Law
di1
dv1
R1C1
+ i1 = C1
(t )
dt
dt
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Differentiator cont
 Examination of this Eqn
Reveals That if R1 were
ZERO, Then vO would be
Proportional to the TIME
DERIVATIVE of the input
Signal
R1
i1
 In the Previous
Differential Eqn use
KCL to sub vO for i1
• Using
vO
i1 +
=0
R2
dvo
dv1
R1C1
+ vo =  R2C1
(t )
dt
dt
Engineering-43: Engineering Circuit Analysis
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• in Practice An Ideal
Differentiator Amplifies
Electrical Noise And Does
Not Operate
• The Resistor R1 Introduces A
Filtering Action.
– Its Value Is Kept As Small As
Possible To Approximate A
Differentiator
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Aside → Electrical Noise
 ALL electrical signals
are corrupted by
external,
uncontrollable and
often unmeasurable,
signals. These
undesired signals are
referred to as NOISE
 Simple Model For A
Noisy 1V, 60Hz Sinusoid
Corrupted With One
MicroVolt of 1GHz
Interference
Engineering-43: Engineering Circuit Analysis
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y(t ) = sin( 120 t ) + 106 sin( 2 109  t )
Signal
Noise
 The Signal-To-Noise Ratio
SN =
signal amplitude
1V
= 106 =
noise amplitude
V
 Use an Ideal Differentiator
dy
(t ) = 120 cos(120t ) + 2000 cos( 2 109  t )
dt
Signal
Noise
 The SN is Degraded Due
to Hi-Frequency Noise
SN =
signal amplitude
120
3
=
=
noise amplitude
2000 50
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Class Exercise  Ideal Differen.
= 1 k
= 2 F
 Given Input v1(t)
• SAWTOOTH Wave
 Let’s Turn on the Lites for
10 minutes for YOU to
Differentiate
 Given the IDEAL
Differentiator Ckt and
INPUT Signal
 Find vo(t) over 0-10 ms
 Recall the Differentiator
Eqn
dvo
dv1
R1C1
+ vo =  R2C1
(t )
dt
dt
R1 = 0; Ideal ckt
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Differentiator Ex.
= 1 k
= 2 F
 The Slope from 0-5 mS
dv1
10 V
m=
=
dt 5 10 3 s
 For the Ideal Differentiator
 Given Input v1(t)
Engineering-43: Engineering Circuit Analysis
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dv1
vo =  R2C1
(t )
dt
 Units Analysis
V
V
V s
= =
=
A Q
Q
s
Q
F =   F = s
V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Differentiator cont.
= 1 k
= 2 F
dv1 t 
10 V
vo =  R2C1
= 2  10 3 S 
dt
5 10 3 S
20
vo =  V = 4V
: 0  t  5 in mS
5
 A Similar Analysis for 5-10
mS yields the Complete vO
 Derivative Scalar
PreFactor
R2C1 = 1103   2 106 F = 2 103 s
OutPut
InPut
 Apply the Prefactor
Against the INput Signal
Time-Derivative (slope)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Integrator Example
= 0.2 μF
5 k =
 Given Input v1(t)
• SQUARE Wave
Engineering-43: Engineering Circuit Analysis
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 For the Ideal Integrator
t
1
vo (t ) = vo (0) 
vi ( x)dx

R1C2 0
 Units Analysis Again
V
V
V s
= =
=
A Q
Q
s
Q
F =   F = s
V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Integrator Ex. cont.
 0<t<0.1 S
• v1(t) = 20 mV (Const)
0.1
 R1C2vo (t ) =  v1 (t )dt = 20 103V  0.1S = 2mV  S
0
 The Integration
PreFactor
1
1
1
=
=
= 1000S 1
R1C2 5k  0.2F 0.001S
 Next Calculate the
Area Under the Curve
to Determine the
Voltage Level At the
Break Points
Engineering-43: Engineering Circuit Analysis
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 0.1t<0.2 S
• v1(t) = –20 mV (Const)
0.2
 R1C2vo (t ) =  R1C2vo (0.1) +  v1 (t )dt =


0.1
= 2mV  S +  20 103V  0.1S = 0
 Integrate In Similar
Fashion over
• 0.2t<0.3 S
• 0.3t<0.4 S
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
RC OpAmp Integrator Ex. cont.1
 Apply the 1000/S PreFactor and Plot Piece-Wise
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Practical Example
 Simple Circuit Model For a
Dynamic Random Access Memory Cell (DRAM)
 Note How Undesired
Current Leakage is
Modeled as an I-Src
Engineering-43: Engineering Circuit Analysis
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 Also Note the TINY Value
of the Cell-State
Capacitance (50x10-15 F)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Practical Example cont
 During a WRITE Cycle the
Cell Cap is Charged to 3V
for a Logic-1
 The Criteria for a
Logic “1”
• Vcell >1.5 V
 Now Recall that
V = Q/C
• Or in terms of Current
t
1
vC = vC (0) +  iC ( x)dx
C0
Engineering-43: Engineering Circuit Analysis
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• Thus The TIME PERIOD
that the cell can HOLD the
Logic-1 value
Vcell
I leak  t
I leak
= 3
 1.5 
t  1.5V
Ccell
Ccell
1.5(V )  50 1015 ( F )
3
tH =
=
1
.
5

10
s
12
50 10 A
 Now Can Calculate the
DRAM “Refresh Rate”
1
fR =
= 667 Hz
tH
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Practical Example cont.2
 Consider the Cell at the
Beginning of a READ
Operation
Qcell = 3V  50 fF = 150 fCoul
Qout = 1.5V  450 fF = 675 fCoul
Qtotal = 150 fCoul + 675 fCoul = 825 fCoul
 When the Switch is
Connected Have Caps in
Parallel
Ctotal = 50 + 450 = 500 fF
 Then The Output
 Calc the Change in VI/O
at the READ
Engineering-43: Engineering Circuit Analysis
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VI / O
Q 825 fCoul
= =
= 1.65V
C
500 fF
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Design Example
 Design an OpAmp ckt to implement in
HARDWARE this Math Relation
t
v0 = 5 v1  y dy  2v2
0
 Examine
the Reln to
find an
Integrator
Engineering-43: Engineering Circuit Analysis
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Adder
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
t
Design Example
v0 = 5 v1  y dy  2v2
0
 The Proposed
Solution
 The by Ideal
OpAmps &
KCL & KVL &
Superposition
t
v0 = 5 v1  y dy  2v2
0
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
t
Design Example
v0 = 5 v1  y dy  2v2
0
 The Ckt Eqn
 Then the Design
Eqns
R4
R4
5=
; 2=
R1 R2C
R3
 TWO Eqns in
FIVE unknowns
Engineering-43: Engineering Circuit Analysis
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 This means that we,
as ckt designers, get
to PICK 3 values
 For 1st Cut Choose
• C = 20 μF
• R1 = 100 kΩ
• R4 = 20 kΩ
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
t
Design Example
v0 = 5 v1  y dy  2v2
0
 In the Design Eqns
20k
5=
100kR2 20 F
 R2 = 20k
20k
2=
R3
 R3 = 10k
 Then the DESIGN
Engineering-43: Engineering Circuit Analysis
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20μ
20k
20k
100k
10k
 If the voltages are
<10V, then all
currents should be
the in mA range,
which should
prevent over-heating
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
WhiteBoard Work
 Let’s Work These Probs
80k
choose C
such that
vo = 10 v1 t dt
+
Find
Energy
Stored
on Cx
+
8V
60µF
-
24V
Cx
-
Engineering-43: Engineering Circuit Analysis
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Figure PFE-3
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
APPENDIX
IC GROUND
BOUNCE
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
LEARNING EXAMPLE
FLIP CHIP MOUNTING
IC WITH WIREBONDS TO THE OUTSIDE
GOAL: REDUCE INDUCTANCE IN
THE WIRING AND REDUCE THE
“GROUND BOUNCE” EFFECT
Engineering-43: Engineering Circuit Analysis
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A SIMPLE MODEL CAN BE USED TO
DESCRIBE GROUND BOUNCE
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt
MODELING THE GROUND BOUNCE EFFECT
VGB (t ) = Lball
Lball  0.1nH
diG
(t )
dt
40  103 A
m=
40  109 s
IF ALL GATES IN A CHIP ARE CONNECTED TO A SINGLE GROUND THE CURRENT
CAN BE QUITE HIGH AND THE BOUNCE MAY BECOME UNACCEPTABLE
USE SEVERAL GROUND CONNECTIONS (BALLS) AND ALLOCATE A FRACTION OF
THE GATES TO EACH BALL
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06-4_RC_OpAmps.ppt