Digital Design – Datapath Components
Chapter 4 Datapath Components
Digital Design
Datapath Components
I2
1
1
0
2x1
(a) I1
0
I0
1
0
(b)
1
0
D
D
D
D
Q
Q
Q
Q
Q2
load = 0
Q3
Q1
I3
I2
1
1
0
2x1
I1
0
I0
1
0
load
I3
I2
I1
I0
Q3
Q2
Q1
Q0
Q0
1
0
load = 1
load
I3
I3
I2
1
1
0
2x1
I1
0
I0
1
0
1
0
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Q3
Q2
Q1
Q0
(c)
Q3
Q2
Q1
Q0
Figure 4.1 4-bit parallel load register: (a) internal design, (b) block symbol, and
(c) paths when load=0 and load=1.
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Digital Design
Datapath Components
Scale
2.2 pounds
Present weight Save
Weight Sampler
b
I3 I2I1I0
load
Q3Q2Q1Q0
3.1 pounds
Saved weight
Figure 4.2 Weight sampler implemented using a 4-bit parallel load register.
3
Digital Design
Datapath Components
a4 a3a2 a1 a0
t4
t3
t2
t1
t0
osc
timer
clk
I4
I3
I2
I1
I0
Q4
Q3
Q2
Q1
Q0
ld Ra
b4 b3 b2b1 b0
I4
I3
I2
I1
I0
Q4
Q3
Q2
Q1
Q0
ld Rb
c4c3c2c1c0
I4
I3
I2
I1
I0
ld
Q4
Q3
Q2
Q1
Q0
Rc
C
new line
TemperatureHistoryStorage
Figure 4.3 Internal design of the TemperatureHistoryStorage component, using
parallel load registers.
4
Digital Design
C
8
d0
load
reg0
T
2x4
d1
a0
8
load
reg1
8-bit
4x1
i0
a1
8
i1
d
d2
load
reg2
e d3
load reg3
D
8
I
8
load
i0
A
i1
To the abovemirror display
From the car’s
central computer
Datapath Components
i2
M
s1
8
s0
i3
x
y
Figure 4.4 Above-mirror display design.
5
Digital Design
Datapath Components
LED
lit LED
1
0
1
0
0
0
1
0
Q
R7 R6 R5 R4 R3 R2 R1 R0
8
d7 d6 d5 d4 d3 d2 d1 d0
e
i2 i1i0 3x8 decoder
D
microprocessor
I
R0
load 10100010
from from
microprocessor decoder
D
10100010
010000101 10100010
010000101 10100010
010000101 10100010
010000101
i2,i1,i0
000 (R0)
001 (R1)
011 (R3)
101 (R5)
111 (R7)
010 (R2)
100 (R4)
110 (R6)
e
clk
Figure 4.5 An electronic checkerboard.
6
Digital Design
Datapath Components
LED
lit LED
R7 R6 R5 R4 R3 R2 R1 R0
10100010 10100010 10100010 10100010
010000101 010000101 010000101 010000101
Figure 4.6 Checkerboard after loading registers for initial checker positions.
7
Digital Design
Datapath Components
1 1 0 1
Register contents
before shift right
0 1 1 0
Register contents
after shift right
shr_in
0
Figure 4.7 Right shift example: sample contents before and after a right shift, and
bit-by-bit view of the shift.
8
Digital Design
Datapath Components
shr
1 0
2x1
D
1
0
D
1
0
D
1
0
D
shr=1
(a)
shr_in
1
0
2x1
1
0
1
0
1
0
D
D
D
D
Q
Q
Q
Q
Q3
Q2
Q1
Q0
(c)
Q
Q3
Q
Q2
Q
Q1
Q
Q0
shr_in
shr
Q3
Q2
Q1 Q0
Figure 4.8 Shift register: (a) implementation, (b) paths when shr=1, and (c)
register symbol.
9
Digital Design
Datapath Components
1101
Register contents
before rotate right
1110
Register contents
after rotate right
Figure 4.9 Right rotate example: register contents before and after the rotate,
and bit-by-bit view of the rotate operation.
10
Digital Design
Datapath Components
Note: this line is 1 bit, rather than 8 bits like before
x y
c
d0
shr_in
shr
reg0
T
2x4
a0
i0
a1
i1
8
d1
shr_in
shr
reg1
d2
shr_in
shr
reg2
A
8
shr_in
shr
reg3
4x1
i1
d
D
8
I
8
e d3
i0 s1s0
i2
M
shift
8
i3
Figure 4.10 Above-mirror display design using shift registers to reduce the
number of lines coming from the car’s computer.
11
Digital Design
Datapath Components
shr_in I3
0
s1 3 2 1 0
4x1
s0
I1
I2
0
I0
0
0
32 10
32 10
3 210
D
D
D
D
Q
Q
Q
Q
Q3
shr_in I3 I2 I1 I0
s1
s0
Q3 Q2 Q1 Q0
Q2
Q1
s1
0
0
1
1
s0
0
1
0
1
Q0
Operation
Maintain present value
Parallel load
Shift right
Shift left
Figure 4.12 4-bit register with parallel load and shift right operations.
12
Digital Design
Datapath Components
ld
0
0
0
0
1
1
1
1
shr
0
0
1
1
0
0
1
1
shl
0
1
0
1
0
1
0
1
Operation
Maintain present value
Shift left
Shift right
Shift right -- shr has priority over shl
Parallel load
Parallel load -- ld has priority
Parallel load -- ld has priority
Parallel load -- ld has priority
shr_in
ld combishr national
shl circuit
I3 I2 I1 I0
shr_in I3 I2 I1 I0
s1
shl_in shl_in
s0
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Figure 4.13 A small combinational circuit maps the control inputs ld, shr, and shl
to the mux select inputs s1 and s0.
13
Digital Design
Datapath Components
Inputs
ld shr
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
shl
0
1
0
1
0
1
0
1
Outputs
s1 s0
0 0
1 1
1 0
1 0
0 1
0 1
0 1
0 1
Note
Operation
Maintain value
Shift left
Shift right
Shift right
Parallel load
Parallel load
Parallel load
Parallel load
ld
0
0
0
1
shr
0
0
1
X
shl
0
1
X
X
Operation
Maintain value
Shift left
Shift right
Parallel load
Figure 4.14 Truth table describing operations of a register with left/right shift and
parallel load along with the mapping of the register control inputs to the internal
4x1 mux select lines (left), and a compact version of the operation table (right).
14
Digital Design
Datapath Components
Step
Description
1
Determine
mux size
Count the number of operations (don’t forget the maintain present value
operation!) and add in front of each flip-flop a mux with at least that
number of inputs.
2
Create mux
operation
table
Create an operation table defining the desired operation for each
possible value of the mux select lines.
Connect mux
3
inputs
4
Map control
lines
For each operation, connect the corresponding mux data input to the
appropriate external input or flip-flop output (possibly passing through
some logic) to achieve the desired operation.
Create a truth table that maps external control lines to the internal mux
select lines, with appropriate priorities, and then design the logic to
achieve that mapping
Table 4.1 Four-step process for designing a multifunction register.
15
Digital Design
Datapath Components
Step 1: Determine mux size
There are 5 operations -- load, shift left, synchronous clear, synchronous set, and
maintain present value.
Step 2: Create operation table
s2
0
0
0
0
1
1
1
1
s1
0
0
1
1
0
0
1
1
s0
0
1
0
1
0
1
0
1
Operation
Maintain present value
Parallel load
Shift left
Synchronous clear
Synchronous set
Maintain present value
Maintain present value
Maintain present value
Example 4.6 Register with load, shift, and synchronous clear and set/
16
Digital Design
Datapath Components
Step 3: Connect mux inputs
1 0
In
from Qn-1
s2
s1
s0
7 6 5 43 210
D
Q
Qn
Step 4: Map control lines
Inputs
clr set
0
0
0
0
0
0
0
1
1
X
ld
0
0
1
X
X
Outputs
shl s2 s1 s0
0
0 0 0
1
0 1 0
X
0 0 1
X
1 0 0
X
0 1 1
Operation
Maintain present value
Shift left
Parallel load
Set to all 1s
Clear to all 0s
s2 = clr’*set
s1 = clr’*set’*ld’*shl + clr
s0 = clr’*set’*ld + clr
Example 4.6 Register with load, shift, and synchronous clear and set.
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Digital Design
Datapath Components
Inputs
a1 a0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
c
s1
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
0
1
1
s0
0
1
1
1
1
0
1
0
1
1
0
1
1
0
1
0
A 2-bit adder, which adds two 2-bit numbers, could be designed by starting with
the following truth table.
18
Digital Design
Datapath Components
Transistors
10000
8000
6000
4000
2000
0
1
2
3
4
N
5
6
7
8
Figure 4.19 Why large adders aren’t built using standard two-level combinational
logic -- notice the exponential growth. How many transistors would a 32-bit adder
require?
19
Digital Design
Datapath Components
0
1111
+0110
10
1111
+0110
11
1111
+0110
1
1111
+0110
---1
---01
---101
---10101
Figure 4.17 Adding two binary numbers by hand, column by column.
20
Digital Design
Datapath Components
+
1
1
0
A: 1
1
1
1
B: 0
1
1
0
b a ci
co s
1
0
b a ci
co s
1
b a ci
co s
0
b a
co s
1
SUM
Figure 4.18 Using combinational components to add two binary numbers column
by column.
21
Digital Design
Datapath Components
Half-adder Truth Table
Inputs
a
b
0
0
0
1
1
0
1
1
a
Outputs
co
s
0
0
0
1
0
1
1
0
b
a
b
Half-adder
(HA)
co s
co
s
Figure 4.19 Half-adder circuit (left) and block symbol (right).
22
Digital Design
Datapath Components
Full-adder Truth Table
Inputs
a
b
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
a b
Outputs
co
s
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
ci
0
1
0
1
0
1
0
1
ci
a b ci
Full
adder
(FA)
co s
co
s
Figure 4.20 Full-adder circuit (left) and block symbol (right).
23
Digital Design
Datapath Components
a3 b3
a2 b2
a b ci
FA
co s
co
s3
a1 b1
a0 b0
a b ci
FA
co s
a b ci
FA
co s
s2
s1
a b
HA
co s
a3a2a1a0 b3b2b1b0
4-bit adder
co s3s2s1s0
s0
Figure 4.21 4-bit adder: carry-ripple implementation with 3 full-adders and 1 halfadder (left), and block symbol (right).
24
Digital Design
Datapath Components
a3 b3
a2 b2
a b ci
FA
co s
co
s3
a1 b1
a0 b0 ci
a b ci
FA
co s
a b ci
FA
co s
a b ci
FA
co s
s2
s1
s0
a3a2a1a0 b3b2b1b0
4-bit adder ci
co s3s2s1s0
Figure 4.22 4-bit adder: carry-ripple implementation with 4 full-adders, with a
carry-in input (left), and block symbol (right).
25
Digital Design
Datapath Components
0 0
0
1
0
0
1
0
0
a b ci
a b ci
a b ci
FA
FA
FA
co s
co s
0
1
co s
0
1
0
0
0 0
0
a b ci
0
0
a b ci
1
0
1
a b ci
FA
FA
FA
co s
co s
0
1
co s
1
0
0
0
0 0
0
a b ci
FA
co s
0
1 0
1
1 0
a b ci
FA
co s
1
co s
1
0
1
a b ci
FA
co s
1
1
a b ci
FA
0
0 0
0
1
1 0
1 1
0
a
b ci
FA
co s
1
0
1 0
Output after 2 ns (1 FA delay)
0
a b ci
FA
(b)
co s
1
Output after 4 ns (2 FA delays)
0
1
1
0
a b ci
FA
(c)
co s
1
1
a b ci
FA
a b ci
FA
co s
1
co s
1
0
0
(a)
1 1
0
1
0111+0001
Output after 6 ns (3 FA delays)
0
1 1
a
0
b ci
FA
(d)
co s
1
0
Output after 8 ns (4 FA delays)
Figure 4.23 Example of adding 0111+0001 using a 4-bit carry-ripple adder.
26
Digital Design
Datapath Components
a3a2a1a0 b3b2b1b0
4-bit adder ci
co s3s2s1s0
co
s7s6s5s4
a3a2a1a0 b3b2b1b0
4-bit adder ci
co s3s2s1s0
a7..a0
b7..b0
8-bit adder
co
s7..s0
ci
s3s2s1s0
Figure 4.24 8-bit carry-ripple adder built from two 4-bit carry-ripple adders (left);
block symbol (right).
27
Digital Design
Datapath Components
1
0
DIP switches
a7..a0
b7..b0 ci
8-bit carry-ripple adder
co
s7..s0
0
CALC
LEDs
Figure 4.25 8-bit DIP-switch-based adding calculator.The addition 2+3=5 is
shown.
28
Digital Design
Datapath Components
1
0
DIP switches
a7..a0
b7..b0 ci
8-bit adder
co
s7..s0
e
clk
ld
8-bit register
0
CALC
LEDs
Figure 4.26 8-bit DIP-switch-based adding calculator, using a register to block
spurious LED outputs.
29
Digital Design
Datapath Components
weight
sensor
7 01
2
6
5 4 3
0 0000
a7..a0
b7..b0
8-bit adder
co
s7..s0
clk
1
ld
display register
ci
0
Weight
Adjuster
to display
Figure 4.27 Compensating scale: the dial outputs a number from 0 to 7 (000 to
111), which gets added to the sensed weight and then displayed.
30
Digital Design
Datapath Components
(a)
(b)
i3 i2 i1 i0
(c)
i3 i2 i1 i0
in
01
01
01
01
q3q2q1q0
q3 q2 q1 q0
<<1
i3 i2 i1 i0
in
sh
inR
shL
shR
inL
20 1 20 1 20 1 20 1
s0
s1
q3 q2 q1 q0
Figure 4.28 Combinational shifters: (a) left shifter with block symbol shown at
bottom, (b) left shift or pass component, (c) left/right shift or pass component.
31
Digital Design
Datapath Components
Example 4.9 Approximate Celsius to Fahrenheit converter.
We want to convert that temperature to Fahrenheit, again using 8 bits. The equation for
converting is:
F = C*9/5 + 32
Let’s assume that we are not concerned about accuracy, so we’ll replace the equation by a
simpler one:
F = C*2 + 32
C
8
<<1
0
10000000
8-bit adder
8
F
Figure 4.29 Celsius to Fahrenheit converter.
32
Digital Design
Datapath Components
T
clk
Ra
Rc
Rb
Rd
ld
+
+
+
0
>>2
Ravg
Tavg
Figure 4.30 Temperature averager using a right-shift-by-2 to divide by 4.
33
Digital Design
Datapath Components
8
x
sh <<4 in
0
y
sh <<2 in
0
z
sh <<1 in
0
8
Q
Figure 4.31 8-bit barrel shifter.
34
Digital Design
Datapath Components
a3
b3 a2
b2 a1
b1 a0
b0
a3 a2 a1 a0
b3b2 b1 b0
4-bit equality comparator
eq
eq
Figure 4.32 Equality comparator: internal design (left), block symbol (right).
35
Digital Design
Datapath Components
b3
a3
Igt
Ieq
Ilt
a
in_gt
in_eq
in_lt
a2
b
out_gt
out_eq
out_lt
a
in_gt
in_eq
in_lt
Stage3
0
1
0
b2
b
out_gt
out_eq
out_lt
Stage2
Igt
Ieq
Ilt
a3 a2 a1 a0
a1
b1
a
b
in_gt out_gt
inA=B out_eq
in_lt
out_lt
a0
a
in_gt
in_eq
in_lt
Stage1
b3 b2 b1b0
4-bit magnitude comparator
b0
b
out_gt
out_eq
out_lt
AgtB
AeqB
AltB
Stage0
AgtB
AeqB
AltB
Figure 4.33 4-bit magnitude comparator: internal design using identical
components in each stage (top), and block symbol (bottom).
36
Digital Design
Datapath Components
1 =
a3
a
Igt 0 in_gt
Ieq 1 in_eq
Ilt 0 in_lt
1
0
0
1
0
1
1
b3
a2
b2
a1
b1
a0
b0
b
a
0
out_gt
in_gt
out_eq 1 in_eq
out_lt 0 in_lt
Stage3
b
out_gt
out_eq
out_lt
Stage2
1
1
0 = 0
a3
b3
a2
a
b
out_gt
out_eq
out_lt
Igt 0 in_gt
Ieq 1 in_eq
Ilt 0 in_lt
Stage3
a
in_gt
in_eq
in_lt
b2
a
b
in_gt out_gt
inA=B out_eq
in_lt
out_lt
Stage1
b
out_gt
out_eq
out_lt
0
1
1
a1
b1
a0
b0
Stage1
AgtB
AeqB
AltB
Stage0
1
b
a
b
0
out_gt
in_gt out_gt
out_eq 1 inA=B out_eq
out_lt 0 in_lt
out_lt
Stage2
a
in_gt
in_eq
in_lt
a
in_gt
in_eq
in_lt
b
out_gt
out_eq
out_lt
AgtB
AeqB
AltB
Stage0
Figure 4.34 The “rippling” within a magnitude comparator.
37
Digital Design
Datapath Components
Igt 0
Ieq 1
Ilt 0
1
1
0
0
1 > 0
1
1
a3
b3
a2
b2
a1
a0
b0
a
in_gt
in_eq
in_lt
b
out_gt
out_eq
out_lt
a
in_gt
in_eq
in_lt
Stage3
Igt 0
Ieq 1
Ilt 0
b
out_gt
out_eq
out_lt
Stage2
b1
a
b
a
in_gt out_gt 1 in_gt
inA=B out_eq 0 in_eq
in_lt
out_lt 0 in_lt
Stage1
b
out_gt
out_eq
out_lt
Stage0
1
1
0
0
1
0
1
1
a3
b3
a2
b2
a1
b1
a0
b0
a
in_gt
in_eq
in_lt
b
out_gt
out_eq
out_lt
Stage3
a
in_gt
in_eq
in_lt
b
out_gt
out_eq
out_lt
Stage2
a
b
in_gt out_gt
inA=B out_eq
in_lt
out_lt
Stage1
AgtB
AeqB
AltB
a
in_gt
in_eq
in_lt
b
out_gt 1 AgtB
out_eq 0 AeqB
out_lt 0 AltB
Stage0
Figure 4.34 The “rippling” within a magnitude comparator (cont.)
38
Digital Design
Datapath Components
MIN
B
A
8
0
1
0
8
Igt
AgtB
A
B
Ieq
AeqB
Ilt 8-bit magnitude comparator AltB
8
s
I1
I0
8-bit
2x1 mux
C
8
A B
Min
C
8
Figure 4.35 A combinational component to compute the minimum of two
numbers: internal design using a magnitude comparator (left), and block symbol
(right).
39
Digital Design
Datapath Components
4-bit up-counter
cnt
4-bit up counter
tc
C
4
cnt
ld 4-bit register
tc
Figure 4.36 4-bit upcounter block symbol.
4
C
+1
Figure 4.37 4-bit upcounter internal design.
carries: 0 1 1
00 1 1
unused +
1
0 0 100
Figure 4.38 Adding 1 to a
binary number requires
only 2-bits per column.
40
Digital Design
a3
a1
a2
1
a0
a b
HA
co s
a b
HA
co s
a b
HA
co s
co s3
s2
s1
a b
HA
co s
s0
Incrementer (+1)
Datapath Components
a3a2a1 a0
+1
cos3s2s1 s0
Figure 4.39 4-bit incrementer internal design (left) and block symbol (right).
41
Digital Design
Datapath Components
mode
clk
cnt
2-bit up counter
tc c1c0
xy
Figure 4.40 Sequencer for xy inputs of
above-mirror display.
1
cnt 8-bit up-counter
tc
C
osc
(unused)
(256 Hz) p
(1 Hz)
Figure 4.41 Clock divider.
42
Digital Design
Datapath Components
4-bit down counter
cnt ld
4-bit register
tc
4
C
-1
Figure 4.42 4-bit down-counter design.
43
Digital Design
Datapath Components
4-bit up/down-counter
dir
clr
cnt
1 2x1 0
clr
ld 4-bit register
4
-1
+1
1 2x1 0
C
tc
Figure 4.43 4-bit up/down-counter design.
44
Digital Design
Datapath Components
1 cnt 3-bit up-counter
clk
tc
c2 c1 c0
(1 Hz)
unused
c b a
3x8 dcd
d7 d6 d5 d4 d3 d2 d1 d0
lights
Figure 4.44 Light sequencer.
45
Digital Design
Datapath Components
L 4
ld
cnt
1 2x1 0
ld 4-bit register
tc
4
C
+1
Figure 4.45 Internal design of a 4-bit up-counter with load.
46
Digital Design
Datapath Components
1
clk
1000
L
ld
cnt 4-bit down-counter
tc
C
(unused)
Figure 4.46 A counter setup that pulses tc every 9 cycles.
47
Digital Design
Datapath Components
countdown
reset
59
0
8
L
ld
cnt
clk
(1 Hz)
c0
c1
c2
c3
c4
c5
c6
c7
8-bit
downctr tc
i0
i1
i2
i3
i4
i5
d0
d1
d2
d3
d58
d59
d60
d61
6x64 d62
dcd d63
Happy
New Year!
1
2
3
58
59
fireworks
Figure 4.47 Happy New Year countdown system using a down-counter.
48
Digital Design
Datapath Components
clr
cnt 6-bit up-counter
C
tc
osc
p
(60 Hz)
1
(1 Hz)
Figure 4.48 Clock divider.
49
Digital Design
Datapath Components
vehicle
b
Speed
a Measurer
a’
S0
clr=1
s
b’
a
S1
b
S2
cnt=1 cnt=0
(compute time and
output speed)
clr
cnt
C
16
Figure 4.49 Measuring vehicle speeds in a highway speed measuring system.
50
Digital Design
Datapath Components
0110
(the top number is called the multiplicand)
0011
(the bottom number is called the multiplier)
----
(each row below is called a partial product)
0110
(because the rightmost bit of the multiplier is 1, and 0110*1=0110)
0110
0000
+0000
(because the second bit of the multiplier is 1, and 0110*1=0110)
(because the third bit of the multiplier is 0, and 0110*0=0000)
(because the leftmost bit of the multiplier is 0, and 0110*0=0000)
-------00010010
(the product is the sum of all the partial products: 18, which is
6*3)
Multiplying two 4-bit binary numbers 0110 and 0011 by hand.
51
Digital Design
Datapath Components
a3
a2
a1
a0
pp1
b0
pp2
b1
pp3
b2
pp4
b3
A B
*
P
Block symbol
0
0
+ (5-bit)
00
+ (6-bit)
000
+ (7-bit)
p7..p0
Figure 4.50 Internal design of a 4-bit by 4-bit array-style multiplier.
52
Digital Design
Datapath Components
1st column
0
1 0 1 10
-0 1 1 1
1
a3 b3
a2 b2
a b wi
FS
wo s
wo
2nd column
0 1 10
1 10 1 0
-0 1 1 1
1 1
s3
3rd column
0 1
1 10 1 0
-0 1 1 1
0 1 1
a1 b1
4th column
0 1
1 10 1 0
-0 1 1 1
0 0 1 1
a0 b0 wi
a b wi
FS
wo s
a b wi
FS
wo s
a b wi
FS
wo s
s2
s1
s0
a3a2a1a0 b3b2b1b0
4-bit subtractor wi
wo s3s2s1s0
Figure 4.51 4-bit subtractor: subtraction “by hand” example (top); borrow-ripple
implementation with four full-subtractors, with a borrow-in input (bottom left),
and block symbol (bottom right).
53
Digital Design
Datapath Components
1
0
DIP switches
A
B ci 0
8-bit adder
co S
1
0
f
e
clk
A
B wi 0
8-bit subtractor
wo S
0 2x1 1
ld
8-bit register
CALC
LEDs
Figure 4.52 8-bit DIP-switch-based adding/subtracting calculator, using an input f
to select between addition and subtraction.
54
Digital Design
Datapath Components
C = 255 - R
M = 255 - G
Y = 255 - B
RGBtoCMY
255
R 8
G
B
255 8 255 8
C 8
M 8
Y 8
Figure 4.54 RGB to CMY converter.
Example 4.19 Color space converter -- RGB to CMYK.
55
Digital Design
Datapath Components
8
G
8
B
8
RGBtoCMYK
R
R G B
RGBtoCMY
C M Y
8
8
8
MIN
8
K = Minimum(C, M, Y)
C2 = C - K
M2 = M - K
Y2 = Y - K
MIN
8
C2
8
M2
8
8
Y2
K
Figure 4.55 RGB to CMY converter.
Example 4.19 Color space converter -- RGB to CMYK.
56
Digital Design
Datapath Components
1
2
3
4
5
6
7
8
9
9
8
7
6
5
4
3
2
1
0
10
10
4
6
7
0
-4
10
+6
3
20
13
13
3
7-4=3
7+6=13 -->3
Adding the complement results in an answer
exactly 10 too much -- dropping the tens column gives
the right answer.
Figure 4.56 Subtracting by adding.
57
Digital Design
Datapath Components
A
B
N-bit
1
A B
Adder cin
S
Figure 4.57 Two’s complement
subtractor built with an adder.
B
A
b7
b6
sub
0 1
N-bit 2x1
A
AdderBcin
S
sub
...
adder’s B inputs
Figure 4.58 Two’s complement adder/subtractor
(left); alternative circuit for B (right).
58
Digital Design
Datapath Components
1
0
1
0
DIP switches
f
e
clk
A
B
sub 8-bit adder/subtractor
S
ld
8-bit register
CALC
LEDs
Figure 4.59 8-bit DIP-switch-based adding/subtracting calculator, using an
adder/subtractor and two’s complement number representation.
59
Digital Design
Datapath Components
Inputs
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
Operation
S
S
S
S
S
S
S
S
=
=
=
=
=
=
=
=
A+B
A-B
A+1
A
A AND B (bitwise AND)
A OR B (bitwise OR)
A XOR B (bitwise XOR)
NOT A (bitwise complement)
Sample output if
A=00001111,
B=00000101
y
S=00010100
S=00001010
S=00010000
S=00001111
S=00000101
S=00001111
S=00001010
S=11110000
Table 4.2 Desired calculator operations.
60
Digital Design
Datapath Components
1
0
DIP switches
8
A
+
8
1 0
x
y
z
e
clk
8
B
-
+1
AND OR XOR NOT
8
8 8 8 8
88
What a
waste.
0 1 2 3 4 567
s2
A
lot
of
wires.
s1 8-bit 8x1
s0
ld
8-bit register
CALC
LEDs
Figure 4.60 8-bit DIP-switch-based multi-function calculator, using separate
components for each function.
61
Digital Design
Datapath Components
A
x
y
z
B
a7 b7
a6 b6
a0 b0
AL-extender
AL-extender
IA
IB
Adder cin
IS
x
y
z
...
abext
abext
ia7 ib7 ia6 ib6
ALU
abext
cinext
ia0 ib0
cin
S
Figure 4.61 ALU design based on a single adder, with an arithmetic/logic
extender.
62
Digital Design
Datapath Components
1
0
DIP switches
8
8
A
x
y
z
e
clk
x
y
z
ld
B
B
A
ALU
S
8-bit register
CALC
LEDs
Figure 4.62 8-bit DIP-switch-based multi-function calculator, using an ALU.
63
Digital Design
C
32
load
d0
4x16
reg0
i0
too much
fanout
32-bit
16x1
...
i3-i0
huge mux
32
d
To the abovemirror display
From the car’s
central computer
Datapath Components
D
...
congestion
d15
e
load
load
reg15
32
s3-s0
i15
Figure 4.63 Above-mirror display design, assuming 16 32-bit registers.
64
Digital Design
Datapath Components
32
4
32
W_data
R_data
W_addr
R_addr
W_en
4
R_en
16x32
register file
Figure 4.64 16x32 register file block symbol.
65
Digital Design
Datapath Components
bus
32
W_data
d0
load
reg0
W_addr
R_data
d0
2x4
2x4
d1
driver
32
load
reg1
d1
i0
i1
i0
i1
d2
write
decoder
load
reg2
d2
e d3
load
reg3
d3 e
R_addr
R_en
W_en
4x32 register file
Figure 4.65 One possible internal design of a 4x32 register file.
66
Digital Design
C
32
WA
load
4
32
W_data
R_data
W_addr
R_addr
W_en
R_en
16x32
register file
D
4
1
To the abovemirror display
From the car’s
central computer
Datapath Components
RA
Figure 4.66 Above-mirror display design, using a register file.
67
Digital Design
Datapath Components
Transducer
Beamformer
Digital Signal
Scan
Processor
Converter
Monitor
Figure 4.68 Basic components of an ultrasound machine.
68
Digital Design
Datapath Components
2
1
(b)
2
3
(c)
Transducers
1
2
Transducers
(a)
X
Transducers
sound 1
wave
Transducers
focal
point
X
Both waves reach the focal
point at the same time
focal
2
point
X 3
X
(d)
Figure 4.69 Focusing sound at a particular point using beamforming:
(a)
(b)
(c)
(d)
first time step -- only the botton transducer generates sound
second time step -- the top transducer now generates sound too
third time step -- the two sound waves add at the focal point
an illustration showing that the top transducer is two time steps away from the
focal point, while the bottom transducer is three time steps away, meaning the
top transducer should generate sound one time step later than the bottom
transducer
69
Digital Design
Datapath Components
Transducers
focal X
point
(a)
strong
result
X
X
(b)
delay 1
time-step
(c)
(d)
+
result without
the delay
Figure 4.70 Listening to sound from a particular point using beamforming
(a)
(b)
(c)
(d)
first time step
second time step -- the top transducer has heard the sound first
third time step -- the bottom transducer hears the sound at this time,
delaying the top transducer by one time step results in the waves from the focal
point adding, amplifying the sound.
70
Digital Design
Datapath Components
Transducers
s d start_out
o
delay_out
Out ld
Delay
DSP
s d
o
dcd
Out ld
addr
Delay
en
Figure 4.71 Transducer output delay circuits
for two channels.
o
tc cnt L
ld
down
counter
C
OutDelay
d
ld
Figure 4.72 OutDelay circuit.
71
Digital Design
Datapath Components
s
d
Out ld
o
start_out
delay_out
d
ld
reg
Delay
delay_echo
td
reg
Figure 4.73 Transducer output and echo
delay circuits for one channel.
t
reg
t
Echo td t_delayed to
adders
Delay
reg
d
ld
4x1
N
EchoDelay
Figure 4.74 EchoDelay circuit.
72
Digital Design
Datapath Components
A B C DE F GH
+
AB C D
+
+
E F GH
+
+
+
+
+
+
3-adder +
delay
S
+
+
+
7-adder
delay
+
S
Figure 4.75 Adding many numbers: linearly (left), and using an adder tree (right);
note that both methods use seven adders.
73
Digital Design
Datapath Components
s
d
Out ld
o
Delay
start_out
delay_out
reg- d
ister ld
N
d
t
ld
Echo td
Delay
to
* adders
Figure 4.76 Channel extended with a multiplier.
74