Enabling Technologies for
Reconfigurable Computing
November 21, 2001, Tampere, Finland
Reiner Hartenstein
University of
Kaiserslautern
Enabling Technologies for
Reconfigurable Computing
Part 3:
Resources for RC
Wednesday, November 21, 14.00 – 15.30 hrs.
Schedule
Xputer Lab
University of Kaiserslautern
time
slot
08.30 – 10.00
Reconfigurable Computing (RC)
10.00 – 10.30
coffee break
10.30 – 12.00
Stream-based Computing for RC
12.00 – 14.00
lunch break
14.00 – 15.30
Resources for RC
15.30 – 16.00
coffee break
16.00 – 17.30
FPGAs: recent developments
© 2001, reiner@hartenstein.de
2
http://www.fpl.uni-kl.de
>> Configware Industry
Xputer Lab
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Xputer architecture and circuitry
http://www.uni-kl.de
© 2001, reiner@hartenstein.de
3
http://www.fpl.uni-kl.de
Xputer Lab
Configware heading for mainstream
University of Kaiserslautern
• Configware market taking off for mainstream
• FPGA-based designs more complex, even SoC
• No design productivity and quality without good
configware libraries (soft IP cores) from various
application areas.
• Growing no. of independent configware houses
(soft IP core vendors) and design services
• AllianceCORE & Reference Design Alliance
• Currently the top FPGA vendors are the key
innovators and meet most configware demand.
© 2001, reiner@hartenstein.de
4
http://www.fpl.uni-kl.de
OS for PLDs
Xputer Lab
University of Kaiserslautern
• separate EDA software market, comparable
to the compiler / OS market in computers,
• Cadence, Mentor, Synopsys just jumped in.
• < 5% Xilinx / Altera income from EDA SW
© 2001, reiner@hartenstein.de
5
http://www.fpl.uni-kl.de
Xilinx Alliances
Xputer Lab
University of Kaiserslautern
• The Software
AllianceEDA Program
• ... Xilinx Inc.'s
Foundation...
• free WebPACK
downloadable tool
palette
© 2001, reiner@hartenstein.de
• The Xilinx XtremeDSP
Initiative (with Mentor
Graphics)
• MathWorks / Xilinx
Alliance.
• The Wind River / Xilinx
alliance
6
•#
http://www.fpl.uni-kl.de
The Software Alliance EDA Program
Xputer Lab
University of Kaiserslautern
provides a wide
selection of EDA tools
helps leading EDA
vendors to integrate
Xilinx Alliance software
tightly into their tools
© 2001, reiner@hartenstein.de
Acugen Software,
Agilent
EEsof EDA,
Aldec,
Aptix,
Auspy Development,
Cadence,
Celoxica,
Dolphin Integration,
Elanix,
Exemplar,
Flynn Systems,
Hyperlynx,
7
IKOS Systems,
Innoveda,
Mentor
Graphics,
MiroTech,
Model Technoloy,
Protel International,
Simucad,
SynaptiCAD,
Synopsys,
Synplicity,
Translogic,
Virtual Computer Corporation.
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
The Xilinx AllianceCORE program
a cooperation between Xilinx and third-party
core developers, to produce a broad selection
of industry-standard solutions for use in
Xilinx platforms. - Partners are:
Amphion Semiconductor, Ltd.
ARC Cores
CAST, Inc.
DELTATEC
Derivation Systems, Inc.
Dolphin Integration (Grenoble)
Eureka Technology Inc.
Frontier Design Inc.
GV & Associates, Inc.
inSilicon Corporation
iCODING Technology Inc.
Loarant Corporation
Mindspeed Technologies
- A Conexant Business
(formerly Applied Telecom) |
© 2001, reiner@hartenstein.de
MemecCore
Mentor Graphics
Inventra
NewLogic Technologies, Inc. (Europe)
NMI Electronics
Paxonet Communications, Inc.
Perigee, LLC
Rapid Prototypes Inc.
sci-worx GmbH (Hannover, Germany)
SysOnChip
TILAB (Telecom Italia Lab)
VAutomation
Virtual IP Group, Inc.
XYLON.
8
http://www.fpl.uni-kl.de
Xputer Lab
The Xilinx Reference Design Alliance Program
University of Kaiserslautern
The Xilinx Reference Design Alliance Program helps
the development of multi-component reference
designs that incorporate Xilinx devices and other
semiconductors.
The designs are fully functional, but no warranties,
no liability. Partners are:.
ADI Engineering
Innovative Integration
© 2001, reiner@hartenstein.de
JK microsystems, Inc.
LYR Technologies
NetLogic Microsystems
9
http://www.fpl.uni-kl.de
Xputer Lab
The Xilinx University Program
University of Kaiserslautern
The Xilinx University Program provides
•
•
•
•
•
•
•
Xilinx Student Edition Software,
Professor Workshops,
a Xilinx University User Group,
Presentation Materials and Lab Files,
Course Examples,
Research,
Books, etc.
© 2001, reiner@hartenstein.de
10
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Altera offers over a hundred IP
cores like, for example:
Altera offers over a
hundred IP cores (1)
• modulator,
• synchronizer,
• DDR SDRAM controller,
• Hadamar transform,
• interrupt controller,
• Real86 16 bit microprocessor,
• floating point,
• FIR filter,
• discrete cosine,
• ATM cell processor,
• and many others.
• controller,
• UART,
• microprocessor,
• decoder,
• bus control,
• USB controller,
• PCI bus interface,
• viterbi controller,
• fast Ethernet
• MAC receiver or transmitter,
© 2001, reiner@hartenstein.de
11
http://www.fpl.uni-kl.de
Altera offers over a
hundred IP cores (2)
Xputer Lab
University of Kaiserslautern
from Altera |
AMIRIX Systems, Inc.
Amphion Semiconductor, Ltd.
Arasan Chip Systems, Inc.
CAST, Inc.
Digital Core Design
Eureka Technology Inc.
HammerCores
Innocor
Ktech Telecommunications, Inc.
Lexra Computing Engines
Mentor Graphics - Inventra
© 2001, reiner@hartenstein.de
12
Modelware
Ncomm, Inc.
NewLogic Technologies
Northwest Logic
Nova Engineering, Inc.
Palmchip Corporation
Paxonet Communications
PLD Applications
Sciworx
Simple Silicon
Tensilica
TurboConcept.
http://www.fpl.uni-kl.de
Altera IP core design services
Xputer Lab
University of Kaiserslautern
Altera IP core design
services are available
from:
• Northwest Logic
© 2001, reiner@hartenstein.de
13
http://www.fpl.uni-kl.de
Altera Certified Design Center
Xputer Lab
(CDC) Program
University of Kaiserslautern
Certified Design Center (CDC) Program:
•
•
•
•
•
•
•
•
Barco Silex
El Camino GmbH
Excel Consultants
Plextek
Reflex Consulting
Sci-worx
Tality
Zaiq Technologies.
© 2001, reiner@hartenstein.de
14
http://www.fpl.uni-kl.de
The Altera Consultants
Alliance Program (ACAP):
Xputer Lab
University of Kaiserslautern
The Altera Consultants Alliance
Program (ACAP): lists
•41 offices in North America and
•29 in the rest of the world.
© 2001, reiner@hartenstein.de
15
http://www.fpl.uni-kl.de
Devlopment boards
Xputer Lab
University of Kaiserslautern
Devlopment boards are offered from:
• Altera
• El Camino GmbH
• Gid'el Limited
• Nova Engineering, Inc.
• PLD Applications
• Princeton Technology Group
• RPA Electronics Design, LLC
• Tensilica.
© 2001, reiner@hartenstein.de
16
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Consultants and services not listed
by Xilinx nor Altera (index)
Algotronix, Edinburgh,
Andraka Consulting Group
Arkham Technology, Pasadena, CA
Barco Silex, Louvain-la-Neuve, Belgium,
Bottom Line Technologies, Milford, NJ
Codelogic, Helderberg, South Africa,
Coelacanth Engineering, Norwell, MASS
Comit Systems, Inc., Santa Clara, CA
EDTNProgrammableLogicDesignCenter
© 2001, reiner@hartenstein.de
Flexibilis, Tampere, Finland,
Geoff Bostock Designs, Wiltshire, England,
Great River Technology, Alberquerque, NM,
New Horizons GB Ltd, United Kingdom,
North West Logic
Silicon System Solutions, Canterbury, Australia,
Smartech, Tampere, Finland,
Tekmosv, Austin, Texas,
The Rockland Group, Garden Valley, CA
Nick Tredennick, Los Gatos, California,
Vitesse,
17
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Consultants and services not
listed by Xilinx nor Altera (1)
Algotronix, Edinburgh, Reconfigurable Computing and FPL in
software radio, communications and computer security
Andraka Consulting Group high performance FPGA designs for
DSP applications
Arkham Technology, Pasadena, low cost IP cores for Xilinx and
Atmel, embedded processor, DSP, wireless communication,
COM / CORBA / DirectX, client-server database programming,
software internationalization, PCB design
Barco Silex, Louvain-la-Neuve, Belgium, IP integration boards
for ASIC and FPGA, consultancy, design, sub-contracting
© 2001, reiner@hartenstein.de
18
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Consultants and services not
listed by Xilinx nor Altera (2)
Bottom Line Technologies, Milford, New Jersey, FPGA design,
training, designing Xilinx parts since 1985
Codelogic, Helderberg, South Africa, consulting, FPGA design
services
Coelacanth Engineering, Norwell, Massachusetts, design services,
test development services, in wireless communication, DSP-based
instrumentation, mixed-signal ATE
Comit Systems, Inc., Santa Clara, California, DSP, ASIC,
networking, embedded control in avionics -- FPGA / ASIC design
and system software
EDTN Programmable Logic Design Center
© 2001, reiner@hartenstein.de
19
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Consultants and services not
listed by Xilinx nor Altera (3)
FirstPass, Castle Rock, Colorado
Vitesse, ASIC design
Flexibilis, Tampere, Finland, VHDL IP cores for Xilinx products
Geoff Bostock Designs, Wiltshire, England, FPGA design
services
Great River Technology, Alberquerque, New Mexico, FPGA
design services in digital video and point-to-point data
transmission for aerospace, military, and commercial
broadcasters
New Horizons GB Ltd, United Kingdom, FPGA design and
training, Xilinx specialist
North West Logic; FPGA and embedded processor design in
digital communications, digital video
© 2001, reiner@hartenstein.de
20
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
Consultants and services not
listed by Xilinx nor Altera (4)
Silicon System Solutions, Canterbury, Australia, VHDL IP
cores for the ASIC and FPGA/CPLD/EPLD markets
Smartech, Tampere, Finland, ASIC and FPGA design
Tekmosv, Austin, Texas, Multiple Designs on a Single Gate
Array, HDL synthesis, design conversions, chip debug, test
generation
The Rockland Group, Garden Valley, California, a
TeleConsulting organization about logic design for FPGAs
Nick Tredennick, Los Gatos, California, investor and
consultant
© 2001, reiner@hartenstein.de
21
http://www.fpl.uni-kl.de
>> Terminology
Xputer Lab
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Xputer architecture and circuitry
http://www.uni-kl.de
© 2001, reiner@hartenstein.de
22
http://www.fpl.uni-kl.de
Terminology
Xputer Lab
University of Kaiserslautern
Platform
Programming
source
“von Neumann”
Hardware
Software
Soft Machine (w.
soft datapaths)
Coarse grain
Flexware
high level
Configware
fine grain Flexware
netlist level
Configware
Paradigm
RL (FPGA etc.)
© 2001, reiner@hartenstein.de
23
http://www.fpl.uni-kl.de
Xputer Lab
Terminology & Acronyms
University of Kaiserslautern
•
•
•
•
•
•
•
• RC: reconfigurable computing
• RL: reconfigurable logic
Software (SW): procedural sources*
Configware (CW): structural sources
Hardware (HW): hardwired platforms
ASIC: customizable hardwired platforms
Flexware (FW): reconfigurable platforms
FPGA: field-programmable gate array
FPL: field-programmable logic
*) note: firmware is SW !
© 2001, reiner@hartenstein.de
24
http://www.fpl.uni-kl.de
Stream-based Computing (2)
Xputer Lab
University of Kaiserslautern
terms:
•
•
•
•
DPU:
DPA:
rDPU:
rDPA:
datapath unit
datapath array
reconfigurable DPU
reconfigurable DPA
• stream-based computing:
using complex pipe network
(super-systolic: Kress et al.)
© 2001, reiner@hartenstein.de
25
http://www.fpl.uni-kl.de
Confusing Terminology
Xputer Lab
University of Kaiserslautern
Computer Science and EE as well as ist R&D and applicatgion areas
suffer from a babylonial confusion.
Communication not only between Computer Science and EE, but also
between ist special areas, even between ist different abstrac tion
levels is made difficult – mainly because of immature terminology in
relation to reconfigurable circuits and their applications.
Terms are rarely standardized and often used with drastically
different meanings – even within then same special area.
Often terms have been so badly coined, that they are not selfexplanatory, but mesleading. A demonstratory example is the
comparizon of terms used used in VHDL and Verilog.
Ideal are "intuitive" terms. But often Intuition yields the wrong idea.
Whenever a new term appears in teaching, I often have to tell the
students, that the term does not mean, what he believes.
© 2001, reiner@hartenstein.de
26
http://www.fpl.uni-kl.de
.
Terms (1)
[à la Ingo Kreuz]
Xputer Lab
University of Kaiserslautern
Term
Hardware
Flexware
Meaning
hardwired
Reconfigurable
Example
Processor, ASIC
(structurally programmable)
FPLA, FPGA,
KressArray
Firmware
Microprogramme
IBM 360 Computer Family
Software
procedural programs
Word, C, OS,
Compiler, etc.
(rarely used
after introduction of RISC proc.)
(sequentially executable by a CPU)
Configware structural programs, soft
IP cores, personalizing CPLD,
FPGA, or other Flexware
© 2001, reiner@hartenstein.de
27
for rDPA FPGA
configuration, e. g. as a logic
circuit, state machine,
datapath, function
http://www.fpl.uni-kl.de
.
Terms (2)
[à la Ingo Kreuz]
Xputer Lab
University of Kaiserslautern
Term
Meaning
Example
data
objects of computing
“data” property
depends on the moment
of watching
data stream ordered, also parallel
data word lists,
obtained by scheduling
programming personalisation by
loading programm code
program
source text or object
code for programming
© 2001, reiner@hartenstein.de
28
Bits, numbers, operands,
results, any text (also
compiler input) lists,
graphs, tables, images, ...
I/O data streams for
systolic or other arrays
procedural code or
structural code: for
(re)configuration
procedural oder structural
http://www.fpl.uni-kl.de
.
Terms (3)
[à la Ingo Kreuz]
Xputer Lab
University of Kaiserslautern
Term
boot program
booting
Meaning
simple program to
enable programming
- usually saved in
non-volatile memory
load and execute a
boot program
© 2001, reiner@hartenstein.de
29
Example
comparable to the
starter of the
motor of a car
http://www.fpl.uni-kl.de
Hardware Terms (1)
[à la Ingo Kreuz]
Xputer Lab
University of Kaiserslautern
Term
machine
„dataflow
machine“
CPU
Meaning
execution unit, driven by
deterministic sequencer
not a machine, since without
a deterministic sequencer
(exotic concept)
Instruction Set Processor
("von Neumann”): program
counter (instruction
sequencer) and DPU - mode of
Example
von Neumann
machine
(sleeping
research
area)
ARM, Pentium
core,
operation: deterministically
instruction-driven
© 2001, reiner@hartenstein.de
30
http://www.fpl.uni-kl.de
Hardware Terms (2)
[à la Ingo Kreuz]
Xputer Lab
University of Kaiserslautern
Term
DPU
Meaning
data path unit, processes
operands - no CPU since without
sequencer - no maschine
Computer
Parallel
Computer
CPU with RAM and interfaces
ensemble of several Computers
Xputer
deterministically data-driven
Machine, (transport-triggered) data counter(s) used instead of a
program counterm
indeterministically data-driven
dataflow
machine
(execution sequence unpredictable)
© 2001, reiner@hartenstein.de
31
Example
ALU with
registers,
multiplexers etc.
MoM
architectures
(Kaiserslautern)
(sleeping research
area)
http://www.fpl.uni-kl.de
Terms on Parallelism (1)
[à la Ingo Kreuz]
Xputer Lab
University of Kaiserslautern
Term
parallelism
Meaning
several levels of parallelism
distinguished
concurrent
parallel processes run on
different CPUs of a parallel
computer - may occasionally
exchange signals or data
ISP (instruction several CPUs run in parallel
set parallelism) by clocked synchronization
© 2001, reiner@hartenstein.de
32
Example
parallel processes,
parallelism at
instruction set level,
pipelines,
weather prognisis,
complex simulations,
etc.
VLIW (very long
instruction word)
computer
http://www.fpl.uni-kl.de
[à la Ingo Kreuz]
Xputer Lab
Terms on Parallelism (2)
University of Kaiserslautern
Term
pipelining
chaining
Pipe network
Meaning
several uniform or different
DPUs running simultaneously
- connected to a pipeline by
buffer registers.
several uniform or different
DPUs running simultaneously
- connected to a pipeline
without buffer registers
Ensemble of DPUs, also
multiple pipelines, also with
irregular or wild structures
© 2001, reiner@hartenstein.de
33
Example
pipelined CPUs, pipe
networks, systolic,
etc.
Schaltnetze,
komplexe
arithmetische
Operatoren
systolisc arrays,
stream-based
computing arrays
http://www.fpl.uni-kl.de
[à la Ingo Kreuz]
Xputer Lab
Terms on Parallelism (3)
University of Kaiserslautern
Term
Meaning
Example
Systolic Array
Pipe network with only
linear (straight-on, no
branching), uniform
pipelines (all DPUs
hardwired and with same
functionality) pipelines
pipe network, configured
before fabrication
Matrix computation,
DSP, DNA sequencing,
etc.
stream-based arrays,
configurable after
fabrication
KressArray
stream-based
computing arrays
(super-systolic arrays)
(coarse grain)
reconf. streambased arrays
© 2001, reiner@hartenstein.de
34
image processing, DSP,
complex functions and
algorithms
http://www.fpl.uni-kl.de
Counterparts
[à la Ingo Kreuz]
Xputer Lab
University of Kaiserslautern
category
programing
mode
property
procedural
(classical)
counterpart
machine:
principle of
operation
controlflow-driven
(instruction-driven): v.
Neumann
system:
principle of
operation
Set-up time
(datapaths
switched thru)
instruction-flow-driven Data-stream-based (systolisc
(parallel computer etc.) array, DPU array, KressArray)
during run time;
(instruction-driven)
© 2001, reiner@hartenstein.de
35
structural (synthesis, design)
- „field-programmable“, PLA
„programming“, etc.
Data-driven: Xputer machine
before run time:
FPGA (at compile time)
Gate Array (at fabrication)
http://www.fpl.uni-kl.de
>> MoPL data-procedural language
Xputer Lab
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Xputer architecture and circuitry
http://www.uni-kl.de
© 2001, reiner@hartenstein.de
36
http://www.fpl.uni-kl.de
Xputer Lab
Fundamental Ideas available (1)
University of Kaiserslautern
• Data Sequencer Methodology
• Data-procedural Languages (Duality w. v. N.)
• ... supporting memory bandwidth optimization
• Soft Data Path Synthesis Algorithms
• Parallelizing Loop Transformation Methods
• Compilers supporting Soft Machines
• SW / CW Partitioning Co-Compilers
© 2001, reiner@hartenstein.de
37
http://www.fpl.uni-kl.de
Xputer Lab
Fundamental Ideas available (2)
University of Kaiserslautern
• Programming Xputers
• Similarities to programming computers
• How not to get confused by similarities
• What benefits vs. Computers ?
© 2001, reiner@hartenstein.de
38
http://www.fpl.uni-kl.de
Programming Language Paradigms
Xputer Lab
University of Kaiserslautern
language category
both deterministic
operation
sequence
driven by:
state register
address
computation
Instruction fetch
parallel memory
bank access
© 2001, reiner@hartenstein.de
Computer Languages
Xputer Languages
procedural sequencing: traceable, checkpointable
read next instruction,
read next data item,
goto (instr. addr.),
goto (data addr.),
jump (to instr. addr.),
jump (to data addr.),
instr. loop, loop nesting
data loop, loop nesting,
no parallel loops, escapes,
parallel loops, escapes,
instruction stream branching data stream branching
program counter
data counter(s)
massive memory
overhead avoided
cycle overhead
memory cycle overhead
overhead avoided
interleaving only
no restrictions
39
http://www.fpl.uni-kl.de
Similar Programming Language Paradigms
Xputer Lab
University of Kaiserslautern
language category
both deterministic
sequencing
driven by:
© 2001, reiner@hartenstein.de
Computer Languages
Xputer Languages
procedural sequencing: traceable, checkpointable
read next instruction,
read next data object,
goto (instruction addr.),
goto (data addr.),
jump (to instruction addr.),
jump (to data addr.),
instruction loop,
data loop,
instruction loop nesting
data loop nesting,
no parallel loops,
parallel data loops,
instruction loop escapes,
data loop escapes,
instruction stream branching data stream branching
40
http://www.fpl.uni-kl.de
JPEG zigzag scan pattern
-> Declarations
goto PixMap[1,1]
4
Xputer
EastScan
is Lab
University of Kaiserslautern
step by [1,0]
end EastScan;
1
SouthScan is
step by [0,1]
endSouthScan;
HalfZigZag;
SouthWestScan
uturn (HalfZigZag)
2
NorthEastScan is
loop 8 times until [*,1]
step by [1,-1]
endloop
end NorthEastScan;
3
SouthWestScan is
loop 8 times until [1,*]
step by [-1,1]
endloop
end SouthWestScan;
© 2001, reiner@hartenstein.de
y
dataHalfZigZag
counter
data counter
data counter
data counter
41
HalfZigZag
HalfZigZag is
EastScan
loop 3 times
SouthWestScan
SouthScan
NorthEastScan
EastScan
endloop
end HalfZigZag;
x
http://www.fpl.uni-kl.de
>> Xputer architecture and circuitry
Xputer Lab
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Xputer architecture and circuitry
http://www.uni-kl.de
© 2001, reiner@hartenstein.de
42
http://www.fpl.uni-kl.de
Xputer Lab
University of Kaiserslautern
GAG Scheme
GAG = Generic
Address
Generator
DA
B0
[|
L0
Limit
Stepper
GAG
© 2001, reiner@hartenstein.de
DA
|
L
|
]
limit
B0
Address
Stepper
|
Base
Stepper
A
43
http://www.fpl.uni-kl.de
GAG: Address Stepper
GAG: Address Stepper
Xputer Lab
University of Kaiserslautern
]
[
Base
B0
Limit
GAG =
Generic
Address
Generator
[|
DA
|
|
stepVector
maxStepCount
init
tag
L
B0
|
DA
A
Step
Counter
+/–
=o
Escape
Clause
End
Detect
L
|
|
]
limit
A
Address
© 2001, reiner@hartenstein.de
44
endExec
http://www.fpl.uni-kl.de
Generic Sequence Examples
Xputer Lab
University of Kaiserslautern
L0 DA B0
a)
Limit
Slider
b)
A
c)
d)
Address
Stepper
e)
© 2001, reiner@hartenstein.de
f)
Base
Slider
GAG
g)
45
http://www.fpl.uni-kl.de
Slider Operation Demo Example
Xputer Lab
University of Kaiserslautern
address
floor
F
ceiling
B0
DA
DB
x
© 2001, reiner@hartenstein.de
y
DB
46
L0
C
DL
DL
http://www.fpl.uni-kl.de
Xputer Lab
MoM Xputer Architecture
University of Kaiserslautern
Smart memory interface
Scan
Window
„Cache“
© 2001, reiner@hartenstein.de
rDPA
47
Multiple
RAM banks
http://www.fpl.uni-kl.de
Xputer Lab
MoM Architecture Features
University of Kaiserslautern
• Scan Cache Size adjustable at run time
• Any other shape than square supported
• 2-dimensional memory space
• Supports generic „scan patterns“
– Subject of parallel access transformations
– compare Francky Cathoor et al .
• Supports visualization
© 2001, reiner@hartenstein.de
48
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Herz‘ MoM Xputer Architecture
Xputer Lab
University of Kaiserslautern
smart
memory
interface
Scan
Window
„Cache“
© 2001, reiner@hartenstein.de
KressArray
49
Multiple
RAM banks
http://www.fpl.uni-kl.de
Xputer Lab
MoM Application Examples
University of Kaiserslautern
• Image Processing
• Grid-based design rule check [1983*]
–
–
–
–
4 by 4 word scan cache
Pattern-matching based
Our own nMOS „DPLA“ design
design rule violation pixel map automatically
generated from textual design rules
– 256 M&C nMOS, 800 single metal CMOS
– Speed-up > 10000 vs. Motorola 68000
*) „machine“ not yet discovered
© 2001, reiner@hartenstein.de
50
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Schedule
Xputer Lab
University of Kaiserslautern
time
slot
08.30 – 10.00
Reconfigurable Computing (RC)
10.00 – 10.30
coffee break
10.30 – 12.00
Stream-based Computingfor RC
12.00 – 14.00
lunch break
14.00 – 15.30
Resources for RC
15.30 – 16.00
coffee break
16.00 – 17.30
FPGAs: recent developments
© 2001, reiner@hartenstein.de
51
http://www.fpl.uni-kl.de
>>> Coarse Grain
Xputer Lab
University of Kaiserslautern
- END © 2001, reiner@hartenstein.de
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