Summary
and
Perspectives
Jan M. Rabaey
Low Power Design Essentials ©2008
Chapter 13
Low-Power Design Rules – Anno 1997
 Minimize waste (or reduce switching capacitance)
–
–
–
–
Match computation and architecture
Preserve locality inherent in algorithm
Exploit signal statistics
Energy (performance) on demand
 Voltage as a design variable
– Match voltage and frequency to required performance
More easily accomplished in application-specific than
programmable devices
Low Power Design Essentials ©2008
[Ref: J. Rabaey, Intel’97]
13.2
Adding Leakage to the Equation
 The emergence of power domains
 Leakage not necessarily a bad thing
– Optimal designs have high leakage (ELk/ESw ≈ 0.5)
 Leakage management requires runtime
optimization
– Activity sets dynamic/static power ratio
 Memories dominate standby power
– Logic blocks should not consume power in standby
Low Power Design Essentials ©2008
[Emerged in late 1990s]
13.3
Low-Power Design Rules – Anno 2007
 Concurrency Galore
– Many simple things are way better than one complex one
 Always-Optimal Design
– Aware of operational, manufacture and environmental variations
 Better-than-worst-case Design
– Go beyond the acceptable and recoup
 The Continuation of Voltage Scaling
– Descending into ultra-low voltages
– How close can we get to the limits?
 Explore the Unknown
Low Power Design Essentials ©2008
[Ref: J. Rabaey, SOC’07]
13.4
Some Concepts Worth Watching




Novel switching devices
Adiabatic logic and energy-recovery
Self-timed and asynchronous design
Embracing non-conventional
computational paradigms
– Towards massive parallelism?
Low Power Design Essentials ©2008
13.5
Novel Switching Devices
 Nanotechnology brings promise of broad
range of novel devices
– Carbon-nanotube transistors, NEMS,
spintronics, molecular, quantum, etc
– Potential is there – long-term impact unclear
– Will most probably need revisiting of logic
design technology
 Out-of-the-box thinking essential
Low Power Design Essentials ©2008
13.6
Example: Nano-Mechanical Relays
Source
Drain
 Minimum energy in CMOS limited by leakage
– Even if had a perfect (zero leakage) power gate
 How about a nano-scale mechanical switch?
– Infinite Roff, low Ron
Low Power Design Essentials ©2008
[Ref: H. Kam, UCB’08]
13.7
Relay Circuit Design and Comparison
Relay FA Cell
A
A
B
Cin
Cout
B
A
A
90nm
CMOS
B
B
A
Sum
A
B
A
B
Cin
Cout
B
A
B
Low Power Design Essentials ©2008
[Ref: E. Alon, UCB’08]
13.8
Adiabatic Logic and Energy Recovery
 Concept explored in the 1990’s
-Proven to be ineffective at that time
 With voltage scaling getting harder, may become attractive again
Example: Resonant Adiabatic
Mixed-Signal Processor Array for
Charge-Based Pattern Recognition
Adiabatic logic modeled as
transmission gate driving capacitive
load from resonant clock
Adiabatic mixed-signal multiply-accumulation
(MAC). Charge-coupled MOS pair represents
variable capacitive load.
Low Power Design Essentials ©2008
© IEEE 2007
[Ref: R. Karakiewicz, JSSC’07]
13.9
number
Self-Timed and Asynchronous Logic
delay
Delay distribution as a function of variability
 Synchronicity performs best
under deterministic
conditions and when duty
cycle is high
 However, worst-case model
does not fair well when
variability is high
 In ideal case, self-timed
logic operates at “average
conditions”
 Protocol and signaling overhead of self-timed made it unattractive when
delay distributions where narrow
 This is not longer the case, especially under ultra low-voltage conditions
Effective “synchronous island” size is shrinking
 The “design flow” argument does not really hold either
− Example: Handshake Solutions [Ref: Handshake]
Low Power Design Essentials ©2008
13.10
Exploring the Unknown –
Alternative Computational Models
Humans
Ants
• 10-15% of terrestrial animal biomass
109 Neurons/”node”
Since 105 years ago
• 10-15% of terrestrial animal biomass
105 Neurons/”node”
Since 108 years ago
Easier to make ants than humans
“Small, simple, swarm”
Low Power Design Essentials ©2008
[Courtesy: D. Petrovic, UCB]
13.11
Example: Collaborative Networks
Metcalfe’s Law
to the rescue of
Moore’s Law!
Boolean
Collaborative Networks
 Networks are intrinsically robust → exploit it!
 Massive ensemble of cheap, unreliable components
 Network Properties:
– Local information exchange → global resiliency
– Randomized topology & functionality → fits nano
properties
– Distributed nature → lacks an “Achilles heel”
Low Power Design Essentials ©2008
Bio-inspired
13.12
Learning from Sensor Network Concept
Low Power Design Essentials ©2008
[Ref: J. Rabaey, I&C’04]
13.13
“Sensor Networks on a Chip”
 “Large” number of very simple
unreliable components provide
estimates of result
 Fusion block combines estimates
exploiting the statistics
 Fusion block only “reliable”
component
© IEEE 2007
x
y
Computation
Statistically
similar
Decomposition
Sensor 1
Estimators need to be independent
for this scheme to be effective
y1
y2
Sensor 2
y
x
Sensor 3
y3
Fusion Block
y4
Sensor 4
y1
Low Power Design Essentials ©2008
[Ref: S. Narayanan, Asilomar’07]
Sensor NOC
13.14
Example: PN code acquisition for CDMA

Statistically similar decomposition of
function for distributed sensor-based
computation.

Robust statistics framework for design of
fusion block.

Creates better result with power savings of
up to 40% for 8 sensors in PN-code
acquisition in CDMA systems

New applications in filtering, ME, DCT, FFT
and others
© IEEE 2007
100X
[Ref: S. Narayanan,
Asilomar’07]
Low Power Design Essentials ©2008
with 40% energy
savings
Prob (Detection)
13.15
Book Summary
 Energy-Efficient one of (if not the most)
compelling issues in Integrated Circuit
Design today and in the coming decades
 The field has matured substantially
– From “getting rid of the fat” and reducing
waste
– To “truly energy-lean” design technologies
 Still plenty of opportunities to move
beyond what can be done today
 There is plenty of room at the bottom
Low Power Design Essentials ©2008
13.16
Interesting References for Further Contemplation
Books and Book Chapters

L. Svensson, “Adiabatic and Clock-Powered Circuits,” in C. Piguet, Low-Power Electronics Design, Ch. 15, CRC
Press, 2005.

R. Wasser (Ed.), Nanoelectronics and Information Technology, Wiley-CVH, 2003.
Articles

E. Alon et al,, “Integrated Circuit Design with NEM Relays,” UC Berkeley Technical Report, 2008.

Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen, “Low-power CMOS digital design,” IEEE Journal of
Solid-State Circuits, vol. 27, pp. 473 - 484, April 1992.

D.M. Chapiro, “Globally Asynchronous Locally Synchronous Systems,” PhD thesis, Stanford University, 1984.

Digital Light Processing (DLP), http://www.dlp.com

Handshake Solutions, “Timeless Designs,” http://www.handshakesolutions.com

T. Indermaur and M. Horowitz, “Evaluation of charge recovery circuits and adiabatic switching for low power CMOS
design,” Symposium on Low Power Electronics, pages 102-103, October 1994.

H. Kam, E. Alon, and T.J. King, “Generalized Scaling Theory for Electro-Mechanical Switches ,” UC Berkeley, 2008.

R. Karakiewicz, R. Genov, and G. Cauwenberghs, "480-GMACS/mW resonant adiabatic mixed-signal processor array
for charge-based pattern recognition," IEEE Journal of Solid-State Circuits, vol. 42, pp. 2573 - 2584, November 2007.

D. Liu and C. Svensson, "Trading speed for low power by choice of supply and threshold voltages," IEEE Journal of
Solid-State Circuits, vol. 28, pp. 10 - 17, January 1993.

Sriram Narayanan, Girish V. Varatkar, Douglas L. Jones, Naresh Shanbhag. "Sensor Networks-Inspired Low-Power
Robust PN Code Acquisition”, Proceeding of Asilomar Conference on Signals, Systems, and Computers, pp. 13971401, October, 2007.

J. Rabaey, “Power dissipation, A cause for a paradigm shift?”, Invited Presentation, Intel Designers Conference,
Phoenix, 1997.

J. Rabaey, “Embracing Randomness – A Roadmap to Truly Disappearing Electronics,” Keynote Presentation, I&C
Research Day, http://www.eecs.berkeley.edu/~jan/presentations/randomness.pdf, EPFL Lausanne, July 2004.

J. Rabaey, “Scaling the Power Wall”, Keynote Presentation SOC 2007,
http://www.eecs.berkeley.edu/~jan/presentations/PowerWallSOC07.pdf, Tampere, Nov. 2007.
Low Power Design Essentials ©2008
13.17