Future memory requirements
Computer memory classification
Emerging memory types
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Phase change memory
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Polymer memory
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Molecular memory
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Ionic memory
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Carbon memory
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Metal-oxide memory
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…..
For future memory
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Scalability (~ 10 nm)
Fast speed (close to DRAM)
High performance & storage capability (close to HDD)
Low cost (close to HDD)
Two terminal structure based non-charge memory
Simple process
Low energy consumption
From 2013 ITRS
Various kind of memory device
*Feature size (F): the smallest feature you can create
Existing memory
Material with RRAM characteristic
- Colossal Magneto-Resistance (CMR)
- Metal oxide : Nb2O5, NiO, Al2O3, SiOx
- Chalcogenide material : GeTe, MoS2..
- Perovskite material : SrTiO3, SrZrO3..
Emerging memory
MRAM: Magnetroresistive RAM
- Switching speed (sub 50 ns for write
andPhase-change
erase)
PRMA:
RAM
7
- Large on/off ratio ( up to 10 ) FRAM: Ferroelectric RAM
- Low power consumption (10-5 W/bit)
RRAM: Resistive RAM
- Standard CMOS technology
Jeong et al., Rep. Prog. Phys. 75 076502 (2012)
SiOx switching memory
Our Group (before 2012)
Various Nanogap Systems
Vertical SiOx Junction
Advantages
• High on-off ratio up to 107
• Low energy consumption (10-3 J/Gbits)
Unipolar Switching Behavior
Edge switching
• Fast switching speed (~ 50 ns)
• Unipolar type (sub-5 nm channel)
• Radiation hardened memory
• Potential both 1D-1R and 1T-1R
• Low-temperature, Low-cost fabrication
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ACS Nano, 3 (12), 4122-4126 (2009)
Small 5 (24), 2910-2915 (2009).
Nano Letters 10 (10), 4105-4110 (2010)
JACS, 133 (4), 941-948 (2010).
Nat Commun 3, 1101 (2012)
method
• Substrates-Independent (ITO, Flexible, or
hard Si substrate)
• CMOS technology
SiOx memory development
Main Issues
• High density integration
• Stability Issue
1 kbit 1D-1R Device
Conducting-Interlayer SiOx y
Adv. Mater (2013)
J. Appl. Phys. (2012)
Adv. Mater (2013)
ACS Nano (2014)
ACS Nano (2012)
Sci. Rep.. (2013)
Adv. Mater (2012)
• High Electroforming Voltage
• Edge Switching transport
IEEE EDL. (2012)
Appl. Phys. Lett. (2012) Appl. Phys. Lett. (2013)
Appl. Phys. Lett. (2013)
Nano Lett. (2013)
Graphene/SiOx/Graphene on Plastic Substrate
Graphene/SiOx/Graphene on Glass
Nanoporous SiOx; the big breakthrough
Nanoporous SiOx
Internal edge switching transport
Nanoporous SiOx
Electroforming Voltage (13x less)
Nanoporous SiOx
Nanoporous SiOx
SiOx advantages
Nanoporous SiOx memory
1. Fabrication of porous SiOX film (active layer of memory)
Method: Anodic galvanostatic etching method
Direct deposition of porous SiOX
Method: E-beam evaporator
Substrate
Cathode
Vaporized material
Anode
Step 1
Step 2
Electron beam
Electron gun
Target material
(SiO2)
Step 3
To vacuum pump
Pt/Ti deposition
SiOx deposition
Porous process
(Hf/Ethanol, 0.5 %)
Problems
i) Due to the resistance variation, uniformity of pore has decreased.
(The electrode is narrower, this problem will be serious)
ii) Can not be applied to multi-layer structure
iii) The size of pore is sensitively affected by concentration of solution and etching time.
iv) Anodic etching method is not suitable for mass production.
Future works
3D stackable memory
Base structure
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Diode : Poly PN diode or Ti/TiOx/Pt
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Memory : Nanoporous SiOx
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Isolation layer : Non-porous SiOx and Graphene
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Possible Electrodes : Pt, Al, Ti, TiN
Procedures
1st 1D-1R junction (8 layers)
2nd1D-1R junction (8 layers)
3rd 1D-1R junction (8 layers)
Energy consumption of writing of 1D-1R cross bar devices
3. Operation of one-diode one-memory (1D1R) device.
Operation yield of 1D1R cell
Bottom electrode
8
7
6
5
4
3
2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Working memory
Working diode
Middle electrode
Top electrode
1
1 mm
Memory - 89% (57/64 )
: measure between Bott. and Mid. elec.)
Diode - 93% (60/64)
: measure between Mid. and Top elec.)
1D1R cell - 86% ( 55/64)
: measure between Bott. and Top elec.)
- Since, the burning issue was suppressed by
solution 1 and 2, the diode that is located on
memory can be operated stably. Thus, overall
operation yield of 1D1R cell was increase up to 86%.
3. Operation of one-diode one-memory (1D1R) device.
Current manufacturing process for 1D1R cell
Sample cleaning
Reactive ion etching of SiOx (d: 100 nm)
Photolithography (bottom electrode) - LOR
- S1518
Ti deposition (t: 3 nm, e-beam evaporator)
Pt deposition (t:97 nm, e-beam evaporator)
Reactive ion etching of Substrate (d: 40 nm)
Inspection I
: depth profile
Lift off process
Inspection IV
: Morphology
: memory property
Ti deposition (t: 3 nm, sputter)
TiO2 deposition (140 nm, e-beam evaporator)
Inspection V
: Thickness of TiO2
Pt deposition (t:37 nm, sputter)
Photolithography (Top electrode)
Lift off process
Inspection II
: Morphology
Porous SiOx deposition (t: 120 nm, e-beam
evaporator)
Thermal annealing ( 300 oC, 1 hr)
Photolithography (middle electrode)
Reactive ion etching of TiO2 (d: 100 nm)
Ti deposition (t: 100 nm, e-beam evaporator)
Inspection III
: Thickness of SiOx
Characterization of 1D1R
Inspection VI
: Morphology
: Diode property