Flash Memory Built-In
Self-Diagnosis with
Test Mode Control
Jen-Chieh Yeh, Yan-Ting Lai,
Yuan-Yuan Shih, and Cheng-Wen Wu
Laboratory for Reliable Computing (LaRC)
Department of Electrical Engineering
National Tsing Hua University
Hsinchu, Taiwan 30013
Outline
• Introduction
• Flash Memory Diagnosis Methodology
• BISD with Enhanced Test Mode Control
• Experimental Results
• Conclusions
2
Introduction
• Flash memory is enjoying a rapid market
growth
• System integration and new applications drive
the demand for flash technologies [ITRS 2003]
• Embedded flash memory is gaining popularity
in SOC applications
• BIST and BISD are considered a good solution
for flash memory testing and diagnosis
3
Flash Memory Fault Models
• Flash memories are commonly tested for
disturbance problems
• Flash disturb fault models are defined in our
DELTA02 and VTS02 papers
• WPD, WED, BPD, BED, and OP faults are
considered here for the BiNOR-type flash
memory
• SAF, TF, SOF, CFst and AF are also
considered
4
BiNOR-Type Flash Memory
• Bi-directional tunneling program/erase NORtype flash memory
• Low power consumption and excellent
reliability
NOR
Program
Erase
VT is raised
VT is decreased
BiNOR VT is decreased
VT is raised
Source: IEEE Trans. Electron Devices, 2001
5
Flash Memory Diagnosis Methodology
Fault Models
Fault
Simulator
Diagnosis
Algorithm
BISD
Source: ICCAD00
SAF, TF, SOF, CFst, AF,
WPD, WED, BPD, BED, OP
Fault Dictionary
March-FT
(SA1)
Error Catch
and Analysis*
Tester Log
Error Bit Map
Parser
(to get
signatures)
(WPD)
(BPD)
Fault Map
6
Part of the March-FT Fault Dictionary
• March-FT:
{ (f); (r1,p0,r0);
<0
0 0 1
Signatures
(r0); (f); (r1,p0,r0);
1
0
0 0 1
Fault Sets
(r0); }
1>
Groups
<0100001000> SAF(0), OPM, SOFM, SOFT
A
<0001100011> SAF(1), TF(D)
B
<0000001000> TF(U), CFst(0;1/0)L, OPH,
C
CFst(1;1/0)S, AFL, WPDL,
BPDL
7
BISD with Enhanced Test Mode Control
• Built-in March-FT algorithm
• Programmable diagnosis algorithms
• Flexible output format for test and/or diagnosis
• Supports dynamic burn-in (BI) test
• Engineering test mode can be accessed by BISD
– Overall test time is reduced
• Provides various types of access commands, e.g.,
Reset Wait
8
High Voltage (HI-V) Tests
• HI-V tests usually employed to reduce the
test time in the engineering test mode
• TExecution(HI-V Erase) < TExecution(Erase)
{A9, RSTB, OEB}
Normal
Signal
flags
Test Collar
{A[17:10], A[8:0]}
DQ
{WEB, CEB}
BISD
HI-V
Detector
Memory
Controller
Memory
Array
9
BISD Architecture
2
MUX
CMD Reg.
5
CLK
BRS
BMS
BNS
BIM
BAC
BFI
BSO
FSM
of
CTR
7
CMD
Decision
E-info. Selector
E-info. Register
5
FSM
of
TPG
March
Op.
Counter
43
BISD Controller
(CTR)
E-info.
Collector
FOPC LookUp Table
ADDR
Generator
DB Generator
& Comparator
Control Signal
Generator
I/O Selector
BSI
RBB
WPB
8
8
I/O1
I/O2
CEB
WEB
REB
CLE
ALE
5
Test Pattern Generator
(TPG)
10
Parallel Test Methods
Original Program/Erase Unit
Y-Decoder
Flash
Memory
Controller
Page buffer & SA
Page buffer &SA
Block 0
Block 1024
Block 1
Block 1025
Block 2
Block 1026
Plane 0
Plane 1
Block 1023
Block 2047
Page buffer & SA
Page buffer &SA
Charge pump and other analog circuitry
X-Decoder
Proposed Program/Erase Unit
11
Experimental Results
Case I
Case II
Flash memory area
7.6mm2
60mm2
Flash memory capacity
2Mb
256Mb
BISD area
0.05mm2
0.3mm2
Area overhead
0.67%
0.5%
BISD frequency
10MHz
40MHz
• BISD circuit implemented on FPGA
• BISD test results compared with those of ATE
12
Diagnosis Result for 2Mb Flash
Chip1 Chip2 Chip3 Chip4 Chip5 Chip6 Chip7 Chip8
MSCAN
Pass
Fail
Pass
Fail
Partial
Fail
March-FT
Fail
Fail
Fail
Fail
Fail
Fail
Fail
Pass
Unmodeled
Faults
0
10
0
---
0
---
0
0
Fault
Groups
A: 1
B: 19
C:182 C: 1
D: 81 E: 2
F: 1
G: 1
J: 30
K: 54
A: 4
C:113
D: 16
Pass Pass
A: 6
A: 5
C: 4
C:876 C:940 D: 1
D:550 D:496
J:105
13
The Error Bitmap for Chip 5
14
The Fault Bitmap for Chip 5
15
Results for 256Mb Flash Memory
• Three chips are tested in this case
• ATE test result: one passed and two failed
• FPGA (BISD prototype) test results: two passed
and one failed
– The difference between ATE and FPGA is
clock rate
– Real BISD can perform at-speed test
• Diagnosis result for the failed chip: one block
cannot be erased (SA0)
– Same for ATE & FPGA
16
Conclusions
• We have proposed a flash memory diagnosis
methodology and BISD design
– Supports test, diagnosis, and BI modes
– With enhanced test mode control
• Area overhead is low
• An FPGA-based low-cost flash memory
diagnosis system is implemented
– Real BISD required for at-speed test
17