DC56 Bi-weekly Meeting
July 10, 9-11am CDT
Design Plan of
2nd FEE prototype
Chih-Hsun Lin, Ming-Lee Chu,
Chia-Yu Hsieh, Takahiro Sawada
Wen-Chen Chang
Institute of Physics, Academia Sinica, Taiwan
1
Outline
1st FEM & Results of Performance
Noise Test at IPAS & 2nd FEM Design Plan
Schedule & Manpower
Summary




2
1ST FEM & RESULTS OF
PERFORMANCE
3
Parameters of DC5/6
Item
Parameters
Active Area
X*Y=248*208 cm2
Plane
X,Y,U,V
Cell size
8 mm
Number of channels
(256+32)*8=2304
Gas mixture
Ar/C2H6/CF4 45/50/5
Drift velocity of gas
72 m/ns
Time window
75 ns
Position resolution
200 m
Timing resolution
1 ns
Pile-up percent for 160(105) KHz event rate
1.1(0.8) %
Number of primary electrons
~80
Gas gain
5*10^4
Nominal charge injection
2000000 e = 320 fC
Discriminator threshold
25000 e = 4 fC
4
FEE Components (1st FEE Design Plan)
Front End Module (FEM):



CMAD  preamplifier, shaper, discriminator
TDC  FPGA-TDC
Data Collection Module (DCM):



FPGA  Collect TDC data + Encoding data + Event buffer
+CMAD control
Optical transceiver  deliver TDC data to GANDALF
GANDALF : the interface module between DCM and
readout buffer

5
Schematic of FEE (1st FEE Design Plan)
6
CMAD-Datasheet
Parameters
Number of Channel
Time resolution (Jitter)
Shaper Peaking time
Processing speed
Linear dynamic range
Noise level
Threshold level
Gain
Gain resolution
Input signal
Output signal
DAC (gain, threshold, baseline)
Power consumption
7
CMAD
8
< 1 ns (100 ps)
10-20 ns
> 5 MHz/chan
0 – 900 fC
0.63 fC (threshold 4 fC)
0 – 400 mV (800 mV)
Low: 0.4 mV/fC – 1.2 mV/fC
High: 1.6 mV/fC – 4.8 mV/fC
0.1 mV/fC
Single-end
LVDS
10 bits
< 30 mW /per chan.
CMAD (INFN, Torino)
8
CMAD – Gain and Threshold Setting
* Gain Setting
Set Digital
Gain
Value [dig] [mV/fC]
Low
Gain
High
Gain
9
* Threshold Setting
Conversion
factor [fC/dig]
0
1.1
0.41
1
1.0
0.45
2
0.9
0.51
3
0.8
0.55
4
0.7
0.59
5
0.6
0.70
6
0.5
0.86
7
0.40
1.10
8
4.4
0.10
9
4.0
0.11
10
3.6
0.12
11
3.2
0.14
12
2.8
0.16
13
2.4
0.18
14
2.0
0.22
15
1.6
0.28
0 digit
Maximum thr.
650 digit
Minimum thr.
(pedestal)
All the channels/chips are calibrated in
order to have the pedestal positioned at
650 digit.
FPGA-TDC: Lattice XP2
250 MHz Clock, 1 ns Resolution
1 CMAD + 1 TDC
4 CMAD + 1 TDC
10
Block diagram of FEM module
Phase
Adjustment
0
CMAD
270
360
PLL
Synchreset
(1 ns accuracy)
11
System
Clock
FPGA
TDC
Measurement
FIFO
38.88
MHz
DAC
Setup
DCM
DC wire
90
~250
MHz
Xilinx Spartan-6 LXT (XC6SLX25T)
12
Block diagram of DCM module
FEM FIFO
Trigger
System Clock
Synch-reset
FPGA
Sorting
Trigger
Offset
Trigger
Latency
Hit Buffer
Trigger
Matching
Optical
Transceiver
13
FIFO
Trigger
Window
GANDALF
TDC
Meas.
Divided
Buffer
160 MByte/s
14
15
Components (baseline for 2,560 channels)
PreamplifierDiscriminator
TDC
DCM Control
Board
Gandalf
CMAD
FPGA-TDC
(LatticeXP2)
FPGA +
optical package
VME FPGA
8 Inputs/
8 Output
(8 channels)
8 Inputs/
1 Output
(8 channels)
40 Inputs/
1 Output
(320 channels)
8 optical
inputs/outputs
(2560 channels)
300 piece(s)
300 piece(s)
8 piece(s)
1 piece(s)
INFN, Torino
(READY)
IPAS
IPAS
Freiburg
(READY)
16
1st FEM (used in DESY beam test)

CMAD

FPGA [ TDC + Collect TDC data + Encoding data + Event buffer +DAC control (DCM function)]

USB – I/O
Daisy chain
Daisy chain
USB
17
CMAD
Wire input
Switching
regulator
FPGA
TDC
1st FEM Lab Test (FEM004) - Time Resolution
1-ns time resolution is achieved for all channels.
18
1st FEM Lab Test (FEM004) – Noise Level
* Results of noise level by threshold scan at gain= 4.4 mV/ fC.
19
Noise ( fC )
ch0 0.583  0.006
ch1 0.604  0.005
ch2 0.578  0.004
Noise ( fC )
ch3 0.620  0.011
ch4 0.610  0.004
ch5 0.608  0.005
Noise ( fC )
ch6 0.681  0.009
ch7 0.616  0.009
1st FEM Lab Test - Noise
1st
FEM prototype
CMAD @ gain = 4.4 mV / fC
MWPC CMAD board
( Michela’s presentation)
CMAD @ gain = 4.4 mV / fC
The noise level are equivalent to the results of MWPC CMAD board.
20
1st FEM Lab Test –
Single-hit Rate
No event loss at 250k single-hit rate.
21
1st FEM Lab Test (FEM004) –
TDC Linearity
 TDC is determined by the 4 phase lock loops with 250 MHz clocks instead
of delay-line.
 No visible non-linearity accumulation appears with more than 4 clock cycles.
22
1st FEM + PTA
- Cosmic Ray Test @ UIUC
Trigger scintillator
PTA
Small trigger scintillator
Tracking DC 0,1,4
Tracking DC 2,3
Trigger scintillator
drift window
Cosmic Ray Test Set up
23
TDC spectrum for a set of DC prototype - PTA.
DESY Beam Test Result

1st FEM + Proto. DC - PTA achieved a position resolution of
~ 200 um.
Position resolution
Efficiency
c
CMAD@ 4fC,1mV/fC,1.9kV,PTA
24
CMAD@ 4fC,1mV/fC
Noise level @ DESY Beam Test
• Noise could be under control but with lots of effort during the beam test.
• PTA was send to Taipei for the further investigation of sources of noise.
25
TDC Distribution @ DESY Beam Test
Trigger jiggering
or signal reflection?
26
NOISE TEST AT IPAS & 2ND FEM
DESIGN PLAN
27
Noise Test of 1st FEM prototype @ Taipei
(with PTA)
• Noise test
 Switching regulator  We
Daisy
remove them from the board and
chain
apply DC low-power supply. The
FPGA
noise is reduced. We will replace it
CMAD
TDC
by the linear regulator in the 2nd
Daisy
FEM.
chain
 USB  To be checked. Even
USB
though USB will not be used in the
final FEM, we have to use it during
the test.
 FPGA  To be checked. After
this test we will decide whether  Shielding  Good Shielding of
detector PCB and connector is
the digital and analog parts
very important. We will discuss it
should be separated. The pros
and cons for the choices will be later.
discussed later.
1st FEM prototype
Wire input
Switching
regulator
28
Noise Test of 1st FEM prototype @ Taipei
(with PTA)
* 1st FEM + PTA @ Taipei
* 1st FEM + PTA @ DESY
4 fC
CMAD @ gain = 1 mV/ fC ,
Without HV
CMAD @ gain = 1 mV/ fC
With HV
• Even though the EMI of 1st FEM is big, we can reduce noise below 4 fC by
good shielding and removing the switching regulator. We also get good
result at Taipei.
29
2nd FEE Design Plan
To be Decided (1): Separation of Analog and Digital Parts.
Plan1A.
Separate analog and digital part
Plan 1B.
Combine FPGA-TDC and
CMAD on the same board
Structure
CMAD boards & Backplane & FPGA- FEM board (CMAD + FPGATDC+
TDC ) +
DCM
Daisy chain + DCM board
Pros
Potentially less noisy
More mechanical flexibility
Cons
We have to be very careful of the
mechanical structure between
CMAD board and back plane.
Potentially more noisy
Note:
According to the test result in DESY beam test, the noise could be significantly
reduced by good metal shielding. We are repeating the test in Taipei. If the noise could
be indeed effectively reduced by this method, we prefer “Plan 1B” for the design.
30
31
32
2nd FEE Design Plan
To be Decided (2): Num. of channels per FEM module

The form factor of DC56 is similar to DC4. Therefore we will follow the geometry of
ASD8 board which used for DC4.
ASD8 board
Plan 2A: 16-ch per connector  8 chips per board  64-ch per board
Plan 2B: 32-ch per connector  16 chips per board  128-ch per board
If it doesn’t affect the performance, we prefer 128ch per FEM board.
The number of FEM boards will be reduced by half.
33
DC5/6 FEE Design (Plan 2A)
• Wires/per plane:
256+32
– 36 CMADs
– 5 FEMs (1 FEM = 8
CMADs )
– 1 DCM
• no. of plane: 8
– 8 DCM
– 1 GANDALF
• spare modules: 10%
• We will produce 50
FEMs and 10 DCMs.
34
DC5/6 FEE Design (Plan 2B)
• Wires/per plane:
256+32
– 36 CMADs
– 3 FEMs (1 FEM = 16
CMADs )
– 1 DCM
• no. of plane: 8
– 8 DCM
– 1 GANDALF
• spare modules: 10%
• We will produce 30
FEMs and 10 DCMs.
35
2nd FEE Design Plan
To be Decided (3): Shielding
•
We found that DC PCB is the main source of noise and thus the shielding of it is very
important. Copper tape was used for this purpose but the conductivity is not good enough
and difficult to handle. We have the following suggestions:
1) Use multilayer PCB, with top and bottom covered by ground layer. (see PCB cross
section view)
2) Cover bottom PCB by metal shield onto PCB. (see PCB cross section view)
3) making “via” which is the hole connecting the ground of top and bottom PCBs. (see next
slide)
36
1st
FEM
detector
connector
detector PCB
1st FEM
detector
connector
detector PCB
37
2nd FEE Design Plan
To be Decided (3): Shielding
making via which is hole go though top and
bottom ground on the PCB. The EM wave
from outside will be destroyed before
picked up by signal wire.
38
Electronic board with via. This
technique is used for reducing
noise.
SCHEDULE, MANPOWER &
SUMMARY
39
Schedule (1)
Activity
Timeline
FEM
--Design/Layout/Fab (1st prototype)
01/08/2012 – 30/11/2012 (4 mons)
--Test
01/12/2012 – 31/03/2013 (4 mons)
--Package of CMAD Chip
01/04/2013 – 30/04/2013 (1 mons)
--Design/Layout/Fab (2nd prototype)
01/07/2013 – 30/09/2013 (3 mons)
--Test
01/10/2013 – 31/12/2013 (2 mons)
--Design/Layout/Fab (3rd prototype)
01/01/2014 – 28/02/2014 (2 mons)
--Test
01/03/2014 – 31/03/2014 (1 mons)
DCM
40
01/08/2012 – 31/03/2014
01/07/2013 – 31/03/2014
--Design/Layout /Fab (1st prototype)
01/07/2013 – 30/09/2013 (3 mons)
--Test
01/10/2013 – 31/12/2013 (2 mons)
--Design/Layout/Fab (2nd prototype)
01/01/2014 – 28/02/2014 (2 mons)
--Test
01/03/2014 – 31/03/2014 (1 mons)
Schedule (2)
Activity
Timeline
Mass production
01/04/2014 – 31/05/2014 (2 mons)
Final test
01/06/2014 – 30/06/2014 (1 mons)
Delivery of FEE Components to
CERN
01/07/2014 – 31/07/2014 (1 mon)
On-site Installation of DC FEE
01/08/2014 – 30/09/2014 (2 mons)
41
Manpower




Project manager:
Wen-Chen Chang
Engineer:
Ming-Lee Chu (Analog part)
Chih-Hsun Lin (Digital Part)
Postdoc:
Takahiro Sawada (system test and installation)
Graduate student:
Chia-Yu Hsieh (system test and installation)
42
Summary



The performance of 1st FEM prototype matches the specifications in
term of noise level, TDC resolution and gain.
We are surveying the noise of DC system (FEM+PTA) at IPAS.
Some details of the design of 2nd FEM will be decided based on the
outcomes.
Things To Decided:

Separation of Analog and Digital Parts.
Connection scheme with DC5.
Shielding and grounding scheme.

LV power supply, power distribution, regulation and protection.




The 2nd FEM and 1st DCM will be accomplished and tested before
Dec. 2013.
We aim at accomplishing the installation of DC56 FEM by Oct. 2014.
43
Back up
44
Shielded Connector
Male
• The two-- and three-row connectors are
available in 32, 64, and
96 positions.
• Pitch is 2.54 mm.
Female
45
Shielding
AS8D
46
DC PCB Shielding
Side view
(Via)
(Via)
G
S
G
3 rows
connector
Via : go through top and
bottom layer but avoiding
signal wire
Al frame / chamber
Bottom layer (Gnd)
Middle layer (signal)
Bottom layer (Gnd)
Al frame / chamber
Metal hat
47
DC PCB Shielding
Top view
Via
signal
…….
connector
48
FEM board
Optical link
49
DC PCB
Al frame / chamber
exposed copper (Ground)
resistive plane
DC wire layout
resistive plane
exposed copper (Ground)
Al frame / chamber
50
2nd
FEE design
1 FEM = 8 CMADs = 64 ch
1 DCM  4 FEMs  32 CMADs
1 DC  12 DCMs ( 3 lays or each s
2 DCs  24 DCMs 3 Gandalfs
439 mm
DC input
** 16 ch or 32 ch
CMAD
8 ch
CMAD
8 ch
** 8 or 16 CMADs
．．．．．．．．．
CMAD
8 ch
?
mm
?
** Daisy chain
or back plane
Power, I/O
FPGA
TDC
．．．．． FPGA
TDC
** 2 or 4 FPGA-TDC
** Daisy chain
Or back plane
Power, I/O
51
CMAD Chip (Preamplifier/Comparator)
Parameters
Number of Channel
Time resolution (Jitter)
Shaper Peaking time
Processing speed
Linear dynamic range
Noise level
Threshold level
Gain
Gain resolution
Input signal
Output signal
DAC (gain, threshold)
Power consumption
52
CMAD
8
< 1 ns (100 ps)
10-20 ns
> 5 MHz/chan
0 – 900 fC
0.63 fC (threshold 4 fC)
0 – 400 mV (800 mV)
Low: 0.4 mV/fC – 1.2 mV/fC
High: 1.6 mV/fC – 4.8 mV/fC
0.1 mV/fC
Single-end
LVDS
10 bits
< 30 mW /per chan.
DCM board (first prototype)

Xilinx Spartan-6 LXT FPGA: serially controlling and
performing data readout of 4*10 daisy-chained FEM cards.




On-board encoding and buffering scheme.



Maximum data size: 18bits*8chs*40cards=5760 bits.
Transfer speed: 100 Mbps*10 chains
Maximum transfer time per event: 5.76s.
A 256-unit circular memory buffer for recording TDC of hits in
the past 6.6 s. (trigger latency? + longest drifting time 75nsec).
One unit size = 25bits*8chs*40cards=8000 bits, total memory
size 8000*256=256kB.
SFP Optical transceiver:

53
Speed of transmission 3.2 Gbits/sec; < 2.5 sec for per trigger.
(Maximum trigger rate 100kHz 10 sec )
GANDALF boards with optical
mezzanine cards





It receives and re-distributes the “Trigger and Control
System” (TCS) signal into DCM boards.
Different bits in the TCS word are used as triggers, RESET,
begin of spill, end of spill and data enable.
Upon receipt of the trigger, GANDALF will retrieve TDC
data from the DCM boards via 8 channels of 3.2-Gbps
optical link.
Assuming 10% occupancy and 100k trigger rate, the data
flow rate is 18bits/8*2560chs*0.1*100k = 57.6 MB/sec.
These data will be further delivered to the Readout
Buffer via the S-LINK with the data speed of 160 MB/sec.
54