Placement: Hot or Not
Chuck Alpert
Design Productivity Group
Austin Research Laboratory
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
The State of Placement
 Placement is an old problem
 Rajeev: Today, the EDA academic
community is not producing a lot of
new ideas. Yes, at one time they
did, but not today.
 “Lou Scheffer” : place-and-route
is in reasonable shape
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Placement Trends (my guess, not scientific)
Chip gate count: 21 M
Largest Block: 1.5 M
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Chip gate count: 76 M
Largest Block: 3.7 M
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Placement is Hot
 Design sizes are exploding
 Designers are embracing
automation like never before
 Secondary factors (power, area)
become differentiating
 Wirelength is no longer primary
– Congestion
– Timing
– Power
– Clock-friendly
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Generic Design Flow
From Cadence
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Design Productivity Group, Austin Research Laboratory
Vt Optimization?
Swap to lower vt
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Gate Sizing or Repowering
a
d
c
e
b
f
a
b
7
c
d
e
f
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Buffering and Layer Assignment
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Inverter Absorption / Decomposition
a
d
c
b
f
a
b
9
e
e
g
f
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Composition / Decomposition
w
w
x
y
z
x
nd2
B
Out
AOI
Out
nd2
A
nd2
C
y
z
D
nd2
C
D
Courtesy: Louise Trevillian, founder of Logic Synthesis
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Example Timing Closure “Optimization”
Critical Path Optimization
While 500 most critical nets still optimizable
Gate sizing and vt Optimization
Buffering on sub-tree
Buffering on entire tree
Congestion-aware layer assignment
Suite of logic transforms
Compression Optimization
For remaining critical nets
Gate sizing and vt Optimization
Buffering, layer assignment on sub-tree
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
What Timing-Driven Placement Means
Synthesis
Traditional Placement
Optimization
Weight all nets?
If not, what
percent?
What weight
range?
Set Net Weights
Timing-driven Placement
What netlist
state for
timing-driven
placement?
Optimization
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Over Weight Can Destroy Congestion
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Initial
After
Timing-driven
Placement
Optimization
Placement
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Don’t Put Timing into Placement!
Placement
Timing
Timing-driven
Placement Flow
Easy
Constraints
Placement
Incremental
Placement
Constraint
Generation
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Timing
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Example Incremental Timing-Driven Placement
Initial
Final
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Techniques Required for Timing-Driven Placement
 Identification of “easy” constraints
 Incremental Placement
– Shorten critical paths without hurting other paths
– Fast, incremental wirelength recovery
– Congestion-preserving detailed placement (don’t pack!)
– Getting pipeline latches right
 Meaningful timing model
 Interleave optimization (e.g., layer assignment)
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Pipeline Latch Placement
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Pipeline Latch Placement
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Interference From Other Logic
Logic
Logic
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Power-Aware Placement

#nets
Switching Factor
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Congestion Still Huge Problem
 Contests focus on congestion-driven placement
 Also need for incremental congestion repair
 Fast, accurate congestion modeling is key
Placement A
Placement B
Router 1
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Placement A
Placement B
Router 2
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Placement Density Reasonable First Order
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Local Congestion Effects (Pin Density)
Before Spreading
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After Spreading
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Handling Movebounds
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Move Bound Challenges
 Don’t increase runtime
 High density / low
density
 Inclusive or exclusive
 OverlappingSoft or
absolute
 Different shapes
 Support high quantity
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Datapath Placement
net1
net1
LEGAL HPWL = 2385800
Base Run
HPWL = 2513500
SoftLEGAL
Alignment
LEGAL HPWL = 2461745
Forced
Alignment
Courtesy: Sam Ward
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Latch Huddling: Good For Clock Skew and Power
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July 26, 2012
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Why Huddling is Good for Clocks
More Clock Wire
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Less Clock Wire
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
All Object Movement (Before and After Huddling)
movement
(in tracks)
1-50
50-100
100-200
200-500
500+
Global Huddling Placement
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Incremental Huddling Placement
© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Global Clock Trees
Challenge, can we
separate three trees to
prevent routing overlap?
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Proposed Placement Framework
 Keep placement as a stand alone optimization
 Enrich it to handle constraints
 Add constraint generation step to guide placement
– Move bounds
– Power Switching factors
– Tightness of latch huddles
– Clock domain separation
– Use of hierarchical name space
– Alignment of datapath
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Proposed Placement Flow
Pre-Placement
Constraints
Placement (Global or Incremental)
Clock
Analysis
Power
Analysis
Congestion
Analysis
Timing
Analysis
Constraint Generation
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Do We Need to Write a Placer from Scratch?
Clustering
Clustered Global
Flat Global
Pin-Density
Spreading
Density Spreading
Congestion Mitigation
Fast Congestion
Analysis
Congestion-aware
Detailed Placement
Power Reduction
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© 2011 IBM Corporation
Design Productivity Group, Austin Research Laboratory
Chasing the Hot Topics
Instead of trying to
predict the next
important problem
Just ask (a designer)
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© 2011 IBM Corporation