Computer Structure PC Structure and Peripherals Lihu Rappoport and Adi Yoaz 1 Computer Structure 2013 – PC Structure and Peripherals Hard Disks 2 Computer Structure 2013 – PC Structure and Peripherals Hard Disk Structure Rotating platters coated with a magnetic surface Each platter is divided to tracks: concentric circles Each track is divided to sectors • Smallest unit that can be read or written Disk outer tracks have more space for sectors than the inner tracks • Constant bit density: record more sectors on the outer tracks • speed varies with track location Sector Track Moveable read/write head Radial movement to access all tracks Platter rotation to access all sectors Platters Buffer Cache A temporary data storage area used to enhance drive performance 3 Computer Structure 2013 – PC Structure and Peripherals Hard Disk Structure 4 Computer Structure 2013 – PC Structure and Peripherals Disk Access Seek: position the head over the proper track Average: Sum of the time for all possible seek / total # of possible seeks Due to locality of disk reference, actual average seek is shorter: 4 to 12 ms Rotational latency: wait for desired sector to rotate under head The faster the drives spins, the shorter the rotational latency time Most disks rotate at 5,400 to 15,000 RPM • At 7200 RPM: 8 ms per revolution An average latency to the desired information is halfway around the disk • At 7200 RPM: 4 ms Transfer block: read/write the data Transfer time is a function of: sector size, rotation speed, and recording density: bits per inch on a track Typical values: 100 MB / sec Disk Access Time = Seek time + Rotational Latency + Transfer time + Controller Time + Queuing Delay 5 Computer Structure 2013 – PC Structure and Peripherals EIDE Disk Interface EIDE, PATA, UltraATA, ATA 100, ATAPI: all the same interface Uses for connecting hard disk drives and CD/DVD drives 80-pin cable, 40-pin dual header connector 100 MB/s EIDE controller integrated with the motherboard EIDE controller has two channels 6 Primary and a secondary, which work independently Two devices per channel: master and slave, but equal • The 2 devices take turns in controlling the bus If there are two device on the system (e.g., a hard disk and a CD/DVD) • It is better to put them on different channels Avoid mixing slower (DVD) and faster devices (HDD) on the same channel If doing a lot of copying from drive to drive • Better performance by separating devices to separate channels Computer Structure 2013 – PC Structure and Peripherals Disk Interface – Serial ATA (SATA) Point-to-point connection Easier routing, easier installation, better reliability, improved airflow 1/6 the board area compared to EIDE connector 4 wires for signaling + 3 ground to minimize impedance and crosstalk Current HDDs still do not utilize SATA rev 3 BW 7 SATA rev 1: 150 MB/sec SATA rev 2: 300 MB/sec SATA rev 3: 600 MB/sec Thinner (7 wires), flexible, longer cables No master/slave jumper configuration needed when a adding a 2nd SATA drive Increased BW Dedicated BW per device (no sharing) HDD peak (not sustained) gets to 157 MB/s SSD gets to 250 MB/sec Computer Structure 2013 – PC Structure and Peripherals Flash Memory Flash is a non-volatile, rewritable memory NOR Flash Supports per-byte data read and write (random access) • Erasing (setting all the bits) done only at block granularity (64-128KB) • Writing (clearing a bit) can be done at byte granularity Suitable for storing code (e.g. BIOS, cell phone firmware) NAND Flash Supports page-mode read and write (0.5KB – 4KB per page) • Erasing (setting all the bits) done only at block granularity (64-128KB) Suitable for storing large data (e.g. pictures, songs) • Similar to other secondary data storage devices 8 Reduced erase and write times Greater storage density and lower cost per bit Computer Structure 2013 – PC Structure and Peripherals Flash Memory Principles of Operation Information is stored in an array of memory cells In single-level cell (SLC) devices, each cell stores one bit Multi-level cell (MLC) devices store multiple bits per cell using multiple levels of electrical charge Each memory cell is made from a floating-gate transistor Resembles a standard MOSFET, with two gates instead of one • A control gate (CG), as in other MOS transistors, placed on top • A floating gate (FG), interposed between the CG and the MOSFET channel The FG is insulated all around by an oxide layer electrons placed on it are trapped • Under normal conditions, will not discharge for many years When the FG holds a charge, it partially cancels the electric field from the CG • Modifies the cell’s threshold voltage (VT): more voltage has to be applied to the CG to make the channel conduct Read-out: apply a voltage intermediate between the possible threshold voltages to the CG • Test the channel's conductivity by sensing the current flow through the channel • In a MLC device, sense the amount of current flow 9 Computer Structure 2013 – PC Structure and Peripherals Flash Write Endurance Typical number of write cycles SLC MLC NAND flash 100K 1K – 3K NOR flash 100K to 1M 100K Bad block management (BBM) Performed by the device driver software, or by a HW controller • E.g., SD cards include a HW controller perform BBM and wear leveling Map logical block to physical block • Mapping tables stored in dedicated flash blocks or • Each block checked at power-up to create a bad block map in RAM ECC compensates for bits that spontaneously fail 10 Each write is verified, and block is remapped in case of write failure Memory capacity gradually shrinks as more blocks are marked as bad 22 (24) bits of ECC code correct a one bit error in 2048 (4096) data bits If ECC cannot correct the error during read, it may still detect the error Computer Structure 2013 – PC Structure and Peripherals Flash Write Endurance (cont) Wear-leveling algorithms Dynamic wear leveling Map Logical Block Addresses (LBAs) to physical Flash memory addresses Each time a block of data is written, it is written to a new location • Link the new block • Mark original physical block as invalid data • Blocks that never get written remain in the same location Static wear leveling 11 Evenly distribute data across flash memory and move data around Prevent from one portion to wear out faster than another SSD's controller keeps a record of where data is set down on the drive as it is relocated from one portion to another Periodically move blocks which are not written Allow these low usage cells be used by other data Computer Structure 2013 – PC Structure and Peripherals Solid State Drive – SSD Most manufacturers use "burst rate" for Performance numbers Not its steady state or average read rate Any write operation requires an erase followed by the write When SSD is new, NAND flash memory is pre-erased Consumer-grade multi-level cell (MLC) Allows ≥2 bit per flash memory cell Sustains 2,000 to 10,000 write cycles Notably less expensive than SLC drives Enterprise-class single-level cell (SLC) Allows 1 bit per flash memory cell Lasts 10× write cycles of an MLC The more write/erase cycle the shorter the drive's lifespan Use wear-leveling algorithms to evenly distribute writes DRAM cache to buffer data writes to reduce number of write/erase cycles Extra memory cells to be used when blocks of flash memory wear out 12 Computer Structure 2013 – PC Structure and Peripherals SSD (cont.) Data in NAND flash memory organized in fixed size in blocks 13 When any portion of the data on the drive is changed • Mark block for deletion in preparation for the new data • Read current data on the block • Redistribute the old data • Lay down the new data in the old block Old data is rewritten back Typical write amplification is 15 to 20 • For every 1MB of data written to the drive, 15MB to 20MBs of space is actually needed • Using write combining reduces write amplification to ~10% Flash drives compared to HD drives: Smaller size, faster, lighter, noiseless, lower power Withstanding shocks up to 2000 Gs (like 10 foot drop onto concrete) More expensive (cost/byte): ~2$/1GB vs ~0.1$/1GB in HDD Computer Structure 2013 – PC Structure and Peripherals The Motherboard 14 Computer Structure 2013 – PC Structure and Peripherals Computer System Structure – 2009 External Graphics Card HDMI PCI express ×16 CPU BUS LLC Core Core North Bridge (GMCH) On-board Graphics Memory controller DDRII Channel 1 Mem BUS DDRII Channel 2 South Bridge (ICH) PCI express ×1 15 Serial Port Parallel Port IO Controller Floppy Drive keybrd USB IDE SATA controller controller controller mouse Old DVD Drive Hard Disk PCI Sound Card speakers Lan Adap LAN Computer Structure 2013 – PC Structure and Peripherals Computer System – Nehalem External Graphics Card PCI express ×16 DDRIII Cache Channel 1 Mem BUS DDRIII Memory controller Core CPU BUS Core Channel 2 North Bridge On-board Graphics HDMI South Bridge PCI express ×1 16 Serial Port Parallel Port IO Controller Floppy Drive keybrd USB SATA SATA controller controller controller mouse DVD Drive Hard Disk PCI Sound Card speakers Lan Adap LAN Computer Structure 2013 – PC Structure and Peripherals Computer System – Sandy Bridge External Graphics Card PCI express ×16 2133-1066 MHz DDRIII Channel 1 DDRIII Cache Mem BUS Memory controller GFX System Agent Core Channel 2 Line out Line in S/PDIF out S/PDIF in Core Display link Audio Codec 4×DMI South Bridge (PCH) Display port HDMI DVI D-sub BIOS 17 Serial Port Parallel Port Super I/O PCI express ×1 LPC USB Floppy Drive PS/2 keybrd/ mouse exp slots mouse SATA DVD Drive SATA Hard Disk Lan Adap LAN Computer Structure 2013 – PC Structure and Peripherals PCH Connections LPC (Low Pin Count) Bus Supports legacy, low BW I/O devices Typically integrated in a Super I/O chip • Serial and parallel ports, keyboard, mouse, floppy disk controller Other: Trusted Platform Module (TPM), Boot ROM Direct Media Interface (DMI) The link between an Intel north bridge and an Intel south bridge • Replaces the Hub Interface DMI shares many characteristics with PCI-E • Using multiple lanes and differential signaling to form a point-to-point link Most implementations use a ×4 link, providing 10Gb/s in each direction • DMI 2.0 (introduced in 2011) doubles the BW to 20Gb/s with a ×4 link Flexible Display Interface (FDI) Connects the Intel HD Graphics integrated GPU with the PCH south bridge • where display connectors are attached 18 Supports 2 independent 4-bit fixed frequency links/channels/pipes at 2.7GT/s data rate Computer Structure 2013 – PC Structure and Peripherals Motherboard Layout – 1st Gen Core2TM IEEE1394a header audio header PCI express PCI add-in PCI express x1 x16 card connector connector connector Back panel connectors Processor core power connector Rear chassis fan header High Def. Audio header PCI add-in card connector LGA775 processor socket Parallel ATA IDE connector GMCH: North Bridge + integ GFX Processor fan header Speaker Front panel USB header 4 × SATA connectors 19 DIMM Channel A sockets Serial port header DIMM Channel B sockets Diskette drive connector ICH: South Battery Bridge + integ Audio Main Power connector Computer Structure 2013 – PC Structure and Peripherals Motherboard Layout (Sandy Bridge) IEEE1394a header PCI add-in PCI express x1 card connector connector PCI express x16 connector Back panel connectors audio header Processor core power connector High Def. Audio header S/PDIF Rear chassis fan header LGA775 processor socket Processor fan header DIMM Channel A sockets DIMM Channel B sockets Front chassis fan header Chassis intrusion header Front panel USB headers Bios setup config jumper SATA speaker connectorsBattery Main Power PCH connector 20 Serial port header Rear chassis fan header Computer Structure 2013 – PC Structure and Peripherals ASUS Sabertooth P67 B3 Sandy Bridge Motherboard 21 Computer Structure 2013 – PC Structure and Peripherals Motherboard Back Panel Rear Surround USB 2.0 ports eSATA 22 LAN port USB 2.0 ports USB 2.0 ports DVI-I DisplayPort HDMI IEEE 1394A USB 3.0 ports Center / subwoofer Line in S/PDIF Mic in / Side surround Line out/ Front speakers Computer Structure 2013 – PC Structure and Peripherals System Start-up Upon computer turn-on several events occur: 1. The CPU "wakes up" and sends a message to activate the BIOS 2. BIOS runs the Power On Self Test (POST): make sure system devices are working ok 23 Initialize system hardware and chipset registers Initialize power management Test RAM Enable the keyboard Test serial and parallel ports Initialize floppy disk drives and hard disk drive controllers Displays system summary information Computer Structure 2013 – PC Structure and Peripherals System Start-up (cont.) 3. During POST, the BIOS compares the system configuration data obtained from POST with the system information stored on a memory chip located on the MB A CMOS chip, which is updated whenever new system components are added Contains the latest information about system components 4. After the POST tasks are completed the BIOS looks for the boot program responsible for loading the operating system Usually, the BIOS looks on the floppy disk drive A: followed by drive C: 5. After boot program is loaded into memory It loads the system configuration information contained in the registry in a Windows® environment, and device drivers 6. Finally, the operating system is loaded 24 Computer Structure 2013 – PC Structure and Peripherals Backup 25 Computer Structure 2013 – PC Structure and Peripherals Western Digital HDDs Caviar Green 2TB Caviar Blue 1TB Maximum external transfer rate Maximum sustained data rate 300MB/s 126MB/s Average rotational latency Spindle speed Cache size Caviar Black 2TB 138MB/s 4.2 ms 7,200 RPM 7,200 RPM 32MB 64MB Platter size 500GB Areal density 400 Gb/in² Available capacities 2TB Idle power 6.1W 8.2W Read/write power 6.8W 10.7W Idle acoustics 28 dBA 29 dBA Seek acoustics 33dBA 30-34 dBA 26 Computer Structure 2013 – PC Structure and Peripherals HDD Example Performance Specifications Rotational Speed Buffer Size Average Latency Load/unload Cycles 7,200 RPM (nominal) 64 MB 4.20 ms (nominal) 300,000 minimum Buffer To Host (Serial ATA) 6 Gb/s (Max) Formatted Capacity Capacity Interface User Sectors Per Drive 2,000,398 MB 2 TB SATA 6 Gb/s 3,907,029,168 Transfer Rates Physical Specifications Acoustics Idle Mode Seek Mode 0 Seek Mode 3 Current Requirements Power Dissipation Read/Write Idle Standby Sleep 27 29 dBA (average) 34 dBA (average) 30 dBA (average) 10.70 Watts 8.20 Watts 1.30 Watts 1.30 Watts Computer Structure 2013 – PC Structure and Peripherals DDR Comparison DDR Bus clock SDRAM (MHz) Standard 28 Internal rate (MHz) Prefetch (min burst) Transfer Rate (MT/s) Voltage DIMM pins DDR 100–200 100–200 2n 200–400 2.5 184 DDR2 200–533 100–266 4n 400–1066 1.8 240 DDR3 400–1066 100–266 8n 800–2133 1.5 240 Computer Structure 2013 – PC Structure and Peripherals SSD vs HDD Attribute or characteristic Random access time[57] Consistent read performance[61] Solid-state drive Hard disk drive ~0.1 ms 5–10 ms Read performance does not change based on where data is If data is written in a fragmented way, reading back the stored on an SSD data will have varying response times Fragmentation Non-issue due Acoustic levels Mechanical reliability SSDs have no moving parts and make no sound No moving part Files may fragment; periodical defragmentation is required to maintain ultimate performance. Maintenance of temperature Less heat Susceptibility to environmental factors Magneticsusceptibility Weight and size Parallel operation Write longevity Cost per capacity Storage capacity Read/write performance symmetry Free block availability and TRIM Power consumption 29 No flying heads or rotating platters to fail as a result of shock, altitude, or vibration No impact on flash memory Magnets or magnetic surges can alter data on the media very light compared to HDDs Some flash controllers can have multiple flash chips reading HDDs have multiple heads (one per platter) but they are and writing different data simultaneously connected, and share one positioning motor. Flash-based SSDs have a limited number of writes (1-5 Magnetic media do not have a similar limited number of million or more) over the life of the drive. writes but are susceptible to eventual mechanical failure. $.90–2.00 per GB $0.05/GB for 3.5 in and $0.10/GB for 2.5 in drives Typically 4-256GB typically up to 1 – 2 TB Less expensive SSDs typically have write speeds HDDs generally have slightly lower write speeds than their significantly lower than their read speeds. Higher read speeds. performing SSDs have a balanced read and write speed. SSD write performance is significantly impacted by the availability of free, programmable blocks. Previously written HDDs are not affected by free blocks or the operation (or data blocks that are no longer in use can be reclaimed by lack) of the TRIM command TRIM; however, even with TRIM, fewer free, programmable blocks translates into reduced performance.[29][75][76] High performance flash-based SSDs generally require 1/2 to High performance HDDs require 12-18 watts; drives 1/3 the power of HDDs designed for notebook computers are typically 2 watts. Computer Structure 2013 – PC Structure and Peripherals PC Connections Raw bandwidth (Mbit/s) Transfer speed (MB/s) Max. cable length (m) 3,000 300 2 with eSATA HBA (1 with passive adapter) 5 V/12 V[33] SATA revision 3.0 SATA revision 2.0 SATA revision 1.0 PATA 133 SAS 600 SAS 300 SAS 150 6,000 3,000 1,500 1,064 6,000 3,000 1,500 600[34] 300 150[35] 133.5 600 300 150 1 No IEEE 13943200 3,144 393 IEEE 1394800 IEEE 1394400 USB 3.0* USB 2.0 USB 1.0 SCSI Ultra-640 SCSI Ultra-320 Fibre Channel over optic fibre Fibre Channel over copper cable 786 393 5,000 480 12 5,120 2,560 98.25 49.13 400[38] 60 1.5 640 320 10,520 1,000 Name eSATA eSATAp Power provided No 1 (15 with port multiplier) 1 per line 2 0.46 (18 in) No 10 No 1 (>65k with expanders) 15 W, 12–25 V 63 (with hub) 4.5 W, 5 V 2.5 W, 5 V Yes 127 (with hub)[39] No 15 (plus the HBA) No 126 (16,777,216 with switches) 100 (more with special cables) 100[36] 4.5[36][37] 3[39] 5[40] 3 12 2–50,000 4,000 400 12 InfiniBand Quad Rate 10,000 1,000 5 (copper)[41][42]<10,0 00 (fiber) No Thunderbolt 10,000 1,250 100 10 W 30 Devices per channel 1 with point to point Many withswitched fabric 7 Computer Structure 2013 – PC Structure and Peripherals USB USB 2 USB 3 Speed: 480 Mbps 4.8 Gbps Released: April 2000 November 2008 Signaling Method: Polling: either send or receive data (Half duplex) Asynchronous: send and receive data simultaneously (Full duplex) Up to 500 mA Up to 900 mA. Allows better power efficiency with less power for idle states. Can power more devices from one hub. 4 9 Grey in color Blue in color Power Usage: Number of wires within the cable: StandardAConnectors: 31 Computer Structure 2013 – PC Structure and Peripherals