VHDL
1. Define: (1) Delta Delay (2) Transport Delay (3) Routing (4) Placement (5) Postponed
Process
2. Compare Concurrent Signal Assignment with Sequential Signal Assignment .
3. Define : Signal Driver . Discuss effect of Transport Delay and Inertial Delay on Signal
Drivers. Briefly explain Multiple Drivers with it’s problem and solution.
4. Discuss any FSM with appropriate example ,State diagram and VHDL code.
5. List All Data types of VHDL. Explain Scalar Types with syntax and example.
6. Briefly explain All Predefined Operators of VHDL with necessary Example.
7. Write a VHDL code for 4 bit Full adder with neat circuit Diagram ,Truth Table and
Waveforms
8. Write a VHDL code for Ripple counter(Modulo – 16) counter with neat Circuit Diagram,
Truth table and waveforms.
9. Write a VHDL code for 2 x 4 Decoder using Behavioral and Structural style of modeling.
Also draw it’s Circuit Diagram and Truth Table.
10. Write a VHDL code for 9 bit Parity Generator with Circuit Diagram and logic equation.
11. List down the advantages and disadvantages of Finite State Machines.
12. Write a VHDL code for 4-Bit Parallel-In-Serial-Out Shift Register.
13. Realize the following functions using PLA.
8,10,14,15 )
14. Write a VHDL Code for 4 – Bit full – adder. Use structural modeling style. Take 1- Bit
full adder as a component.
15. Define Mealy State Machine and Moore State Machine.Compare them.
16. Explain Process statement. Explain the importance of sensitivity list. Quote suitable
example.
17. Explain basic data types in VHDL.
18. Explain Assertion statement. Explain its usefulness in writing testbench.
19. What do you mean by Delta-delay ? Also explain Inertial Delay model and Transport
Delay model.
20. Write a short note on operators used in VHDL.
21. Write the VHDL code for the 4 to 16 decoder using behavioral style of modeling.
22. Do as directed:
23. (1) Whether following statement is true or false. “Nested process statements are possible
in VHDL”. Also justify your answer.
(2) List all different subtypes of scalar data types in VHDL.
(3) Discuss necessity of resolution function.
24. Explain Inertial Delay model with suitable example. Also summaries effect of Inertial
Delay on Signal Drivers.
25. (1) Compare Signal and Variable in VHDL (2) Discuss Block statement in VHDL
26. Define the following terms:
1. Configuration declaration in VHDL 2. Transport Delay Model
3. Sequential Signal assignment statements 4. Component Instantiation
27. Write the VHDL code using structural model for a 9-bit parity generator circuit.
28. List the main purposes of test-bench. Discuss waveform generation using test-bench.
29. Discuss modeling of mealy state machine with suitable example.
30. Do as directed:
(1) Differentiate between exit and next statements.
(2) Briefly describe necessity of Configuration.
(3) Elaborate Package declaration
31. Explain following operators used in VHDL with example
(1) rem (2) mod (3) abs
32. Briefly describe implicit and explicit visibility in VHDL.
33. How many functions of how many variables can be realized by a PLA with n inputs and
m outputs?
Realize the following functions using PLA.
F1 = Σm( 0,1,4,6)
F2 = Σm( 2,3,4,6,7)
F3 = Σm(0,1,2,6)
F4 = Σm(2,3,5,6,7)
34. Write VHDL codes using WHEN-ELSE statement for following circuits:
1. 4-to-2 priority encoder
2. Four-bit comparator
35. Write a VHDL code using behavioral description for four-bit shift register
which has following features: 1. Parallel load, 2. Left shift, and 3. Right shift.
36. Draw a state diagram for Moore type finite state machine (FSM) which
generates output ‘1’ when it receives input ‘1’ on two subsequent clock cycles.
Include reset signal which brings FSM to initial state when it goes high. Write
VHDL code for this FSM using process statement.
37. Explain configuration and package declaration statements using necessary
examples.
38. Explain various versions of wait statements. What will be the effect of including ‘wait for
0 ns’ statement within the middle of process statement which has signal assignments
statements before and after this wait statement? Explain with appropriate example.
39. Discuss assertion statement and write a VHDL code for rising edge triggered
D flip-flop with a check on setup and hold times to demonstrate application of
this statement.
40. List out uses of block statement and explain each of them in detail with appropriate
statements.
41. Explain inertial and transport delay models with necessary examples.
42. Demonstrate the use of generic and FOR-LOOP statements by writing a
VHDL code for n-input NAND gate.
43. Give general structure of writing a test bench in VHDL. Write a test bench to
generate D and clock inputs for D flip-flop. Assume VHDL code for D flipflop
is available. How do you limit simulation time?
44. Write a VHDL program for n-bit adder using structural description by
instantiating one-bit adder circuit. Program for one-bit adder must be given.
45. Write a behavioral VHDL code for four-bit counter with parallel load. Use
INTEGER data type for signals.
46. Write a behavioral VHDL code for two-digit BCD counter.
47. List the major capabilities of VHDL along with the features that differentiate
it from other hardware description languages.
48. Explain VHDL terms: Configuration, Package, Generic and Process.
49. Write True or False. If statement is true justify it and if false correct it.
(i) The order of execution of concurrent VHDL statements cannot be predicted.
(ii) The statement a<=b after 5 ns; is synthesized as a delay line of 5 ns.
(iii) One entity may be assigned to many architecture bodies.
(iv) We cannot mix structural and data flow description in the same
architecture unit.
(v) Structural style is closer to human thinking than behavioral style.
(vi) Every signal in a sensitivity list of a statement must change to fire the
statement.
(vii) RTL style describes combinational logic.
50. Compare Inertial and Transport delay with suitable examples and
explain Inertial Delay Model.
51. What is Delta-delay? What is its effect in VHDL?
52. Differentiate between concurrent and sequential signal assignment
statement. State concurrent assignment problem.
53. Write VHDL code using behavioral modeling along with test bench for a
positive edge-triggered D flip-flop entity. The description should be based on
a procedure declared in a package. The procedure has the following signals:
d IN std logic
clk IN std logic
q OUT std logic
54. Explain data types used in VHDL. List all possible level that can be assigned to
std_logic data type.
55. Design an N-bit parity generator using an XOR gate in a generate statement.
Value of N should be passed as a generic parameter with a default value of 8.
Use structural modeling style.
56. Summarize VHDL attributes. What is the use of FOREIGN attribute in VHDL?
57. Write VHDL code for a priority encoder using
(i) Conditional assignment statement
(ii) Selected assignment statement
Use dataflow style of description.
58. Write a VHDL code to generate clock with ON period of 15 ns and
OFF period of 25 ns.
59. Define function overloading & operator overloading.
60. Write VHDL code for 1K X 8 RAM with separate input and output buses.
61. Explain modeling of finite state machines. Also compare Moore state
machines and Mealy state machines.
62. Write the code for an 8-bit Mobius counter. It is an 8-bit shift register where the bits 0
and 1 are XOR’ed and fed to the left serial input at the bit 7. The reset signal should
initialize the counter to any state other than “0000”. Verify that counter cycles through 15
states and then returns to the initial state. Create a test bench which directly instantiates
this counter and generate clock and reset signals.
63. How to write a test bench? Give typical test bench format.
.