Background Statement for SEMI Draft Document 5744
LINE ITEM REVISION TO SEMI M49-1014
GUIDE FOR SPECIFYING GEOMETRY MEASUREMENT SYSTEMS
FOR SILICON WAFERS FOR THE 130 nm TO 16 nm TECHNOLOGY
GENERATIONS
Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in
reaching an informed decision based on the rationale of the activity that preceded the creation of this document.
Notice: Recipients of this document are invited to submit, with their comments, notification of any relevant patented
technology or copyrighted items of which they are aware and to provide supporting documentation. In this context,
“patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter
case, only publicly available information on the contents of the patent application is to be provided.
Background:
Along with advanced technology, wafer geometry values are being more critical. Recent discussion for edge
exclusion reduction and scribe fiducial marks for 450mm notchless wafer, Wafer ID and/or fiducial mark may be
possible to impact to wafer geometry evaluation. Therefore M49, specification for geometry measurement system,
need to clarify to adopt exclusion area or exclusion windows. Unfortunately current description of these area are not
clear and to be revise current version.
According to the SEMI Procedure Manual section 3.4.3.3.1, a Line-item Ballot should include the purpose, scope,
limitations (if present), and terminology (if present) sections, along with the full text of any section to which
revisions are being balloted.
This document covers a single line item.
Line Item 1: Add more specific description for exclusion area at section 5.5.22, and removal of
section 3.4 on table 3 and table 4 to prevent duplication. Also correct the error in the table 2.
Notice: Additions are indicated by underline and deletions are indicated by strikethrough.
Review and Adjudication Information
Group:
Date:
Time & Timezone:
Location:
City, State/Country:
Leader(s):
Standards Staff:
Task Force Review
Int’l Advanced Wafer Geometry TF
Monday, July 13, 2015
2:00 PM -5:00 PM PDT
San Francisco Marriott Marquis
San Francisco, CA USA
Noel Poduje (SMS)
Jaydeep Sinha (KLA-Tencor)
M Yoshise (Self)
Kevin Nguyen, knguyen@semi.org
Committee Adjudication
NA Silicon Wafer TC Chapter
Tuesday, July 14, 2015
1:00 PM -4:00 PM PDT
San Francisco Marriott Marquis
San Francisco, CA USA
Noel Poduje (SMS)
Dinesh Gupta (STA)
Kevin Nguyen, knguyen@semi.org
This meeting’s details are subject to change, and additional review sessions may be scheduled if necessary. Contact the task
force leaders or Standards staff for confirmation.
Telephone and web information will be distributed to interested parties as the meeting date approaches. If you will not be able to
attend these meetings in person but would like to participate by telephone/web, please contact Standards staff.
Check www.semi.org/standards on calendar of event for the latest meeting schedule.
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
SEMI Draft Document 5744
LINE ITEM REVISION TO SEMI M49-1014
GUIDE FOR SPECIFYING GEOMETRY MEASUREMENT SYSTEMS
FOR SILICON WAFERS FOR THE 130 nm TO 16 nm TECHNOLOGY
GENERATIONS
Notice: Additions are indicated by underline and deletions are indicated by strikethrough.
Line Item 1: Add more specific description for exclusion area at section 5.5.22, and removal of
section 3.4 on table 3 and table 4 to prevent duplication. Also correct the error in the table 2.
1 Purpose
1.1 This Guide provides recommendations for specifying measurement systems for geometry and flatness of silicon
wafers of the 130, 90, 65, 45, 32, 22, and 16 nm technology generation as anticipated by the International
Technology Roadmap for Semiconductors (ITRS) and in the forecasts of the major manufacturers of semiconductor
devices. Wafer parameters as defined by SEMI M1, SEMI M8, SEMI M11, SEMI M24, or SEMI M38 are specified
by customers of silicon wafer suppliers and are usually part of Certificates of Compliance. Suppliers of silicon
wafers and their customers might measure these parameters using equipment provided by different manufacturers of
such equipment or using different generations of equipment of one supplier. Agreement on basic features and
capability of such measurement systems improves data exchange and interpretation of data as well as procurement
of appropriate measurement systems.
2 Scope
2.1 This Guide outlines and recommends basic specifications for systems for measuring geometry and flatness of
silicon wafers of the 130, 90, 65, 45, 32, 22, and 16 nm technology generation.
2.2 This Guide applies to measurement systems used for verifying the quality parameters geometry and flatness in
large scale production of bare polished or epitaxial silicon wafers the backside of which may be acid etched and/or
covered by unpatterned, homogeneous layers of, for example, poly-Si or low temperature oxide (LTO). Artifacts
(e.g., reference materials) for calibrating a measurement system might have different properties.
2.3 This Guide also applies to measurement systems that provide only a subset of the measurement features
outlined in this Guide.
2.4 The Guide does not apply to measurement systems used to control intermediate process steps during Si wafer
manufacturing. However, it may be completely or partly used for measurement systems for those applications
provided corresponding constraints are appropriately identified.
2.5 The Guide also does not apply to measurement systems for SOI wafers or patterned wafers.
NOTICE: SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their
use. It is the responsibility of the users of the Documents to establish appropriate safety and health practices, and
determine the applicability of regulatory or other limitations prior to use.
3 Referenced Standards and Documents
……
4 Terminology
4.1 General terms, acronyms, abbreviations and symbols associated with silicon technology and used in this
Standard are listed and defined in SEMI M59.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
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Phone: 408.943.6900, Fax: 408.943.7943
5 Recommended Specification for Geometry Measurement Systems for Silicon Wafers
…
5.1.21 The quality of a correlation between different measurement systems is not specified in this Guide.
5.1.22 Exclusion areas are on the wafer surface, inside of or intersecting the FQA boundary, within which
measurement data is not acquired and/or is not used in the calculation of metrics. The areas are;
 Wafer identification marks (Alphanumeric and/or T7)
 Inscribe fiducial marks for 450mm notchless wafers
 Fiducial notch
5.1.22.1 These areas are excluded because the wafer quality within the area is exempt from specification. The
locations of defined areas are as specified in the relevant identification mark or wafer specification (T7, M1). The
extent of defined areas may be machine-dependent and are mutually agreed upon between suppliers and users.
5.1.22.2 The equipment specified areas such as wafer handling contacts are mutually discussed between suppliers
and users for both extent and location, if necessary.
5.1.22.3 The total extent exclusion windows are not to exceed 0.1% of FQA area.
Table 1 Generic Equipment Characteristics
….
Table 2 Materials to be Measured
Item
Recommended Specification
Comments
References
1 WAFERS
monocrystalline, unpatterned
silicon wafers with layers as
specified in Table 2, Item 1.3.4
SEMI M1
(SEMI M8)
(SEMI M11)
1.2.1 Wafer Diameter
200 or 300 or 450 or 200 and
300 and 450 mm nominal
SEMI M1
SEMI MF2074
DIN 50441-4
1.2.2 Wafer Thickness
200 mm wafers: 600–850 µm,
300 mm wafers: 650–850 µm
450 mm wafers: 800–1000 µm
1.1 Kind of Wafers
1.2 Wafer Characteristics – dimensional
See note #1,#2
SEMI MF1530
DIN 50441-1
rounded
SEMI M1
DIN 50441-2
SEMI MF928
1.2.4 Wafer Shape Range
200 mm wafers: warp ≤100 µm,
300 mm wafers: warp ≤200 µm
450 mm wafers: warp ≤150 µm
SEMI M1
SEMI MF1390
DIN 50441-5
1.2.5 Fiducial
200 mm wafers: notch or flat
300 and 450 mm wafers: notch
450 mm notchless wafers: back
surface inscribe fiducial marks
SEMI M1
SEMI MF671
SEMI MF1152
(DIN 50441-4)
1.2.3 Edge Shape
1.2.6 ID Mark(s)
200 mm wafers: customer specific content, type location
of ID mark to be
specified
300 and 450 mm wafers:
according to SEMI Standards
¶ 6.5.1 of SEMI M1
¶ 6.5.1.4 of SEMI M1
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Recommended Specification
Comments
References
1.3 Wafer Characteristics – electrical, optical
0.5 m Ω·cm – intrinsic, p-, n-type
1.3.1 Electrical Resistivity of Wafers,
Conductivity Type
1.3.2 Thermal Donors
Res: SEMI MF673
DIN 50445
SEMI MF84
DIN 50431
Type: SEMI MF42 or
DIN 50432
annealed and not annealed
no effect with respect to
measurement
1.3.3 Wafer Charge
1.3.4 Layers (LTO, poly-Si), Epi
LTO: thickness: 150–900 nm
uniformity: ≤10%
poly-Si: thickness: ≤2 µm
uniformity: <20%
Epitaxial layer: customer specific
1.3.5 Wafer Surface Conditions
front surface: polished, annealed, optional conditions of
or epitaxial layer
both surfaces: etched,
back surface: polished, acid and/or
lapped, as cut
caustic etched, layers according to
Item 1.3.4
#1 Note that the thickness and shape ranges specified in Table 2 are intended to specify the full operating range of the equipment. This range is
significantly wider than that of normal prime wafers and first reclaim wafers. Wafer parameter values for performance verification are specified
in ¶ 5.5.17 and Tables 3 and 4. Performance of the measurement system as outlined in Tables 3 and 4 might be reduced for wafers with other
thickness and shape values. The shape range given for 300 mm wafers, 200 μm, was established for measurement systems (e.g., capacitancebased) suitable for the 130 nm to 65 nm technology nodes. Systems (e.g., interferometer-based) with performance capability suitable for more
advanced technology nodes (i.e., 45 nm and smaller) may have a reduced shape range (e.g., 100 μm) for 300 mm wafers.
#2 Applications for other wafers (e.g., multiple reclaim, process development, special applications) may require other ranges which should be
agreed upon between supplier and user.
Table 3 Metrology Specific Equipment Characteristics for 130, 90, and 65 nm Technology Generations
Item
Recommended Specification
Technology Generation
Grade
90 nm#1
130 nm
A
B
A
65 nm#1
B
A
Comments and References
B
3. SETUP PARAMETERS
Table 4 Metrology Specific Equipment Characteristics for 45, 32, 22, and 16 nm Technology Generations
45 nm Node
32 nm Node
22 nm Node
16 nm Node
Nominal
Nominal
Nominal
Nominal
Property
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Document Number: 5744
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Phone: 408.943.6900, Fax: 408.943.7943
NOTICE: SEMI makes no warranties or representations as to the suitability of the Standards and Safety Guidelines
set forth herein for any particular application. The determination of the suitability of the Standard or Safety
Guideline is solely the responsibility of the user. Users are cautioned to refer to manufacturer’s instructions, product
labels, product data sheets, and other relevant literature, respecting any materials or equipment mentioned herein.
Standards and Safety Guidelines are subject to change without notice.
The user’s attention is called to the possibility that compliance with this Standard or Safety Guideline may require
use of copyrighted material or of an invention covered by patent rights. KLA-Tencor has filed a statement with
SEMI asserting that licenses will be made available to applicants throughout the world for the purpose of
implementing this Standard or Safety Guideline without unfair discrimination. Attention is also drawn to the
possibility that some elements of this Standard or Safety Guideline may be subject to patented technology or
copyrighted items other than those identified above. SEMI shall not be held responsible for identifying any or all
such patented technology or copyrighted items. By publication of this Standard or Safety Guideline, SEMI takes no
position respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in
this Standard or Safety Guideline. Users of this Standard or Safety Guideline are expressly advised that
determination of any such patent rights or copyrights and the risk of infringement of such rights are entirely their
own responsibility.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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