Lecture 24
Dynamic Logic
Mar. 10, 2003
Modern VLSI Design 3e: Chapters 3 & 5
week10-1
Partly from 2002 Prentice Hall PTR
Topics
Pseudo-nMOS gates.
 DCVS logic.
 Domino gates.

Modern VLSI Design 3e: Chapters 3 & 5
week10-2
Partly from 2002 Prentice Hall PTR
Pseudo-nMOS

Uses a p-type as a resistive pullup, n-type
network for pulldowns.
Modern VLSI Design 3e: Chapters 3 & 5
week10-3
Partly from 2002 Prentice Hall PTR
Characteristics
Consumes static power.
 Has much smaller pullup network than
static gate.
 Pulldown time is longer because pullup is
fighting.

Modern VLSI Design 3e: Chapters 3 & 5
week10-4
Partly from 2002 Prentice Hall PTR
Output voltages
Logic 1 output is always at VDD.
 Logic 0 output is above Vss.
 VOL = 0.25 (VDD - VSS) is one plausible
choice.

Modern VLSI Design 3e: Chapters 3 & 5
week10-5
Partly from 2002 Prentice Hall PTR
Producing output voltages
For logic 0 output, pullup and pulldown
form a voltage divider.
 Must choose n, p transistor sizes to create
effective resistances of the required ratio.
 Effective resistance of pulldown network
must be comptued in worst case—series ntypes means larger transistors.

Modern VLSI Design 3e: Chapters 3 & 5
week10-6
Partly from 2002 Prentice Hall PTR
Transistor ratio calculation

In steady state logic 0 output:
– pullup is in linear region,Vds = Vout - (VDD VSS) ;
– pulldown is in saturation.

Pullup and pulldown have same current
flowing through them.
Modern VLSI Design 3e: Chapters 3 & 5
week10-7
Partly from 2002 Prentice Hall PTR
Transistor ratio, cont’d.

Equate two currents:
– Idp = Idd.

Using 0.5 mm parameters, 3.3V power
supply:
– Wp/Lp / Wn/Ln = 3.9.
Modern VLSI Design 3e: Chapters 3 & 5
week10-8
Partly from 2002 Prentice Hall PTR
DCVS logic
DCVSL = differential cascode voltage
logic.
 Static logic—consumes no dynamic power.
 Uses latch to compute output quickly.
 Requires true/complement inputs, produces
true/complement outputs.

Modern VLSI Design 3e: Chapters 3 & 5
week10-9
Partly from 2002 Prentice Hall PTR
DCVS structure
Modern VLSI Design 3e: Chapters 3 & 5
week10-10
Partly from 2002 Prentice Hall PTR
DCVS operation
Exactly one of true/complement pulldown
networks will complete a path to the power
supply.
 Pulldown network will lower output
voltage, turning on other p-type, which also
turns off p-type for node which is going
down.

Modern VLSI Design 3e: Chapters 3 & 5
week10-11
Partly from 2002 Prentice Hall PTR
DCVS example
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Precharged logic
Precharged logic uses stored charge to help
evaluation.
 Precharge node, selectively discharge it.
 Take advantage of higher speed of n-types.
 Requires multiple phases for evaluation.

Modern VLSI Design 3e: Chapters 3 & 5
week10-13
Partly from 2002 Prentice Hall PTR
Domino logic

Uses precharge clock to compute output in
two phases:
– precharge;
– evaluate.

Is not a complete logic family—cannot
invert.
Modern VLSI Design 3e: Chapters 3 & 5
week10-14
Partly from 2002 Prentice Hall PTR
Domino gate structure
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Domino phases
Controlled by clock .
 Precharge: p-type pullup precharges the
storage node; inverter ensures that output
goes low.
 Evaluate: storage node may be pulled down,
so output goes up.

Modern VLSI Design 3e: Chapters 3 & 5
week10-16
Partly from 2002 Prentice Hall PTR
Domino buffer

Output inverter is needed for two reasons:
– make sure that outputs start low, go high so that
domino output can be connected to another
domino gate;
– protects storage node from outside influence.
Modern VLSI Design 3e: Chapters 3 & 5
week10-17
Partly from 2002 Prentice Hall PTR
Domino operation
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Domino effect
Gate outputs fall in sequence:
gate 1
Modern VLSI Design 3e: Chapters 3 & 5
gate 2
week10-19
gate 3
Partly from 2002 Prentice Hall PTR
Monotonicity

Domino gates inputs must be monotonically
increasing: glitch causes storage node to
discharge.
Modern VLSI Design 3e: Chapters 3 & 5
week10-20
Partly from 2002 Prentice Hall PTR
Output buffer

Inverting buffer isolates storage node.
Storage node and inverter have correlated
values.
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Using domino logic

Can rewrite logic expression using De
Morgan’s Laws:
– (a + b)’ = a’b’
– (ab)’ = a’ + b’

Add inverters to network inputs/outputs as
required.
Modern VLSI Design 3e: Chapters 3 & 5
week10-22
Partly from 2002 Prentice Hall PTR
Domino and stored charge
Charge can be stored in source/drain
connections between pulldowns.
 Stored charge can be sufficient to affect
precharge node.
 Can be averted by precharging the internal
pulldown network nodes along with the
precharge node.

Modern VLSI Design 3e: Chapters 3 & 5
week10-23
Partly from 2002 Prentice Hall PTR
Example 1
Modern VLSI Design 3e: Chapters 3 & 5
week10-24
Partly from 2002 Prentice Hall PTR
Lecture 25
RC Transmission Line
Mar. 12, 2003
Modern VLSI Design 3e: Chapters 3 & 5
week10-25
Partly from 2002 Prentice Hall PTR
Topics
Wire delay.
 Buffer insertion.
 Crosstalk.
 Inductive interconnect.

Modern VLSI Design 3e: Chapters 3 & 5
week10-26
Partly from 2002 Prentice Hall PTR
Wire delay
Wires have parasitic resistance, capacitance.
 Parasitics start to dominate in deepsubmicron wires.
 Distributed RC introduces time of flight
along wire into gate-to-gate delay.

Modern VLSI Design 3e: Chapters 3 & 5
week10-27
Partly from 2002 Prentice Hall PTR
RC transmission line
Assumes that dominant capacitive coupling
is to ground, inductance can be ignored.
 Elemental values are ri, ci.

Modern VLSI Design 3e: Chapters 3 & 5
week10-28
Partly from 2002 Prentice Hall PTR
RC trees
Generalization of RC transmission line.
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
RC crosstalk
Crosstalk slows down signals---increases
settling noise.
 Two nets in analysis:

– aggressor net causes interference;
– victim net is interfered with.
Modern VLSI Design 3e: Chapters 3 & 5
week10-30
Partly from 2002 Prentice Hall PTR
Crosstalk delay
There is an optimum wire width for any
given wire spacing---at bottom of U curve.
 Optimium width increases as spacing
between wires increases.

Modern VLSI Design 3e: Chapters 3 & 5
week10-31
Partly from 2002 Prentice Hall PTR
Example 2
Modern VLSI Design 3e: Chapters 3 & 5
week10-32
Partly from 2002 Prentice Hall PTR
Lecture 26
Sequencial Logic
Mar. 14, 2003
Modern VLSI Design 3e: Chapters 3 & 5
week10-33
Partly from 2002 Prentice Hall PTR
Topics
Memory elements.
 Basics of sequential machines.

Modern VLSI Design 3e: Chapters 3 & 5
week10-34
Partly from 2002 Prentice Hall PTR
Memory elements
Stores a value as controlled by clock.
 May have load signal, etc.
 In CMOS, memory is created by:

– capacitance (dynamic);
– feedback (static).
Modern VLSI Design 3e: Chapters 3 & 5
week10-35
Partly from 2002 Prentice Hall PTR
Variations in memory elements
Form of required clock signal.
 How behavior of data input around clock
affects the stored value.
 When the stored value is presented to the
output.
 Whether there is ever a combinational path
from input to output.

Modern VLSI Design 3e: Chapters 3 & 5
week10-36
Partly from 2002 Prentice Hall PTR
Memory element terminology
Latch: transparent when internal memory is
being set from input.
 Flip-flop: not transparent—reading input
and changing output are separate events.

Modern VLSI Design 3e: Chapters 3 & 5
week10-37
Partly from 2002 Prentice Hall PTR
Clock terminology
Clock edge: rising or falling transition.
 Duty cycle: fraction of clock period for
which clock is active (e.g., for active-low
clock, fraction of time clock is 0).

Modern VLSI Design 3e: Chapters 3 & 5
week10-38
Partly from 2002 Prentice Hall PTR
Memory element parameters
Setup time: time before clock during which
data input must be stable.
 Hold time: time after clock event for which
data input must remain stable.

clock
data
Modern VLSI Design 3e: Chapters 3 & 5
week10-39
Partly from 2002 Prentice Hall PTR
Dynamic latch
Stores charge on inverter gate capacitance:
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Latch characteristics
Uses complementary transmission gate to
ensure that storage node is always strongly
driven.
 Latch is transparent when transmission gate
is closed.
 Storage capacitance comes primarily from
inverter gate capacitance.

Modern VLSI Design 3e: Chapters 3 & 5
week10-41
Partly from 2002 Prentice Hall PTR
Latch operation
 = 0: transmission gate is off, inverter
output is determined by storage node.
  = 1: transmission gate is on, inverter
output follows D input.
 Setup and hold times determined by
transmission gate—must ensure that value
stored on transmission gate is solid.

Modern VLSI Design 3e: Chapters 3 & 5
week10-42
Partly from 2002 Prentice Hall PTR
Stored charge leakage
Stored charge leaks away due to reversebias leakage current.
 Stored value is good for about 1 ms.
 Value must be rewritten to be valid.
 If not loaded every cycle, must ensure that
latch is loaded often enough to keep data
valid.

Modern VLSI Design 3e: Chapters 3 & 5
week10-43
Partly from 2002 Prentice Hall PTR
Stick diagram
VDD
Q’
D
VSS

Modern VLSI Design 3e: Chapters 3 & 5
’
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Layout
VDD
Q’
D
VSS

Modern VLSI Design 3e: Chapters 3 & 5
’
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Partly from 2002 Prentice Hall PTR
Multiplexer dynamic latch
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Non-dynamic latches
Must use feedback to restore value.
 Some latches are static on one phase
(pseudo-static)—load on one phase, activate
feedback on other phase.

Modern VLSI Design 3e: Chapters 3 & 5
week10-47
Partly from 2002 Prentice Hall PTR
Flip-flops
Not transparent—use multiple storage
elements to isolate output from input.
 Major varieties:

– master-slave;
– edge-triggered.
Modern VLSI Design 3e: Chapters 3 & 5
week10-48
Partly from 2002 Prentice Hall PTR
Master-slave flip-flop
master
slave
D
Q

Modern VLSI Design 3e: Chapters 3 & 5
week10-49
Partly from 2002 Prentice Hall PTR
Master-slave operation
 = 0: master latch is disabled; slave latch is
enabled, but master latch output is stable, so
output does not change.
  = 1: master latch is enabled, loading value
from input; slave latch is disabled,
maintaining old output value.

Modern VLSI Design 3e: Chapters 3 & 5
week10-50
Partly from 2002 Prentice Hall PTR
Sequential machines
Use memory elements to make primary
output values depend on state + primary
inputs.
 Varieties:

– Mealy—outputs function of present state,
inputs;
– Moore—outputs depend only on state.
Modern VLSI Design 3e: Chapters 3 & 5
week10-51
Partly from 2002 Prentice Hall PTR
Sequential machine definition
Machine computes next state N, primary
outputs O from current state S, primary
inputs I.
 Next-state function:

– N = (I,S).

Output function (Mealy):
– O = (I,S).
Modern VLSI Design 3e: Chapters 3 & 5
week10-52
Partly from 2002 Prentice Hall PTR
FSM structure
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Constraints on structure
No combinational cycles.
 All components must have bounded delay.

Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Signal skew
Machine data signals must obey setup and
hold times—avoid signal skew.
Modern VLSI Design 3e: Chapters 3 & 5
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Clock skew
Clock must arrive at all memory elements in
time to load data.
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapters 3 & 5
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Partly from 2002 Prentice Hall PTR