Chapter 2
Instructions: Language
of the Computer
Instructions:





Language of the Machine
Instruction set: the vocabulary of commands understood
by a given architecture.
More primitive than higher level languages
e.g., no sophisticated control flow
Very restrictive
e.g., MIPS Arithmetic Instructions
We’ll be working with the MIPS instruction set
architecture



similar to other architectures developed since the 1980's
used by NEC, Nintendo, Silicon Graphics, Sony
Design goals: maximize performance and minimize cost,
reduce design time
MIPS arithmetic



Operations and Operands
All instructions have 3 operands
Need to break a C statement into several assembly
instructions
add t0,g,h
add t1,i,j
( f = (g + h) – ( I + j))
sub f,t0,t1

Operand order is fixed (destination first)
Example:
C code:
A = B + C
MIPS code: add $s0, $s1, $s2
(associated with variables by compiler)
MIPS arithmetic



Design Principle 1: simplicity favors
regularity. Why?
Of course this complicates some things...
C code:
A = B + C + D;
E = F - A;
MIPS code:
add $t0, $s1, $s2
add $s0, $t0, $s3
sub $s4, $s5, $s0
Operands must be registers, only 32 registers
provided
Registers vs. Memory




Design Principle 2: smaller is faster.
Why?
Arithmetic instructions operands must be
registers,
— only 32 registers provided
Compiler associates variables with registers
What about programs with lots of variables?
Memory Organization



Viewed as a large, single-dimension array,
with an address.
A memory address is an index into the array
"Byte addressing" means that the index
0
points to a byte of memory.
8 bits of data
1
2
3
4
5
6
...
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
Memory Organization
0
4
8
12
...





32 bits of data
32 bits of data
32 bits of data
Registers hold 32 bits of data
32 bits of data
Bytes are nice, but most data items use larger "words"
For MIPS, a word is 32 bits or 4 bytes.
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8, ... 232-4
Words are aligned
i.e., what are the least 2 significant bits of a word
address?
Instructions


Load and store instructions
Example:
C code:
A[8] = h + A[8];
MIPS code:


lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 32($s3)
Store word has destination last
Remember arithmetic operands are registers,
not memory!
Another Example

What is the MIPS assembly code for
A[12] = h + A[8]
assuming that h is associated with register
$s2 and the base address of the array A is in
$s3?
lw
$t0,32($s3) # temporary reg $t0 gets A[8]
add $t0,$s2,$t0 # $t0 gets h + A[8]
sw $t0,48($s3) # stores h + A[8] into A[12]
Constants


Small constants are used quite frequently
(50% of operands)
e.g., A = A + 5;
B = B + 1;
C = C - 18;
Solutions? Why not?


put 'typical constants' in memory and load them.
create hard-wired registers (like $zero) for
constants like one.
3
Constants (cont’d)

MIPS Instructions:
addi $s3, $s3, 4
slti $s1, $t1, 10
andi $s3, $s3, 6
ori $s3, $s3, 4

Design Principle 3: Make the common case
fast.
So far we’ve learned: (p.59)

MIPS
— loading words but addressing bytes
— arithmetic on registers only

Instruction
Meaning
add $s1, $s2, $s3
sub $s1, $s2, $s3
addi $s1, $s2,100
lw $s1, 100($s2)
sw $s1, 100($s2)
$s1 = $s2 + $s3
$s1 = $s2 – $s3
$s1 = $s2 + 100
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
Machine Language

Instructions, like registers and words of data,
are also 32 bits long


Example: add $t0, $s1, $s2
Registers have numbers, $t0=8, $s1=17,
$s2=18
000000 10001 10010

00000
100000
shamt
funct
Instruction Format:
op

01000
rs
rt
rd
Can you guess what the field names stand for?
MIPS Fields
R-type
 op: basic operation of the instruction, or
opcode (6 bits)
 rs: the first register source operand (5 bits)
 rt: the second register source operand (5 bits)
 rd: the register destination operand (5 bits)
 shamt: shift amount (5 bits)
 funct: function code (6 bits)
Machine Language

Consider the load-word and store-word
instructions,


What would the regularity principle have us do?
New principle: Good design demands good
compromises.
I-Type Instruction




Introduce a new type of instruction format
 I-type for data transfer instructions
 other format was R-type for register
Example: lw $t0, 32($s2)
35
18
8
op
rs
rt
32
16 bit number
Another example: addi (R-type or I-Type?)
Where's the compromise?
Translating MIPS Assembly Language
into Machine Language(p 65-66)

Example (Figure 2.6 MIPS Instruction
Encoding)
A[300] = h + A[300]
lw $t0,1200($t1)
add $t0,$s2,$t0
sw $t0,1200($t1)
MIPS Instruction Encoding: MIPS Reference Data Card
Stored Program Concept



Instructions are bits
Programs are stored in memory
— to be read or written just like data
Fetch & Execute Cycle



Instructions are fetched and put into a special
register
Bits in the register "control" the subsequent
actions
Fetch the “next” instruction and continue
Logical Operations

Useful to operate on fields of bits within a word or
on individual bits.
Logical
operations
C operators
Java
operators
MIPS
Shift left
<<
<<
sll
Shift right
>>
>>>
srl
Bit-by-bit
AND
&
&
and,andi
Bit-by-bit OR
|
|
or,ori
Bit-by-bit
NOT
~
~
nor
shamt



sll $t2,$s0,4#reg $t2 = reg $s0
op
rs
rt
rd
shamt funct
0
0
16
10
4
<< 4 bits
0
Shift amount = 4 (What is the max shift
amount?)
Shifting left by i bits gives the same result as
multiplying by 2i
Instructions for Making
Decisions

Decision making instructions



alter the control flow,
i.e., change the "next" instruction to be executed
MIPS conditional branch instructions:
bne $t0, $t1, Label
beq $t0, $t1, Label

Example:
if (i==j) h = i + j;
bne $s0, $s1, Label
add $s3, $s0, $s1
Label:
....
If-then-else conditional
branches

MIPS unconditional branch instructions:
j

label
Example:
if (i==j)
h=g+h;
else
f=g-h;
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else:sub $s0, $s1, $s2
Exit:
Loops

while loop in C:
while (save[i]==k)
i+=1;

i  $s3, k$s5, base of the array save is in $s6.
Loop: sll
Exit:
$t1,$s3,2
# reg $t1=4*i
add
$t1,$t1,$s6 # $t1= address of save[i]
lw
$t0,0($t1)
bne
$t0, $s5, Exit # go to Exit if save[i]!=k
addi
$s3,$s3,1
# i=i+1
j
Loop
# go to Loop
# reg t0=save[i]
Control Flow


We have: beq, bne, what about Branch-if-less-than?
New instruction:
if



$s3 < $s4 then
$t0 = 1
slt $t0, $s3, $s4
else
$t0 = 0
slti $t0,$s2,10 # $t0=1 if $s2 < 10
Can use the above instructions to build "blt $s1,
$s2, Label"
— can now build general control structures
Note that the assembler needs a register to do this, there
are policy of use conventions for registers ($zero)
Case/Switch Statement

Two possible approaches


Convert the switch statement into a chain of ifthen-else statements
Build a jump address table

MIPS instruction: jr (jump register)

Unconditional jump to the address specified
in the register.
So far (p.77):

Instruction
Meaning
add $s1,$s2,$s3
sub $s1,$s2,$s3
lw $s1,100($s2)
sw $s1,100($s2)
and $s1,$s2,$s3
or $s1,$s2,$s3
nor $s1,$s2,$s3
andi $s1,$s2,100
ori $s1,$s2,100
sll $s1,$s2,10
srl $s1,$s2,10
bne $s4,$s5,L
beq $s4,$s5,L
slt $s1,$s2,$s3
slti $s1,$s2,100
j Label
$s1 = $s2 + $s3
$s1 = $s2 – $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
$s1 = $s2 & $s3
$s1 = $s2 | $s3
$s1 = ~($s2 | $s3)
$s1 = $s2 & 100
$s1 = $s2 ! $100
$s1=s2<<10
$s1=s2>>10
Next instr. is at Label if $s4!= $s5
Next instr. is at Label if $s4 = $s5
if ($s2<$s3) $s1=1, else $s1=0
if ($s2<100) $s1=1, else $s1=0
Next instr. is at Label
Formats
R
op
rs
rt
I
op
rs
rt
J
op
rd
shamt
funct
16 bit address/constant
26 bit address
Supporting Procedures in Computer
Hardware

Six steps the program must follow in an
execution of a procedure
1.
2.
3.
4.
5.
6.
Place parameters in a place where the procedure can
access them
Transfer control to the procedure
Acquire the storage resources needed for the
procedure
Perform the desired task
Place the result value in a place where the calling
program can access it
Return control to the point of origin.
MIPS Registers

MIPS registers:




$a0-a3: four argument registers in which to pass
parameters
$ v0-$v1: two value registers in which to return
values
$ra: one return address register to return to the
point of origin
MIPS instruction: jal ProcedureAddress
(jump and link)
Using More Registers



Use stack
MIPS allocates a register for the stack: the
stack pointer ($sp)
Example: p81-82.
Policy of Use
Conventions
Name Register number
$zero
0
$v0-$v1
2-3
$a0-$a3
4-7
$t0-$t7
8-15
$s0-$s7
16-23
$t8-$t9
24-25
$gp
28
$sp
29
$fp
30
$ra
31
Usage
the constant value 0
values for results and expression evaluation
arguments
temporaries
saved
more temporaries
global pointer
stack pointer
frame pointer
return address
Communicating with People

Load and store bytes




lb $t0,0($sp)
sb $t0,0($gp)
Example: String Copy Procedure
Unicode: 16 bits to represent a character
load halfwords


lh $t0,0($sp)
sh $t0,0($gp)
String Copy Procedure

C version
void strcpy char x[], char y[]
{
int i;
i=0;
while ((x[i]=y[i])!=‘\0’
i+=1;
}
String Copy Procedure (MIPS)
strcpy:
addi
sw
add
L1: add
lb
add
sb
beq
addi
j
L2:lw
addi
jr
$sp,$sp,-4
#adjust stack for 1 more item
$s0,0($sp)
#save $s0
$s0,$zero,$zero #i=0+0
$t1,$s0,$a1 # address of y[i] in $t1
$t2,0($t1)
#$t2=y[i]
$t3,$s0,$a0 #address of x[i] in $t3
$t2,0($t3)
#x[i]=y[i]
$t2,$zero,L2 # if y[i]==0 goto L2
$s0,$s0,1
#i=i+1
L1
# goto L1
$s0,0($sp)
#y[i]==0; end of string, restore
#old $s0
$sp,$sp,4
#pop 1 word off stack
$ra
#return
MIPS Addressing for 32-bit
Immediates and Addresses


We'd like to be able to load a 32 bit constant into a
register
Must use two instructions, new "load upper immediate"
instruction
lui $t0, 1010101010101010
filled with zeros
1010101010101010

0000000000000000
Then must get the lower order bits right, i.e.,
ori $t0, $t0, 1010101010101010
1010101010101010
0000000000000000
0000000000000000
1010101010101010
1010101010101010
1010101010101010
ori
Assembly Language vs.
Machine Language

Assembly provides convenient symbolic
representation



Machine language is the underlying reality



much easier than writing down numbers
e.g., destination first
e.g., destination is no longer first
Assembly can provide 'pseudoinstructions'

e.g., “move $t0, $t1” exists only in Assembly

would be implemented using “add $t0,$t1,$zero”
When considering performance you should
count real instructions
Overview of MIPS





Simple instructions, all 32 bits wide
Very structured, no unnecessary baggage
Only three instruction formats
R
op
rs
rt
rd
I
op
rs
rt
16 bit address
J
op
shamt
26 bit address
Rely on compiler to achieve performance
— what are the compiler's goals?
Help compiler where we can
funct
Addressing in Branches and
Jumps

Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label
j Label


Next instruction is at Label if $t4!= $t5
Next instruction is at Label if $t4 = $t5
Next instruction is at Label
Formats:
I
op
J
op
rs
rt
16 bit address
26 bit address
Addresses are not 32 bits
— How do we handle this with load and store instructions?
Addresses in Branches

Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label

Formats:
I

op
rs
rt
16 bit address
Could specify a register (like lw and sw) and add it to
address



Next instruction is at Label if $t4!=$t5
Next instruction is at Label if $t4=$t5
use Instruction Address Register (PC = program counter)
most branches are local (principle of locality)
Jump instructions just use high order bits of PC

address boundaries of 256 MB
MIPS Addressing Modes
1. Immediate addressing
op
rs
rt
Immediate
2. Register addressing
op
rs
rt
rd
...
funct
Registers
Register
3. Base addressing
op
rs
rt
Memory
Address
+
Register
Byte
Halfword
4. PC-relative addressing
op
rs
rt
Memory
Address
PC
+
Word
5. Pseudodirect addressing
op
Address
PC
Memory
Word
Word
Decoding Machine Code




P102 Example: 00af8020hex
0000 0000 1010 1111 1000 0000
0010 0000
000000 00101 01111 10000 00000
100000
add $s0,$a1,$t7
To summarize:
MIPS operands
Name
32 registers
Example
Comments
$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
$a0-$a3, $v0-$v1, $gp,
arithmetic. MIPS register $zero always equals 0. Register $at is
$fp, $sp, $ra, $at
reserved for the assembler to handle large constants.
Memory[0],
2
30
Accessed only by data transfer instructions. MIPS uses byte addresses, so
memory Memory[4], ...,
words
and spilled registers, such as those saved on procedure calls.
add
MIPS assembly language
Example
Meaning
add $s1, $s2, $s3
$s1 = $s2 + $s3
Three operands; data in registers
subtract
sub $s1, $s2, $s3
$s1 = $s2 - $s3
Three operands; data in registers
$s1 = $s2 + 100
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
Used to add constants
Category
Arithmetic
sequential words differ by 4. Memory holds data structures, such as arrays,
Memory[4294967292]
Instruction
addi $s1, $s2, 100
lw $s1, 100($s2)
load word
sw $s1, 100($s2)
store word
lb $s1, 100($s2)
load byte
sb $s1, 100($s2)
store byte
load upper immediate lui $s1, 100
add immediate
Data transfer
Conditional
branch
Unconditional jump
$s1 = 100 * 2
16
Comments
Word from memory to register
Word from register to memory
Byte from memory to register
Byte from register to memory
Loads constant in upper 16 bits
branch on equal
beq
$s1, $s2, 25
if ($s1 == $s2) go to
PC + 4 + 100
Equal test; PC-relative branch
branch on not equal
bne
$s1, $s2, 25
if ($s1 != $s2) go to
PC + 4 + 100
Not equal test; PC-relative
set on less than
slt
$s1, $s2, $s3
if ($s2 < $s3) $s1 = 1;
else $s1 = 0
Compare less than; for beq, bne
set less than
immediate
slti
jump
j
jr
jal
jump register
jump and link
$s1, $s2, 100 if ($s2 < 100) $s1 = 1;
Compare less than constant
else $s1 = 0
2500
$ra
2500
Jump to target address
go to 10000
For switch, procedure return
go to $ra
$ra = PC + 4; go to 10000 For procedure call
Alternative Architectures



Design alternative:

provide more powerful operations

goal is to reduce number of instructions executed

danger is a slower cycle time and/or a higher CPI
Sometimes referred to as “RISC vs. CISC”

virtually all new instruction sets since 1982 have been RISC

VAX: minimize code size, make assembly language easy
instructions from 1 to 54 bytes long!
We’ll look at PowerPC and 80x86
PowerPC


Indexed addressing
example:

What do we have to do in MIPS?
#$t1=Memory[$a0+$s3]
Update addressing

update a register as part of load (for marching through arrays)
example: lwu $t0,4($s3)
#$t0=Memory[$s3+4];$s3=$s3+4

What do we have to do in MIPS?


lw $t1,$a0+$s3

Others:


load multiple/store multiple
a special counter register “bc Loop” decrement counter, if not 0
goto loop
The Intel IA-32













1978: The Intel 8086 is announced (16 bit architecture)
1980: The 8087 floating point coprocessor is added
1982: The 80286 increases address space to 24 bits, +instructions
1985: The 80386 extends to 32 bits, new addressing modes
1989-1995: The 80486, Pentium, Pentium Pro add a few instructions
(mostly designed for higher performance)
1997: MMX is added
1999: Add 70 instructions labeled SSE (Streaming SIMD Extensions)
2001:Add 144 instructions labeled SSE2
2003: AMD 64
2004: EM64T
“This history illustrates the impact of the “golden handcuffs” of compatibility
“adding new features as someone might add clothing to a packed bag”
“an architecture that is difficult to explain and impossible to love”
A dominant architecture:
80x86


See your textbook for a more detailed description
Complexity:





Instructions from 1 to 17 bytes long
one operand must act as both a source and destination
one operand can come from memory
complex addressing modes
e.g., “base or scaled index with 8 or 32 bit displacement”
Saving grace:


the most frequently used instructions are not too difficult to build
compilers avoid the portions of the architecture that are slow
“what the 80x86 lacks in style is made up in quantity,
making it beautiful from the right perspective”
Summary

Instruction complexity is only one variable


Design Principles:





lower instruction count vs. higher CPI / lower
clock rate
simplicity favors regularity
smaller is faster
good design demands compromise
make the common case fast
Instruction set architecture

a very important abstraction indeed!