FRC FPGA Architecture
Kickoff 2009
Agenda
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FRC Robot Controller Architecture
FPGA Features and Use Cases
Break
WPILib for LabVIEW
Break
WPILib for C / C++
cRIO Architecture
Ethernet
Freescale
PowerPC
Ethernet
Slot 1
RS232
Slot2
PCI
Xilinx FPGA
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Slot 8
NI 9201 Architecture
8 Channel Analog Input Module
Channel 1
Channel 2
FPGA
ADC
MUX
NI 9201
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Channel 8
/ Battery
NI 9403 Architecture
32-Channel Bidirectional Digital I/O Module
Pull-up
Resistors
Digital I/O (14)
Tristate
Buffer
Hobby PWM
Output (10)
Relay (8 x 2)
FPGA
NI Lightning Bug
Shift Register
Robot Signal
Light
NI 9403
I2C Header
Outputs (4)
Grounding
FETs
I2C Bus
Digital Breakout
NI 9472 Architecture
Solenoid
Channel 1
FPGA
Buffer
Solenoid
Channel 2
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NI 9472
Solenoid
Channel 8
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Analog Input
Use Case
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Angle of a Potentiometer
Distance of a Maxbotics Ultrasonic Sensor
Acceleration of an Accelerometer Axis
Any other Very Low Frequency Analog Signal
Analog Input
• 12-bit ADC with +/-10V Range
• Access Factory Calibration
• Variable-Length Scan List
– 8 maximum
– Repeat entries allowed
• Scan Rate
– Per module basis (one ADC)
– 2us per Conversion Minimum
i.e. 500kS/s with single entry scan list
Analog Input Sources
• Raw Samples
– 16-bit
– Updated After Each Conversion
• Oversample / Average Engine Output
– 32-bit
• Windowed Register Access
– Most recent sample
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Oversample / Average Engine (OAE)
Use Case
• Oversample
– Higher Resolution Samples
– Lower Sample Rate
• Average
– Same Resolution Samples
– Lower Sample Rate
– More Stable Sample Values
Oversample / Average Engine (OAE)
• Specified in bits
– B bits: 2B == N Samples
– 15 bits Each Maximum
• Oversample
– Sums NO samples
• Average
– Sums NA samples
– Divide by NA
• Output changes after NO x NA Samples
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Accumulator
Use case
• Hardware Numerical Integration
• Gyro
– Integrate: Angular Rate  Angle
Accumulator
• 64-bit Value / 32-bit Count
• 2 available
– Hardwired to Slot 1, AI 1 and AI 2 OAE Output
• Center Value
• Deadband
• Value Reset to Zero
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Analog Trigger
Use case
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Reflective Sensor Encoder
Interrupt at Pot Value
Sin-Cos Signal to Quadrature
Variable Reluctance Sensor
Any Analog Signal to Digital
Analog Trigger
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Trigger Events From Analog Signal
Specify Upper and Lower Limit
Source Raw or OAE
Trigger State
– High when Above Upper Limit
– Low when Below Lower Limit
– Unchanged when Between Limits (Hysteresis)
• In Window
– Voltage between Upper and Lower Limit
Analog Trigger
Analog Trigger – Hysteresis
Analog Trigger – Hysteresis (Too Noisy)
Analog Trigger - Rollover Detection
Use case
• Count Rollovers (Rotations)
– Continuous-Turn Potentiometers
– Magnetic Absolute Encoder
– Any Signal that Rolls Over
Analog Trigger - Rollover Detection
• Jump Over Window
• Floating
– Large Change in Value
• Average-Rejection Filter
– 3 Point Filter
• Pulse Output
– Rising and Falling Pulses
– Cannot Read via Register; Routable Only
Analog Trigger – Rollover Detection
Rising Trigger
Analog Trigger – Rollover Detection
Rising Trigger, Low-Pass Filtered
Average Rejection Filter
Use case
• Averaging Inherent in Sampling Process
• Perform More Averaging After Sampling
– Changes the Effective Sample Rate
– Increases the Effect of the Filter
• Balance Effective Sample Rate
– Too Fast, the Filter Has Too Little Effect
– Too Slow, Trigger False Positives
• True Slope Needs at least One Sample In Window
Average Rejection Filter
Analog Trigger – Rollover Detection
Rising Trigger, Average Rejection
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Digital Input / Output
Use case
• Digital Input
– Limit Switches
• Digital Output
– Jaguar Coast / Brake Control
• Pulse Generator
– Ping Signal for Ultrasonic Sensors
Digital Input / Output
• 6.525us Per Sample
• Output Enable (Change)
– 17us Delay for I/O on Both NI 9403 Modules
• Output Latch Configurable Before OE
• Output Pulse Generator
– Invert Bits For Some Time Then Reset
– 1.6ms Maximum
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Slow Digital Output
Use case
• Spike Relay Control
• Robot Signal Light
– Controlled by Network Status Code
– Not Available
• 4 Outputs on I2C Header
– Any Custom Circuits that need More Outputs
Slow Digital Output
• SPI Output to Sidecar Shift Registers
• 320us Per Update
• Spike Relay Control
– Gated by Watchdog
• Robot Signal Light
• 4 Outputs on I2C Header
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Hobby PWM Output
Use case
• Jaguar Motor Controller
– 1x Period Multiplier
– 5ms Update
• Victor Motor Controller
– 2x Period Multiplier
– 10ms Update
• Hobby Servo
– 4x Period Multiplier
– 20ms Update
Hobby PWM Output
• 8-bit Generator
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0 == Disable Output
1 == 0.65ms High
128 == 1.5ms High
255 == 2.35ms High
• Period Multiplier
– 1x, 2x, or 4x
• Gated by Watchdog
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
I2C Bus
Use case
• Hitechnic NXT Compatible Sensors
– Compass
– 3 Axis Accelerometer
– Gyro (No Hardware Integration)
• Devantech Sensors
– SRF08 Ultrasonic Range Finder
– Compass
• Any Other I2C Compliant Sensors
I2C Bus
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Address / Register / Data Transaction Format
Independent Bus Per Module
7-Bit Addresses Only
Write 1 Byte Per Transaction
Read 1, 2, 3, or 4 Bytes Per Transaction
Clock Skewing Only On Read Between Data Bytes
Slave Acknowledge Ignored
Interrupt on Done
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Digital Input Filtering
Use case
• Debounce Buttons
• Synchronize Digital Input Signals
• Filter Out High Frequency Noise
Digital Input Filtering
• 3 Filters Per Module
• Filter Assigned Per Channel
• Correlation Between Channels
– Updates at End of Correlation Period
– Unchanged if Input Changed During Period
• All Routed Digital Inputs Can Be Filtered
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Solenoid Output
Use case
• Control Pneumatic Solenoids
• Less Space Than 4 Spikes
Solenoid Output
• Pass-through
• Gated by Watchdog
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Watchdog
Use case
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Ensure That Critical Code Keeps Running
Added Safety if Used Correctly
Not Mandatory; Strongly Recommended
Disable to Keep Motors Running At Breakpoint
Watchdog
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Disables Actuator Outputs
Configurable Timeout
Feed To Keep Alive
Manual Kill
– Disable Outputs Now
• Immortal Mode
– Timeout and Manual Kill Ignored
– Outputs Enabled
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Counter / Timer
• 2 Types of Counters
– Dedicated 4x Quadrature Decoders
• 4 Available
– General Purpose Counters
• 8 Available
• Signed 31-bit Value
• Most Recent Direction
• Timer On Each Counter Output
Counter / Timer (cont)
• Routable Input Sources
– Digital Input Filter
– Analog Trigger
• Disable (Ignore Inputs)
• Software Reset Value to Zero
• External Reset Value to Zero
Routable Input
Dedicated 4x Quadrature Decoder
Use case
• Highest Resolution
• Dedicated Hardware
• Absolute Angle
– External Reset as Index Input
Dedicated 4x Quadrature Decoder
• A and B Channel
Routable Inputs
• Count for Each Transition of A or B Signal
4x More Precise
1x, 2x Quadrature Decoding Counter
Use case
• Used Up All 4x Decoding Counters
• Less Resolution Needed
• More Averaging of Encoder Speed
– Fewer Timer Events Per Rotation
Up / Down Counter
Use case
• Count Full Rotations of Rollover Sensors
– Route Analog Trigger Rising and Falling Pulses
• Simple Counter
– Disable the “Count Down” Channel
External Direction Counter
Use case
• BaneBots Encoder Divider Kit
• Other Encoder Types
General Purpose Counter
• Counting Modes
– 1x or 2x Quadrature Decoding
• “A” and “B” Inputs
– Up / Down Counter
• “Count Up” and “Count Down” Inputs
– External Direction
• “Count” and “Direction” Inputs
• Rising, Falling, or Both Edge Sensitivity
Semi-Period Timer
Use case
• Echo Signal from Ultrasonic Range Sensor
• Duty-Cycle Measurement
– If Period is Fixed, Measure High or Low Pulse
– If Not, Hard to Get Consistent Sample
Pulse-Length Direction Counter
Use case
• Allegro ATS651 Gear Tooth Sensor
– Direction Information Encoded in Pulse Length
– Provided in Kit in 2005
• Black PCB
• RevNC
General Purpose Counter (cont)
• Special Modes
– Semi-Period
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Primary Output is Timer
Odd Counter Value Means Measurement In Progress
Select High or Low Semi-Period
Single Input Channel
– Pulse-Length Direction
• Direction to Count Determined From Pulse-Length
• Select Pulse-Length Threshold
• Single Input Channel
Timer
Use case
• Measure Speed
• Detect Motor Stall
• Time Events
Timer
• Time Between Counter Events
– Event == Value Change
• Stall Detection
• Sample Averaging
– Sliding Window
– Up to 128 Samples
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
SPI Engine
Use case
• Interface Custom Circuits
• Some Sensors
SPI Engine
• Serial Peripheral Interface / Synchronous Serial
• Input and Output FIFOs
– 512 Words Each
• Highly Configurable
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Chip Select / Pre- or Post-Latch
Clock Polarity
Word Size (1-bit to 32-bit)
MSb or LSb First
• Streaming Interrupts
– Receive Buffer
• Not Empty; Half Full
– Transmit Buffer
• Half Empty; Empty and Idle
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Time / Alarm
Use case
• Time
– Consistent us Value Across Subsystems
– Fast, Precise Benchmark Source
• Alarm
– Interrupt Based Task Scheduling (for C++)
Time / Alarm
• Time
– 1us Resolution
– 32-bit range (71.5 Minutes)
• Alarm
– Schedule for a Specific Time
– Generate an Interrupt
– Interrupt Immediately if Scheduled Time In Past
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Routable Interrupt
Use case
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Interrupt on Button
Timestamp An Event
Some Crazy Interface We Didn’t Foresee
If All Else Fails
Routable Interrupt
• Input Sources Routable
– Digital Input Filter
– Analog Trigger
• Latch Timestamp
• Wait for Acknowledge
– Timestamp Will Not Change Until Acknowledge
– Can be Disabled
FRC FPGA Subsystems
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Analog Input
Oversample / Average
Accumulator
Analog Trigger
Digital Input / Output
Slow Digital Output
Hobby PWM Output
I2C Bus
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Digital Input Filtering
Solenoid Output
Watchdog
Counter / Timer
SPI Engine
Time / Alarm
Routable Interrupt
Direct Memory Access
Direct Memory Access (DMA)
Use case
• Data Streaming
– FIR Filtering
– Fourier Transform (Frequency Content)
• Snapshot of Sensor On Event
– Position Observer
Direct Memory Access (DMA)
• Stream Data Directly to PPC Memory
• Sample Clock
– Correlated Samples of Unrelated Data
– Internally timed
• FPGA Clock Domain
– Externally timed
• Routable Input
• Configurable Data Sources
• Sample Includes Timestamp
• Overrun Indication
Questions?