ST7 MICROCONTROLLER TRAINING
1 - INTRODUCTION
2 - CORE
3 - ADRESSING MODES
4 - PERIPHERALS
5 - ST7 SOFTWARE TOOLS
6 - ST7 HARDWARE TOOLS
7 - STVD7
ST7 PERIPHERALS
1
ST7 I/O PORTS
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT










16-bit timer
Peripheral
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom
Peripheral
Data Ram
256 bytes
Peripheral
Peripheral
Test/Vpp
Peripheral
Reset
Data
EEprom
Optional features :
Peripheral
AD converter
16-bit Timer
8-bit Auto Reload Timer
SPI
SCI
I2C
EEPROM
Programmable OpAmp
CAN
Oscillator
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
2
ST7 I/O PORTS
Overview

ALL THE I/Os ARE INDIVIDUALLY SOFTWARE
CONFIGURABLE USING 3 DIFFERENT REGISTERS :
 DDR:
 DR:
 OR:

Data Direction Register
Data Register
Option Register
ST72254 : 22 MULTIFUNCTION BIDIRECTIONAL I/O LINES





18 Standard I/Os (sink up to 5mA)
8 High Current I/Os (PA0-PA7 can sink up to 20mA)
6 Analog Inputs (PC0-PC5)
16 alternate Functions on 16 pins (for Timers, SPI and I2C)
All the I/Os can be set-up as Interrupt inputs
ST7 PERIPHERALS
3
ST7 I/O PORT
Safe I/O pin transition
01
DDR
OR
Mode
0
0
Floating input
0
1
Input pull- up with/without interrupt
1
0
Output Open-Drain
1
1
Output Push-Pull
00
10
11
Reset State
ST7 PERIPHERALS
4
ST7 I/O PORT Basic structure
Read / Write
DDRi
Data Direction
Register Bit
Write DRi
Latch Data
Output bit
Read
DRi
Ouput
I/O
Pin
Input
Reg bit
Input
I/O
 SOFTWARE SELECTABLE CONFIGURATION
 HIGH FLEXIBILITY for software and PC board layout
ST7 PERIPHERALS
5
ST7 I/O PORT
Settings & electrical behaviour

Configuration given when no external Hardware is connected
the pins
Input
Floating
Input Pull_up
Ouput
Open Drain
Ouput
Push-Pull
DDR
0
0
0
0
1
1
1
1
OR
0
0
1
1
0
0
1
1
Written DR
0
1
0
1
0
1
0
1
Floating
Floating
Vdd
Vdd
Vss
Floating
Vss
Vdd
X
X
1
1
0
1
0
1
I/O Pin
Read DR
ST7 PERIPHERALS
6
ST7 EXTERNAL INTERRUPTS
Pin 1
Pin 2
Interrupt Source 1
Edge/level selection
Pin M
ST7 Interrupt Controller
Pin 1
Pin 2
Interrupt Source 2
Edge/level selection
Pin N
Pin 1
Miscellaneous Register
Pin 2
Interrupt generation
Interrupt source
Negative edge only
Latched
Positive edge only
Latched
Negative edge and low level
Not Latched
Positive and Negative edge
Latched
ST7 PERIPHERALS
7
ST7 I/O PORT Block Diagram
REGISTER
ACCESS
ALTERNATE
OUTPUT
V DD
1
0
ALTERNATE
ENABLE
DR
DDR
DATA BUS
PULL-UP
Condition
OR
PAD
OR SEL
DDR SEL
DR SEL
CMOS
SCHMITT
TRIGGER
1
0
EXTERNAL
INTERRUPT
POLARITY
SOURCE
SELECTION
FROM
OTHER
BITS
ALTERNATE
INPUT
ST7 PERIPHERALS
ANALOG
INPUT
8
PROGRAMMING TIPS
I/O Port (1)

AD CONVERTION
 Each pin used by the ADC cell must be configured as floating input
(i.e. without pull-up resistors) before activating the analog input mode

ALTERNATE FUNCTION
 A signal coming from an on-chip peripheral can be output on a port.
In this case, the I/O is automatically configured in output mode.
 A signal coming from an I/O can be an input to an on-chip peripheral.
In this case, it must be configured as Input without interrupt (Floating
Input).
ST7 PERIPHERALS
9
PROGRAMMING TIPS
I/O Port (2)

Open Drain Outputs can be used for bus driving where several
devices are connected on the same line. They can be wired
together to increase current drive capability

Voltages driving an Analog Input should always stay within the
absolute maximum ratings (Vss-0.3V to Vdd+0.3V)

Pull-up resistors typically deliver 50µA under 5V

The toggling time on any output pin will be approximately 30ns for
a 50pF load
ST7 PERIPHERALS
10
I/O Ports Configuration Example
PBDR7
PBDR0

Fill the dedicated I/O port
registers in order to have
the following configuration:

PB0:PB2
 Push-Pull Output (high level)
PBDR
PBDDR7

 Floating Input
PBDDR0

PB5
 Input with Interrupt
PBDDR
PBOR7
PB3,PB4

PB6
 Push-Pull Output (low level)
PBOR0

PB7
 Ouput (High Impedance)
PBOR
ST7 PERIPHERALS
11
A/D CONVERTER
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT

 AD converter
16-bit timer








Peripheral
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom
Peripheral
Data Ram
256 bytes
Peripheral
Peripheral
Test/Vpp
Peripheral
Reset
Data
EEprom
Optional features :
Peripheral
Oscillator
16-bit Timer
8-bit Auto Reload Timer
SPI
SCI
I2C
EEPROM
Programmable OpAmp
CAN
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
12
ST7 AD CONVERTER
Overview (1)

8-BIT SUCCESSIVE APPROXIMATIONS CONVERTER WITH UP
TO 8 ANALOG CHANNELS:
 ST72254 : 6 inputs
 ST72334 and ST725xx : 8 inputs
 ST72171 : 6 external inputs + 2 internal inputs

FEATURE :
 Accuracy : 1 LSB
 Total Unajusted Error MAX : 1 LSB
 Conversion time : 24 CPU cycle ie 3µs at full speed (8MHz)

FLAGS
 COCO : end of conversion (Status flag)
 ADON : ADC on/off bit (to reduce power consumption)
ST7 PERIPHERALS
13
ST7 AD CONVERTER
Overview (2)

LOW CONSUMPTION MODES
 Wait mode doesn't affect the ADC
 Halt mode stops the ADC.

HARDWARE
 ST72334 and ST725xx : Vdda and Vssa must be connected
externally respectivelly to Vdd and Vss through decoupling capacitors.
 ST72254 : connection done internally

RATIONETRIC In the Functionnal Range
 If analog voltage input > Vdd :
converted result = FFh (no overflow indication)
 If analog voltage input < Vss :
converted result = 00h (no underflow indication)
ST7 PERIPHERALS
14
ST7 AD CONVERTER
Block diagram
COCO
-
ADON
0
-
CH2
CH1
CH0
(Control Status Register) CSR
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
ANALOG
MUX
Fcpu
SAMPLE
&
HOLD
ANALOG TO
DIGITAL
CONVERTER
AD7
AD6
AD5
AD4 AD3
AD2
AD1
AD0
(Data Register) DR
ST7 PERIPHERALS
15
PROGRAMMING TIPS
AD Converter

PROCEDURE
 Step 1 : The analog input pins must be set-up as Input no pull-up no
interrupt
 Step 3 : assign a channel for the conversion (bit CH0, CH1 and CH2
in CSR register) and set the ADON bit
 Step 4 : Wait until COCO bit set. A continuous conversion is
performed.
 To reach the best accuracy, the impedance seen by the analog input pin must be
lower than 10Kohm.
ADON bit
set
Continuous ADC
ADC init :
–IO config
t = 3µs
–Channel selected
t = 3µs
Write in CSR :
Stop conversion
If ADON still set : new
conversion
Else stop ADC
t = 3µs
Beginning of a new conversion
by writing in the CSR (select the analog channel)
ST7 PERIPHERALS
16
ADC Configuration Example
COCO
ADON
CH3
CH2
CH1
CH0
ADCDR

Fill ADCCSR register in order to have an analog conversion
on AIN4.

What bit has to be tested to know the end of the conversion ?
ST7 PERIPHERALS
17
ST7 16-bit TIMER
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT

16-bit timer
 AD converter
Peripheral
 16-bit Timer
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom







Peripheral
Data Ram
256 bytes
Peripheral
Peripheral
Test/Vpp
Peripheral
Reset
Data
EEprom
Optional features :
Peripheral
Oscillator
8-bit Auto Reload Timer
SPI
SCI
I2C
EEPROM
Programmable OpAmp
CAN
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
18
16-bit TIMER
Overview (1)

16-bit free running counter driven by a software configurable
prescaler

4 different modes :
 Input capture (2 pins) : to latch the value of the counter after a
transition on the ICAPi pin
 Output compares (2 pins) : to control an output waveform or to
indicate when a period of time is over
 One pulse : generation of a pulse when an external event occurs
 PWM : generation of a signal with frequency and pulse length set by
software (OCR1 and OCR2)
ST7 PERIPHERALS
19
16-bit TIMER
Overview (2)

The timer clock can be provided by :
 The internal clock with a configurable ratio
 An external source : Fext must 4 times slower than the internal clock
(ie Fmax=2Mhz)
CC1
CC0
Timer clock
0
0
Fcpu/4
0
1
Fcpu/2
1
0
Fcpu/8
1
1
External
ST7 PERIPHERALS
20
16-bit TIMER
Block diagram
ST7 INTERNAL BUS
OUTPUT
COMPARE
REGISTER 1
16-BIT FREE
RUNNING
COUNTER
COUNTER
ALTERNATE
REGISTER
1/2
1/4
1/8
EXCLK
INPUT
CAPTURE
REGISTER 1
16
LOW BYTE
INPUT
CAPTURE
REGISTER 2
16
16-Bit INTERNAL TIMER BUS
OUTPUT
COMPARE
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
0
OCF1
TOF
ICIE
OCIE
TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL2
OCF2
0
OC1E OC2E OPM
CONTROL REGISTER 1
TIMER INTERNAL INTERRUPT
EDGE
DETECT
CIRCUIT 2
ICAP1
EDGE
DETECT
CIRCUIT 1
ICAP2
0
ICF1
ICF2
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
OUTPUT
COMPARE
REGISTER 2
16
CC1 CC0
STATUS REGISTER
HIGH BYTE
8
8-BIT
BUFFER
LOW BYTE
EXEDG
HIGH BYTE
CPU
CLOCK
LOW BYTE
MCU-PERIPHERAL INTERFACE
ST7 PERIPHERALS
PWM
CC1
LATCH 1
OCMP1
LATCH 2
OCMP2
CC0 IEDG2 EXEDG
CONTROL REGISTER 2
21
16-bit TIMER
Input capture (1)

Captures the counter value upon input signal edge detection

Allows an external pulse length measurement

Internal safety process in case of critical interrupts timing
Timer Counter Register
ICAP1A
Edge Detector
Input Capture Register
Software Maskable Interrupt Request
ST7 PERIPHERALS
22
16-bit TIMER
Input capture (1)
ICAP1
(Control Register 1) CR1
ICAP2
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC2R
IC1R
ICF1
ICF2
0
0
0
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
CC1
ST7 PERIPHERALS
CC0 IEDG2
23
16-bit TIMER
Ouput compare (1)

Event generation (Interrupt request/bit toggling) whenever the
compare register matches the counter

Indicates a period of time has elapsed and controls an output
waveform

Internal safety process in case of critical interrupts timing
Timer Counter Register
Match?
Software Maskable Interrupt Request
Pulse generation
Output Compare Register
ST7 PERIPHERALS
24
16-bit TIMER
Output compare (2)
16-BIT
FREE RUNNING
COUNTER
OC1E
OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OC1R
OCIE
OLVL2
OLVL1
Latch
1
OCMP1
Latch
2
OCMP2
16-bit
OC2R
OCF1
OCF2
0
0
0
(Status Register) SR
ST7 PERIPHERALS
25
16-bit TIMER
Real Time Clock


In each Interrupt Routine the OCR Register content is
updated.
There is no shift time (the counter is never reset externally).
FREE RUNNING
COUNTER VALUE
FFFFh
OCR+DT
OCR
0000h
Timer IT
ST7 PERIPHERALS
Timer IT
time
26
16-bit TIMER
One pulse mode (1)

Generation of a pulse synchronized with an external event

Allows Phase Locked Loop Generation

On Input Capture event
 The counter is reset
 The timer output pin is toggled

On Output compare event
 The timer output pin is toggled
 The timer waits for the next Input Capture event
ST7 PERIPHERALS
27
16-bit TIMER
One pulse mode (2)
 Free running counter is
When a external event occurs
on ICAP1 pin
initialized to FFFCh
 OLVL2 bit level is applied
on the OCMP1 pin
I CF1 bit is set
When the free running counter
reaches
OC1R register value
 OLVL1 bit level is applied
on the OCMP1 pin
ST7 PERIPHERALS
28
16-bit TIMER
One pulse mode (3)
FREE RUNNING
COUNTER VALUE
FFFFh
FFFCh
Compare 1
0000h
time
ICAP1
Input Capture pin
Timer input
time
OCMP1
Ouput Compare pin
Timer output
time
ST7 PERIPHERALS
29
16-bit TIMER
PWM mode (1)

Automatic generation of a Pulse Width Modulated signal

Period &pulse lenght set by software:
 The first Output Compare Register OC1R contains the length of the
pulse
 The second Output Compare Register OCR2 contains the period of
the pulse

Resolution up to 100 steps at 20 KHz (fCPU =4 MHz): 1% of
accuracy on the duty cycle
ST7 PERIPHERALS
30
ST7 TIMER
PWM mode (2)
 Free running counter is
initialized to FFFCh
When the free running counter
reaches
OC2R register value
 OLVL2 bit level is applied
on the OCMP1 pin
 ICF1 bit is set
When the free running counter
reaches
OC1R register value
 OLVL1 bit level is applied
on the OCMP1 pin
ST7 PERIPHERALS
31
ST7 TIMER
PWM mode (3)
FREE RUNNING
COUNTER VALUE
Tmax = Ttimer × 65535
FFFFh
FFFCh
Compare 2
Compare 1
0000h
time
OLVL2= 1
OCMP1
Ouput Compare pin
Timer output
OLVL1=0
ST7 PERIPHERALS
time
32
PROGRAMMING TIPS
16-bit timer (1)

Define Input capture pins as inputs through the
corresponding Data Direction Register

Read MSB first and then the LSB
 The counter LSB is buffered during the MSB read
 The counter LSB read accesses the buffered value
 Any access to the high byte disables the corresponding timer function
until the low byte is accessed
 Disable the interrupts during any word access

Writing the counter LSB resets the timer at FFFCh
ST7 PERIPHERALS
33
PROGRAMMING TIPS
16-bit timer (2)

Clearing a status bit is performed by a read access to the status
register followed by an access (read or write) to the low byte of the
corresponding register

The alternate counter register is always matching the counter

Use the alternate counter register when you do not want to clear
the Timer Overflow Flag

No interrupt is generated on compare when the PWM is active, but
the ICF1 bit is set every period and can generates an interrupt

Be aware that the implicit reading performed by the emulator
might clear the status flags
ST7 PERIPHERALS
34
PROGRAMMING TIPS
16-bit timer (3)
CHR
CLR buffered
ACHR
ACLR buffered
Read
Any others Instructions
CLR
Read
ACLR
Returns the CLR buffered value
Clear TOF bit
Returns the ACLR buffered value
CLR
Reset counter to FFFCh
Clear TOF bit
ACLR
Reset counter to FFFCh
Write
ST7 PERIPHERALS
35
Timer Configuration Example
ICIE
OCIE
TOIE
FOLVL2
FOLVL1
OLVL2
IEDG1
OLVL1
OC1E
OC2E
OPM
PWM
CC1
CC0
IEDG2
EXED
TACR1
TACR2

Fill the Timer registers in order to generate a real time clock at 5ms
using an interrupt strategy & a timer clock at 1µs (fCPU = 8MHz).
 An interrupt is generated every 5ms using Output
compare1.
 OCMP1 pin has to be toggled every period

What is the value to add to the TAOC1HR & TAOC1LR every period?
ST7 PERIPHERALS
36
Serial Peripheral Interface
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT

Optional features :
 AD converter
 16-bit Timer
 8-bit Auto Reload Timer
16-bit timer
Peripheral
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom
 SPI
Peripheral
Data Ram
256 bytes





Peripheral
Peripheral
Test/Vpp
Peripheral
Reset
Data
EEprom
Peripheral
Oscillator
SCI
I2C
EEPROM
Programmable OpAmp
CAN
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
37
ST7 SPI
Overview

THE SPI CELL ALLOWS A FULL DUPLEX SYNCHRONOUS SERIAL
COMMUNICATION BETWEEN 2 DEVICES

MAIN FEATURE :
 Full duplex, 3 wire synchronous transfers
 Master : 6 frequency available. It rates up to 2 MHz
 Slave mode : it rates up 4 MHz

THE CLOCK IS PROGRAMMABLE : POLARITY AND PHASE

3 DIFFERENT STATUS FLAG :
 Data transfer : data transfer completed
 Write collision : access to SPIDR during a transmission
 Fault flag : fault in master mode detected
ST7 PERIPHERALS
38
ST7 SPI
Master-Slave communication
Master
Slave
MISO
MISO
8-bit Shift Register
8-bit Shift Register
SPI Clock
Generator
MOSI
MOSI
SCK
SCK
5V
SS
SS
ST7 PERIPHERALS
39
ST7 SPI
Block diagram
SPIDR
Read
Internal Bus
Read Buffer
IT
request
MISO
MOSI
SPISR
8-Bit Shift Register
SPIF WCOL -
MODF
-
-
-
-
Write
SPI
STATE
CONTROL
SCK
MISCR2
SPIOD
SSM
MASTER
CONTROL
SPICR
SPIE SPE SPR2-MSTR CPOL CPHA SPR1 SPR0
SSI
SERIAL CLOCK
GENERATOR
SS
ST7 PERIPHERALS
40
ST7 SPI
Single master configuration
SS
SCK
SS
SS
SCK
SCK
Slave
MCU
Slave
MCU
Slave
MCU
MOSI MISO
MOSI MISO
MOSI MISO
SS
SCK
Slave
MCU
MOSI MISO
MOSI MISO
5V
SS
P o r ts
SCK
Master
MCU
ST7 PERIPHERALS
41
SPI Configuration Example
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
SPICR

Fill the SPICR register in order to configure the SPI cell in





Master mode
Serial clock at 5OOKHz (fCPU=8MHz)
Sampling on 2nd edge
High level after clock signal
No interrupt generation
ST7 PERIPHERALS
42
ST7 I2C
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT

Optional features :





16-bit timer
Peripheral
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom
Peripheral
Data Ram
256 bytes
Peripheral
 I2C
Peripheral
Test/Vpp
 EEPROM
 Programmable OpAmp
 CAN
Peripheral
Reset
Data
EEprom
AD converter
16-bit Timer
8-bit Auto Reload Timer
SPI
SCI
Peripheral
Oscillator
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
43
ST7 I2C
Overview

The I2C cell provides all I2C bus specific sequencing,
protocol, arbitration and timing in order to reduce as much as
possible the software overhead

Polling Management or Interrupt Driven Cell

Main feature :




Multi Master capability
Interrupt generation
Standard I2C mode (up to 100kHz) and Fast I2C mode (up to 400kHz)
7-bit and 10-bit addressing
ST7 PERIPHERALS
44
ST7 SCI
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT

Optional features :
Peripheral




Peripheral
 SCI
16-bit timer
Peripheral
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom
Data Ram
256 bytes




Peripheral
Test/Vpp
Peripheral
Reset
Data
EEprom
Peripheral
Oscillator
AD converter
16-bit Timer
8-bit Auto Reload Timer
SPI
I2C
EEPROM
Programmable OpAmp
CAN
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
45
ST7 SCI
Overview (1)

FULL DUPLEX, ASYNCHRONOUS COMMUNICATION

DUAL BAUD RATE GENERATOR (MAXIMUM SPEED FOR SCI TX and
RX : 250kHz)
Ftx =

Fcpu
[16 × PR × 2] × TR
Frx =
Fcpu
[16 × PR × 2] × RR
PROGRAMMABLE WORD LENGTH
• 8 bits
• 9 bits (8 bits of data plus parity bit)

RECEIVER WAKE FUNCTION BY THE MOST SIGNIFICANT BIT OR
IDLE LINE
ST7 PERIPHERALS
46
ST7 SCI
Overview (2)

3 FLAGS
 Buffer full
 Transmit buffer empty
 End of transmission

MUTING FUNCTIONS FOR MULTIPROCESSOR
CONFIGURATIONS

NOISE, OVERRUN AND FRAME ERROR DETECTION

4 INTERRUPT SOURCES WITH FLAGS
ST7 PERIPHERALS
47
ST7 SCI
Serial data format
LSB
Previous frame
or idle line
Start bit
MSB
Following
frame or idle
line
8 bit data
Optionnal
parity bit
ST7 PERIPHERALS
Stop bit
48
SCI Sampling Data Format
Bit Time
Sampling Time

Each bit time is
Received
bit value
000
0
0
001
0
1
010
0
1
011
1
1
100
0
1
101
1
1
110
1
1
111
1
 Divided by 16 by the SCI clock
 Sampled 3 times on the 8th, 9th and 10th count of the SCI clock

NF
Flag
Data
Sampled
values
0
NF flag is set if the 3 sampling are not equal but the reception
is still available
ST7 PERIPHERALS
49
SCI Block Diagram
Data Register
RDI
pin
Transmit data register
Receive data register
Transmit shift register
Receive shift register
TDO
pin
Transmit rate Control
Transmit
Control
Control register 1
Control Register 2
Wake-Up
Unit
Receive
Control
Receive rate Control
Status Register
SCI Interrupt
Control
ST7 PERIPHERALS
fcpu
/2
/ 16
/ PR
50
ST7 SCI Clock selection
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
TRANSMITTER
CLOCK
f CPU
TRANSMITTER RATE
CONTROL
/16
/2
/PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER
CLOCK
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
ST7 PERIPHERALS
51
SCI Configurable Baud Rate
TR SCT2:SCT0
RR SCR2:SCR0





PR SCP1,SCP0
ETPR
/ERPR
Baud Rate
64 - 110
13 - 11
0
300
16 - 100
13 - 11
0
1200
8 - 011
13 - 11
0
2400
4 - 010
13 - 11
0
4800
2 - 001
13 - 11
0
9600
8 - 011
3 - 01
0
10400
1 - 000
13 - 11
0
19000
X
X
13
38000
Values given for fCPU =8MHz
PR selected by SCP1& SCP0 bits of SCIBRR Register
TR selected by SCT2,SCT1 & SCT0 bits of SCIBRR Register
RR selected by SCR2,SCR1 & SCR0 bits of SCIBRR Register
Reach the industry standard requirement
ST7 PERIPHERALS
52
SCI Configuration Example
R8
T8
TIE
TCIE
M
WAKE
ILIE
TE
SCICR1
RIE
RE
RWU
SBK
SCICR2
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
SCIBRR

Fill the SCI registers in order to configure the Sci cell in
 8 Bit word reception at 9600 Bauds
 8 bit word transmission at 1200 Bauds
 Interrupt generation when RDRF is set (reception flag)

fCPU = 8MHz
ST7 PERIPHERALS
53
ST7 EEPROM Data
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT

Optional features :






16-bit timer
Peripheral
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom
Peripheral
Data Ram
256 bytes
Peripheral
Peripheral
Test/Vpp
 EEPROM
Peripheral
Reset
Data
EEprom
AD converter
16-bit Timer
8-bit Auto Reload Timer
SPI
SCI
I2C
Peripheral
 Programmable OpAmp
 CAN
Oscillator
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
54
SPGA
Software Programable Gain Amplifier
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT

Optional features :







16-bit timer
Peripheral
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom
Peripheral
Data Ram
256 bytes
Peripheral
Peripheral
Test/Vpp
Peripheral
Reset
Data
EEprom
Peripheral
AD converter
16-bit Timer
8-bit Auto Reload Timer
SPI
SCI
I2C
EEPROM
 Programmable OpAmp
 CAN
Oscillator
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
55
Programmable OpAmp
OVERVIEW

Integrated RAIL to RAIL OpAmp

Internal low programmable Gain (Up to 16)

Integrated reference voltage sources, VCC dependent & independent
(Band-Gap).

OpAmp Outputs internally connected to ADC input

Interupt flag in comparator mode

Power on/off bit & active in low power modes

DAC capability with PWM/ART output
ST7 PERIPHERALS
56
SPGA
Block Diagram
SPGA1
Programmable
gain Op-Amp
NS1[2:0] bits
OA1NIN
G1[2:0] bits
AGND
15R /16R
R=2K
R
AZ1 bit
AV
CL
=1, 2, 4, 8, 16,
VR1E, PS1[1:0] bits
OA1PIN

To ADC Channel 8
OA1
R3=2K
OA1O
Band Gap
Reference
Voltage
(1.2V)
VR1[2:0] bits
x V DDA /8
OA1V
bit
8-Step Reference
Voltage 1
Reference voltages:
*1.2V, Vcc independant
*8 steps, VCC dependant
OA1IE bit
OA1
Interrupt
Analog (Amplifier ) or
digital (Comparator) output
ST7 PERIPHERALS
57
SPGA MODES (1)
NS1[2:0] bits
OA1NIN
G1[2:0] bits
AGND
16R
R=2K
AZ1 bit
R
AV
CL =1,
2, 4, 8, 16,

VR1E, PS1[1:0] bits
To ADC Channel 8
OA1PIN
OA1
R3=2K
OA1O
VR1[2:0] bits
x V DDA /8
8-Step Reference
Voltage 1
Band Gap
Reference
Voltage
(1.2V)
OA1V
bit
OA1IE bit
OA1
Interrupt
Programmable
gain Value
Inverter
-1
-2
-3
-4
-8
-16
NS1[2:0] bits
OA1NIN
Non Inverter
G1[2:0] bits
AGND
15R /16R
R=2K
AZ1 bit
R
AV
CL =1,
2, 4, 8, 16,
VR1E, PS1[1:0] bits
OA1PIN

To ADC Channel 8
OA1
R3=2K
OA1O
Band Gap
Reference
Voltage
(1.2V)
VR1[2:0] bits
x V DDA /8
8-Step Reference
Voltage 1
OA1V
bit
OA1IE bit
ST7 PERIPHERALS
OA1
Interrupt
2
3
4
5
8
16
58
OPAMP MODES (2)
Comparator
mode
NS1[2:0] bits
OA1NIN
G1[2:0] bits
AGND
15R /16R
R=2K
AZ1 bit
R
AV CL =1, 2, 4, 8, 16,

VR1E, PS1[1:0] bits
To ADC Channel 8
OA1PIN
OA1
R3=2K
OA1O
Band Gap
Reference
Voltage
(1.2V)
VR1[2:0] bits
x V DDA /8
8-Step Reference
Voltage 1
selectables
positive input
ST7 PERIPHERALS
bit
OA1IE bit
OA1
Interrupt
59
SPGA MODES (3)
NS1[2:0] bits
OA1NIN
G1[2:0] bits
AGND
15R /16R
R=2K
AZ1 bit
R
AV CL =1, 2, 4, 8, 16,
PWM0R / OA1PIN
VR1E, PS1[1:0] bits

To ADC Channel 8
OA1
External
Capacitor
Analog output
can sink up to
40 mA
R3=2K
Band Gap
Reference
Voltage
(1.2V)
VR1[2:0] bits
x V DDA /8
8-Step Reference
Voltage 1
bit
OA1IE bit
OA1
Interrupt
Internal
Resistor
Channel 1
PWM0
8-bit PWM/ARTimer
Channel 2
8-Bit Digital to Analog Converter
ST7 PERIPHERALS
60
ST7 CAN
8-Bit CORE
SP
PCL
PCH
Interrupt
Controller
INT
Accu
Index X
Index Y
CC
PORT

Optional features :







16-bit timer
Peripheral
Peripheral
Program
Peripheral
ST623x BLOCK DIAGRAM
Otp / Rom
Peripheral
Data Ram
256 bytes
Peripheral
Peripheral
Test/Vpp
Peripheral
Reset
Data
EEprom
Peripheral
AD converter
16-bit Timer
8-bit Auto Reload Timer
SPI
SCI
I2C
EEPROM
 Programmable OpAmp
 CAN
Oscillator
Power
Supply
Watchdog
Timer
Optional
ST7 PERIPHERALS
61