Ultrathin Gate Dielectrics on SiGe/SiGeC
Heterolayers
By
Siddheswar Maikap
Department of Physics
Indian Institute of Technology (IIT), Kharagpur
India
1
Who am I ?
IIT, Kharagpur, 1950
IIT, Kanpur, 1963
IIT, Bombay, 1958
IIT, Guwahati, 1994
IIT, Delhi, 1961
IIT, Roorkee, 2001
IIT, Madras, 1961
2
Ph.D Supervisors: Prof. S. K. Ray (Dept. of Physics) and
Prof. C. K. Maiti (Dept. of E & ECE), IIT Kharagpur,
India
July 1997 - October 2001
Postdoc Supervisors: Prof. Nong. M. Hwang and Prof. Doh. Y.
Kim, Dept. of Material Science, Seoul National University,
South Korea
October 2001 - December 2002
Present Supervisor: Professor C. W. Liu, National Taiwan
University, Taiwan
11th February 20033
Outline of the Work
 Introduction
 Growth of group-IV alloy layers
 Ultrathin oxides on partially strained layers
 Extraction of material parameters for
SiGe/SiGeC heterolayers
 High-k gate dielectric for alternative SiO2
Conclusion and Future work
4
Technology Roadmap
 Moore’s law: the gate
length
and
cost
production lines as a
function time. Source:
National
Technology
Roadmap for semiconductors, Semiconductor
Industry Association, San
Jose, USA, 1997 (After D.
J. Paul, Adv. Mater., vol.
11, p. 191).
Year
1998
2001
2004
2007
2010
Channel length (m)
0.2
0.14
0.1
<0.10
<0.07
Oxide thickness (nm)
4-6
4-5
4-5
<4
<4
5
Requirements of gate quality ultrathin oxide
 High quality Si/SiO2 interface
 Low defect density
 Stability under hot carrier stress
 Low thermal budget
 Good barrier properties against impurity diffusion
 Reduced B-penetration from doped poly-Si gate
6
Why SiGe?
 Band-gap engineered semiconductor devices
for VLSI/ULSI technology
 Enhancement of low field hole mobility:
CMOS devices
 Heterojunction bipolar transistor (HBT) for high
speed digital and microwave circuits
 Modulation doped field effect transistor (MODFET)
 Quantum well detectors
 Resonant tunneling diodes
7
Growth of Group-IV Alloy Layers on Si
Schematic diagram of strained and relaxed epilayer on a Si substrate.
In the relaxed layer, many dislocations are seen at the epi/substrate interface.
According to Vegard’s rule:
aSiGe  aSi  xaGe  aSi 
a SiGeC  a Si  xaGe  a Si   yaC  a Si 
where, aSi=5.43 Å, aGe=5.65 Å and ac=3.57 Å
8
Critical Layer Thickness
Critical layer thickness of Si1-xGex films as a function of Ge mole fraction.
Lines show theoretical kinetic model for various growth temperature.
Figure is after D. C. Houghton et al., J. Appl. Phys., vol. 70, 1991, p. 2136.
9
Role of C in SiGe System
 Strain compensation by substitutional C in SiGe:
1 at % C compensates 8.2-10 at % Ge
 Possibility of SiGeC system with either compr-
essive or tensile strain: Additional flexibility in
strain & band-gap engineering
 Better surface smoothness
 Higher critical layer thickness
 Higher strain relaxation temperature
According to Vegard’s rule:
aSiGe  aSi  xaGe  aSi 
a SiGeC  a Si  xaGe  a Si   yaC  a Si 
where, aSi=5.43 Å, aGe=5.65 Å and ac=3.57 Å
10
Strain Compensation
Critical layer thickness of Si1-x-yGexCy as a function of Ge and C
concentration. Figure is after Amour et al., Thin Solid Film., vol. 294,
1997, p. 112.
11
High Resolution X-ray Diffraction
(004) HRXRD spectra from Si0.8Ge0.2 and Si0.69Ge0.3C0.01 films
According to Vegard’s rule:
aSiGe  aSi  xaGe  aSi 
a SiGeC  a Si  xaGe  a Si   yaC  a Si 
where, aSi=5.43 Å, aGe=5.65 Å and ac=3.57 Å
12
Atomic Force Microscopy
AFM (5 m x 5 m) scan of film surface. (a) Si0.6Ge0.4 sample (~22 Å
rms), (b) Si0.56Ge0.4C0.04 sample (~1.3 Å rms).
Sample
Zrms (Å)
Si0.6Ge0.4
22
Si0.56Ge0.4C0.04
1.3
Si0.74Ge0.26
7.58
Si0.69Ge0.3C0.01
11.8
13
Gate oxides on group-IV alloy layers
 Problem in conventional thermal oxidation:
 High temperature oxidation: Not suitable for
group-IV alloys due to strain relaxation
 Selective oxidation of Si: Ge segregation and C precipitation
 Misfit dislocations due to high temperature process
 Degradation of mobility due to relaxed layer at
processing temperature
 Solution:
 Low temperature oxidation
 Minimize the misfit dislocation
14
Low Thermal Budget Methods for Oxidation
 Rapid thermal oxidation (RTO)
 Low pressure chemical vapor deposition (LPCVD)
 Plasma oxidation
Why Microwave Plasma Oxidation
 Electrodeless, Low self bias and High ionization efficiency
 Low temperature (<200oC) growth
Reduced impurity distribution
Absence of Ge segregation
Absence of C precipitation
15
Experimental Setup
Schematic diagram of microwave discharge cavity system
 Oxidation time: 2 min
 Initial Pressure: 10-3 Torr
 Growth Pressure: 1.0 Torr
 Temperature: ~200oC
 Growth rate: 405 Å/min
 Refractive index: 1.44-1.46 (Ellipsometry)
16
High Resolution X-ray Diffraction
High resolution X-ray diffraction characteristics for (a) as-grown,
(b) plasma grown and (C) thermal (750oC, 100 min) oxides on
Si0.685Ge0.3C0.015 samples.
17
Location of Different Trap Charges
Location of trapped charges at different regions in the MOS structures.
18
Fixed Oxide Charge and Interface State Density
Q f q  C ox ( A.q)( ms   F  VFB )
Dit  2 /( q. A)(Gmax /  ) [(Gmax / Cox )2  (1  Cm / Cox )2 ]
where, A is the gate area, ms is the work function between metal and semiconductor, Gmax is the
maximum conductance,  is the angular frequency, and Cm is the capacitance at Gmax.
-4
1.0x10
1.0
-5
C/C ox
8.0x10
-5
6.0x10
0.5
-5
4.0x10
-5
2.0x10
0.0
-5
-4
-3
-2
-1
0
1
2
3
4
0.0
5
Gate Voltage (V)
C-V and G-V characteristics for plasma grown Si0.69Ge0.3C0.01 sample.
Qf/q= -2.7x1011 cm-2 Dit= 5.4x1011 cm-2 eV-1
19
Extraction of Material Parameters of
SiGe/SiGeC Heterolayers
 Hole confinement characteristics
 Extraction of Si-cap layer thickness
 Extraction of buried and surface channel
threshold voltages
 Determination of valence band offset:
Si1-xGex and Si1-x-yGexCy heterolayers
 Generation lifetime of group-IV alloy
layers
20
Hole confinement characteristics
Accumulation
Inversion
1.0
C/Cox
Hole confinement
plateau Ev
0.5
Expt.
Sim. (HFCV)
Sim. (LFCV)
Deep
depletion
0.0
-4
-2
0
2
4
Gate voltage (V)
High frequency (1 MHz) C-V characteristics of a MOS capacitor.
Simulated HF and low frequency C-V characteristics are also shown.
21
Extraction of Si-cap Layer Thickness
20
10
20
10
19
10
NappHF ( cm )
19
-3
-3
NappHF ( cm )
10
18
10
17
10
18
30 A Si-CAP
10
16
10
0
100
200
300
400
500
600
XdHF ( A )
16
17
-3
NB = 4.0 x 10 ( cm )
10
16
10
0
1000
2000
3000
XdHF ( A )
Apparent doping concentration vs. distance from the Si/SiO2 interface.

 1
1 
X dHF (V )   Si 


C
(
V
)
C
ox 
 HF
q Si

N appHF (V )
2
1
1 

2
C
(
V
)
 HF


V
Unconsumed Si-cap layer thickness: 30A
22
Extraction of Threshold Voltages
21
80
20
VTS = -0.75 V
VTH = 0.5 V
60
SiGe channel (Q H )
11
VTS
19
10
Q S , Q H ( 10
-3
NappHF ( cm )
10
-2
VTS = -0.8 V
VTH = 0.7 V
cm )
10
18
10
VTH
17
10
40
20
VTH
VTS
Si-cap (Q S )
16
10
-4
0
-2
0
2
4
Gate voltage (V)
Experimental apparent doping vs.
gate voltage characteristics.
3
2
1
0
-1
-2
-3
Gate voltage (V)
-4
-5
1-D numerical simulation of hole
charge in buried channel
(QH, SiGe) and in surface channel
(Qs, Si-cap) as a function of gate
voltage.
23
Effect of Ge Concentration
80
+
n -poly gate
+
1.0
10% Ge
20% Ge
30% Ge
40% Ge
60
C /C ox
11
-2
Hole density (x10 cm )
n -poly gate
20% Ge
30% Ge
40% Ge
0.5
40
20
SiGe-well
Si-cap
0.0
-4
0
-3
-2
-1
0
Gate voltage (V)
1
2
Low frequency C-V characteristics
-1
-2
-3
-4
Gate voltage (V)
Hole concentration in Si-cap
and SiGe-well
24
Extraction of Valence Band Offset (Ev)
2


t cap C ox (VT  E v ) 
 1  C ox

  1
 Si
qN B X dm
kT  


E v   H  2 F 
ln 

q
2 SiGe N B kT /( qN B X dm ) 2






where, 
where H
F
TH
tcap
Si
Xdm
H
 TH
   (  2 )  2

F
  Si H


1


kT   qN B X dmtcap 

ln 

q  2 SiGeN B kT /( qN B X dm ) 2 




and TH  2 F 
E v
q
Potential at top heterointerface
Fermi potential
Potential at threshold at the top heterointerface
Thickness of Si cap layer
Permittivity of Si
Maximum depletion layer width
VT=VTH-VTS, gate voltage window
25
Valence Band Offset: SiGe and SiGeC
Summary of experimentally measured Ev in strained Si1-xGex and
partially strain compensated Si1-x-yGexCy heterolayers.
26
Generation Lifetime in Si-based Heterolayers
Doping (cm-3)
g (s)
<100> CZ Si (Schwartz et
al.)
Control Si (this work)
5x1015
9
5x1015
5.6
Si0.82Ge0.18 (Schwartz et al.)
3x1017
1.45
2.5x1017
2.6
Si0.8Ge0.2 (this work)
2x1017
1.4
Si0.8Ge0.18C0.02 (Lippert et
al.)
Si0.795Ge0.2C0.005 (this work)
5x1017
0.12
2x1017
1.2
Sample
Si0.9Ge0.1 (Riley et al.)
Transient
response
of
capacitance-time
plot
for
a
partially strained Si0.795Ge0.2C0.005
MOS capacitor.
27
Why high-k dielectric ?
Problem in conventional ultrathin SiO2 ( <2 nm):
• High leakage current
• Low breakdown field
• Poor reliability
Solution:
• High-k dielectric as a gate material
28
Why ZrO2 and HfO2?
J. Robertson, MRS Bull. March 217 (2002)
 High dielectric () constant: 17-30
Thermodynamically stable on Si
 High breakdown field: ~ 10-15 MV/cm
 Large band gap: 5 -8 eV
 Low leakage current
29
Deposition conditions of ZrO2 films on
SiGe/SiGeC by
RF magnetron sputtering
 Substrate temperature: 350oC
 Base pressure: 5x10-6 Torr
 Deposition pressure: 0.2 Torr
Vg
Al
ZrO2 /HfO2
 Ar:O2: 4:1
 Deposition time: 20 min
 RMS roughness: ~ 6.5 nm for 1hr
~ 8.0 nm for 1.5 hr
Interfacial layer
SiGe
30
12
1.0
Si0.69Ge0.3C0.01~ 40 nm
10
8
0.8
6
0.6
4
Cox = 1116 pF
Conductance (S)
ZrO2 ~ 8.5 nm
IL ~ 3.9 nm
Normalized capacitance
Glue
2
0.4
Si epilayer
0
-2
-1
0
1
2
Gate voltage (V)
31
6000
+
5000
10
6
10
5
10
4
10
3
10
2
1000
0
100
Log (counts)
2000
Counts
4000
3000
(b) O 1s
ZrO
+
Zr
+
YO
+
SiGe
+
Ge
+
C
75
50
25
96
98
100
102
104
106
108
110
pth
De
O2 in ZrO2 layer
0
10
20
30
40
50
60
70
80
Interfacial layer
Depth (nm)
Binding energy (eV)
536
532
528
524
Binding energy (eV)
Zr-O bond
Zr 3d
1216 eV
Si 2p
3.48 eV
After etching:
~2 nm
~11 nm
ZrO2 layer
After etching:
~9 nm
~10 nm
~11 nm
Si
Intensity (arb. unit)
Intensity (arb. unit)
94
0
s)
e(
im
t
file
pro
Experimental
Resultant
Deconvoluted
Intensity (arb. unit)
(a) Depth profile of Si 2p and Zr-silicate layers
Zr-Ge-silicate
Interfacial
layer
Interfacial
Layer
Zr-Si bond
Ge in SiGeC layer
x4
1217.9 eV
x1
Zr-Ge-silicate
192
188
184
180
176
108
Binding Energy (eV)
104
100
96
92
1218
1216
Interfacial layer
1214
1212
1210
Binding energy (eV)
32
520
10
1E-6
6
1.0
4
ZrO2 with
interfacial lay
er
0.5
-1
ZrO2 with interfacial layer
- 5 mA/cm
1E-7
1
Interfacial layer
0.1
Haussa et al. (2000)
1E-8
1E-9
0.01
2
-0.03
- 10 mA/cm
2
-0.04
-0.2
1E-3
Interfacial layer
1E-4
-0.3
1E-5
- 5 mA/cm
Zr-Ge-Silicate (2.0 nm)
SiO2 (2.1 nm )
1E-6
2
-0.4
1E-7
0.0
-0.2
-0.4
-0.6
-0.8
- 10 mA/cm
-1.0
2
Gate voltage (V)
0
-2
-0.01
-0.02
2
0.0
-3
0.00
2
8
1.5
Conductance (S)
2
Current density (A/cm )
2.0
Breakdown
ZrO2 with interfacial
layer (3.9 nm)
SiO2 (4.0 nm)
Vg (volts)
Interfacial lay
er
Capacitance (nF)
1E-5
12
Current density (A/cm )
2.5
0
1
Gate voltage (V)
2
3
1E-10
0.0
-0.5
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0
20
60
80
Stress time (sec)
Gate voltage (V)
1/Ceq= 1/CZrO2+ 1/Cinterfacial layer
40
ZrO2 (k) ~ 17.5
IL (k) ~ 7.0
teq= (3.9/kIL)tIL + (3.9/khigh-k)thigh-k
Effective k ~ 12.2
EOT ~ 3.9 nm
33
100
Ultra-thin HfO2 films on p-Si
(a)
5
10
(b)
Log (counts)
Hf
Hf
Hf
HfO
HfO
4
10
(c)
N
HfO
N
3
10
2
10
HfSiO
HfSiO
HfSiO
1
10
0
5 10 15 20 0
5 10 15 20 0
5 10 15 20
Depth (nm)
Samples
IL
VFB (Volts)
(a) HfO2 on Si
6.0
(b) HfO2 on NH3-treated Si
(c) HfO2 on N2O-treated Si
Dit(cm-2 eV-1)
EOT
-0.9
2.0 x1011
~2.8 nm
9.0
-1.2
5.5 x1011
~ 2.6 nm
11.0
-2.1
3.0 x 1011
~ 2.1 nm
34
Atomic concentration (%)
1600
Capacitance (pF)
4
HfO2 on Si
HfO2on NH3 treated Si
HfO2 on N2O treated Si
2000
H-related trap
1200
800
HfO2 on Si
HfO2 on NH3-treated Si
HfO2 on N2O-treated Si
3
2
1
400
0
0
4
-4
-3
-2
-1
0
1
6
2
Gate voltage (V)
8
10
12
14
Depth (nm)
 Substrate temperature: 350oC
 Base pressure: 5x10-6 Torr
 Deposition pressure: 13.5 mTorr
 Ar/N2 : 19 sccm: 7 sccm
 Deposition time: 3 min
35
Conclusion
 High quality strained Si1-xGex and partially strain
compensated Si1-x-yGexCy heterolayers: UHVCVD
 Strained layer characterization:
 Composition and thickness of group-IV
alloy layers: SIMS analysis
 Crystalline quality: HRXRD study
 Surface roughness: AFM study
 Low-temperature plasma oxidation: Preserve
the strain in group-IV alloy layers
36
 Extraction of material parameters for SiGe and
SiGeC heterolayers: Threshold voltages of buried
and surface channel, valence band offset, and
carrier generation lifetime
 ZrO2 and HfO2 high-k gate dielectrics
Physical characterization: HRTEM, ToF-SIMS, XPS
and AES measurements
Electrical characterization: C-V, G-V, I-V and
gate voltage shift
37
Future scope
 Annealing effect on ZrO2 and HfO2 high-k
dielectrics
on Si, SiGe, SiGeC and strained-Si heterolayers
 Stacked gate dielectrics, NH3/HfO2 /N2O,
on Si, SiGe, SiGeC and strained-Si heterolayers
38
Acknowledgments:
The author is grateful to Professor S. K. Banerjee,
The University of Texas at Austin, for providing
experimental support for the growth of strained
Si1-xGex and Si1-x-yGexCy samples used in this study.
The author gratefully acknowledge financial
support from the Creative Research Initiatives
Program of the Korea Ministry of Science
and Technology, South Korea

39