Digital Testing:
Sequential Circuits
3/16/2016
Based on text by S. Mourad
"Priciples of Electronic Systems"
Outline
Issues in testing sequential circuits
Types of Tests
Functional
Deterministic
Checking experiment
Iterative array
Importance of Sequential Circuits
Most circuits are sequential
The outputs depends on the input and
the internal states
Must drive the circuit first in a know state prior to applying
the patterns that sensitize the faults to the outputs:
Use global reset or
a synchronizing sequence
Timing is an important factor
Static and essential hazard
Types of Tests
Exhaustive: 2i+s McCluskey 1981
Pseudorandom Wunderlich 1989
Not effective because it is not sufficient to apply the
patterns, they should be done in the appropriate
sequence
Checking experiment
Fault oriented, adaptation of combinational test
Check literature for more recent algorithms
Checking Experiment
Synchronizing sequence SS: place the FSM in a
known state
Homing sequence HS: places the FSM in a
known state that is identifiable by the output
sequence
Distinguishing sequence DS: produces an
output sequence that defines uniquely the initial
state at which the sequence was applied
Transition sequence TS: indicates the
transition form one state to any other
State Table Verification
for Sequential Circuit
Moore Theorem:
For any reduced strongly connected (no equivalent
states & any state reachable from another state)
n-state sequential machine M, there is an input-output
sequence pair that can be generated by M but can not be
generated by any other sequential machine with n or
fewer states
This sequence is called checking sequence
State Table Verification
for Sequential Circuit
Given the state table of a sequential machine,
find an input /output sequence pair (X,Z) such
that the response to X will be Z iff machine
is fault free.
Then (X,Z) is called checking sequence and
test is called checking experiment
State Table Verification
for Sequential Circuit
Example :
State table
present input
state x=0 x=1
A
C,1 D,0
B
D,0 B,1
C
B,0 C,1
D
C,0 A,0
Homing sequence is x=101
since the final state can be
uniquely defined:
initial state/output
state
final
state
A
B
C
D
C,1
A,0
B,1
C,1
D,0
B,1
C,1
A,0
C,0
D,0
B,0
C,1
State Table Verification
for Sequential Circuit
Definition : Distinguishing sequence
is such an input sequence X that will produce
different output sequence for each initial state
(so the initial state can be distinguished)
Every distinguishing sequence is a homing
sequence but not opposite
State Table Verification
for Sequential Circuit
Uncertainty is a collection of sates which is known to
contain the present state.
A successor tree is a structure which displays
successor uncertainties for all input sequences xi
A collection of uncertainties is an uncertainty vector
An uncertainty vector whose components contain a
single state, each is trivial
A vector whose components contain single states or
identical repeated states is homogeneous
State table verification
for sequential circuit
Algorithm to generate homing sequence:
Homing sequence - path from root to trivial or
homogenous vector.
Homing tree is a successor tree in which a node
becomes terminal if :
1. Non-homogenous components in an uncertainty
vector are the same as on the previous level
2. Uncertainty vector is trivial or homogeneous
State Table Verification
for Sequential Circuit
Example : Consider FSM
State table
present input
state x=0 x=1
A
B,0 D,0
B
A,0 B,0
C
D,1 A,0
D
D,1 C,0
State table
present input
state x=0 x=1
A
B,0 D,0
B
A,0 B,0
C
D,1 A,0
D
D,1 C,0
Homing Sequence
Example :
(ABCD)
1
0
(AB(DD)
0
(ABCD)
1
(AB)(DD) (BD)(CC)
0
1
(A)(D)(DD)
(BC)(AA)
0
homing
1
(A)(D)(BB) (AB)(DD)
same
Algorithm to generate a
distinguishing sequence
Distinguishing sequence - path from root to trivial
vector. A distinguishing tree is a successor tree in
which a node becomes terminal if
1. Non-homogenous components in an uncertainty
vector are the same as on the previous level
2. Uncertainty vector contains a homogeneous
non-trivial component (does not have to be
a homogeneous vector)
3. Uncertainty vector is trivial
State table verification
for sequential circuit
Example : Consider the following state table
present
state
A
B
C
D
input
x=0 x=1
A,0 C,1
B,0 D,1
A,1 C,0
D,0 B,0
present
state
A
B
C
D
input
x=0 x=1
A,0
C,1
B,0
D,1
A,1
C,0
D,0
B,0
A successor tree
Finding distinguishing sequence
(ABCD)
0
1
(ABD)(A)
0
(BC)(CD)
0
1
(A)(ABD) (B)(CD)(C)
0
(B)(A)(A)(D)
1
(B)(A)(D)(A)
0
(D)(CB)(C)
0
1
(D)(A)(B)(A)
1
(D)(A)(B)(A) (B)(C)(D)(C)
(D)(C)(BC)
1
(B)(C)(D)(C)
State table verification
for sequential circuit
Example : Consider FSM
(ABCD)
State table
present input
state x=0 x=1
A
B,0 D,0
B
A,0 B,0
C
D,1 A,0
D
D,1 C,0
0
(AB)(DD)
1
(ABCD)
Homogeneous component
No distinguishing sequence
Distinguishing Sequence
Example : Consider FSM, different output vectors
for different initial state
Input sequence X = 1,0
State table
present input
state x=0 x=1
A
A,0 C,1
B
B,0 D,1
C
A,1 C,0
D
D,0 B,0
initial
state
A
B
C
D
input
x=1 x=0
C,1 A,1
D,1 D,0
C,0 A,1
B,0 B,0
so X=1,0 distinguishing
Transfer Sequence
Transfer sequence - takes machine from one state
to another
Example : Consider previous FSM (no transfer sequence)
B
0
B
1
D
0
1
D
B
Not strongly connected FSM
Transfer Tree
Example : Consider the
following FSM
we get the transfer tree
B
0
State table
present input
state x=0 x=1
A
B,1 C,0
B
A,0 D,1
C
B,0 A,0
D
C,1 A,1
1
0/1
D
A
0
1
0
B
C
C
A
1
A
To get from B to C we can select x = 1,0
0/0
B
0/0
1/0
1/1
1/0
C
D
0/1
1/1
State table verification
for sequential circuit
Synchronizing sequence takes machine to the
specific final state regardless of the output or
initial state - does not always exists
Example :
Algorithm to generate synchronizing sequence :
Consider the previous machine with
synchronizing sequence x= 1,1,0
Synchronizing Sequence
Example :
(ABCD)
1
0
(ABC)
0
1
(AB)
(ACD)
1
(CD)
1
0
0
(AB)
0
(ACD)
(AB)
(BC)
(AC)
0
1
(AD)
(B)
1
(AC)
Designing checking experiments
Machine must be strongly connected & diagnosable
( i.e. have a distinguishing sequence)
1. Initialization (take it to a fixed state[s])
a) Apply homing sequence & identify the
current state
b) Transfer current state to S
2. Identification (make machine to visit each state
and display response)
3. Transition verification (make every state transition
result checked by distinguishing sequence)
Designing checking experiments
Example : Consider FSM
State table
present input
state x=0 x=1
A
B,1 C,0
B
A,0 D,1
C
B,0 A,0
D
C,1 A,1
1. Initialization:
Successor tree
(ABCD)
0
(BC)(AB)
0
1
(AC)(AD)
1
(AB)(A)(B) (A)(C)(D)(D)
Found distinguishing sequence x = 0,1 (so it is a homing
sequence as well) and the current state is determined
Designing checking experiments
Example (Initialization cont.) :
State table
present input
state x=0 x=1
A
B,1 C,0
B
A,0 D,1
C
B,0 A,0
D
C,1 A,1
After applying distinguishing sequence 0 1
Initial
states
A
B
C
D
Input
0 1
B,1 D,1
A,0 C,0
B,0 D,1
C,1 A,0
final
states
D
C
D
A
Designing checking experiments
2. Identification:
Visit each state and analyze the results
present
state
A
B
C
D
input
x=0
B,1
A,0
B,0
C,1
x=1
C,0
D,1
A,0
A,1
Initial
states
A
B
C
D
Input
0 1
B,1 D,1
A,0 C,0
B,0 D,1
C,1 A,0
final
states
D
C
D
A
time
1 2 3 4 5 6 7 8 9 10 11
input
0 1 0 1 0 0 1 0 1 0 1
state A
D
A B
C
D
A
output
1 1 1 0 1 0 0 0 1 1 0
Designing checking experiments
3. Transition verification:
Check transition from A to B with input 0, then
apply distinguishing sequence 01 to identify the
initial state before transition
time
1 2 3
input
0 0 1
state A B
C
output
1 0 0
State table
present input
state x=0 x=1
A
B,1 C,0
B
A,0 D,1
C
B,0 A,0
D
C,1 A,1
Designing checking experiments
Example : Check transition from C to B with
input 0 and from C to A with input 1, and so on.
The entire checking test
time
1 2 3 4 5 6 7 8 9 10 11
input
0 0 1 0 0 1 1 0 1 0 0
state
A B C B
C A
D C
output
1 0 0 0 0 0 0 1 1 1 0
Designing checking experiments
time
input
state
output
12 13 14 15 16 17 18 19 20 21
1 1 0 1 0 1 0 0 0 1
D A
D
B A
1 1 1 1 1 0 1 0 1 1
time
input
state
output
22 23 24 25 26 27 28 29 30 31
1 1 0 1 0 1 0 1 0 1
D A C
D
B D
A
1 0 0 1 1 0 1 1 1 0
DFT for sequential circuits
Critical testability problems
1. Noninitializable design - change design to have
a synchronizing sequence
2. Effects of component delays - check for hazard &
races in simulation
3. Nondetected logic redundant faults -do not use
logic redundancy
4. Existence of illegal states - avoid add transition
to normal states
5. Oscillating circuit - add extra logic to control
oscillations
DFT for sequential circuits
Checking experiments can not be applied for
FSM without a distinguishing sequence
Modification procedure for such FSM:
I. Construct testing table
upper part contains states & input/output pairs
lower part contains products of present & next
states with the rule that (state)*(-) = (-)
II. Construct testing graph
DFT for sequential circuits
Example:
state table
present
state
A
B
C
D
input
x=0 x=1
A,0 B,0
A,0 C,0
A,1 D,0
A,1 A,0
Testing table for machine
present
state
A
B
C
D
AB
AC
AD
BC
BD
CD
input/output
0/0 0/1 1/0
1/1
A
B
A
C
A
D
A
A
AA BC
BD
AB
CD
AC
AA
AD
-
DFT for sequential circuits
II . Construct testing graph
An edge Xp/Zp exists directed from present state
SiSj to next states SkSl if SkSl (k  l) is present in
row SiSj under Xp/Zp
Example:
for our machine
we have:
AB
1/0
1/0
AD
BC
1/0
1/0
CD
AC
1/0
1/0
BD
DFT for sequential circuits
A machine is definitely diagnosable if its testing
graph has no loops and there are no repeated states
(i.e. no circled states in testing table) – so the
example machine is not definitely diagnosable
In order to make machine definitely diagnosable
additional outputs (up to k = log (# states ) ) are
required
DFT for sequential circuits
Example: (with added output)
present
state
A
B
C
D
input
x=0 x=1
A,00 B,01
A,01 C,00
A,10 D,00
A,11 A,01
Testing graph
AD
BC
1/01
1/00
BA
CD
After machine is modified to have distinguishing
sequence apply checking experiment procedure
to test it.
Sequential Circuit Testing
1. Cut the few of the feedback wires to make the circuit
acyclic
2. Each feedback wire is a pseudo input and a pseudo
output
3. Consider different time frames decided by the clock
and the inputs values
4. Use D-algorithm or any other to detect the faults
5. Start with the final time frame at which the fault is
observed and trace backward to an earlier frame until
the signal is justified
6. The PI cannot be assigned any values x I = 
7. Repeat 5 until all signal are justified, if there is a
conflict, trackback and select another justification path
Sequential Circuit Model
I
m
Sequential
Circuit
n
k
Z
(a) Feedback Circuit.
I
SI
m
Copy 1
n
Copy 2
Z
n
SO
(b) Time Frame Based Model.
n
SI
Copy j
k
Z
SO
An Example
2
3
6
5
9
4
1
10
12
13
77
8
11
14
Time Frames
2
3
0
1
5
6
1
1
0
0
7
1
0
1
8
SI13
0
Frame
1
D
12
9
1
1
1
0
4
10
5
6
0
SI5
1
10
2
3
13
11
0
1
4
14
0
D'
0
1
12
9
7
8
SI13
Frame
2
D
D'
D'
13
D'
11
14
Another Example
D'
D
X3
1
3
D
D
SET
Q
d
D'
F1
f
CLR
X2
D
SET
output
4
Q
e
Q
F2
CLR
X1
2
b
D
SET
c
Q
F3
CLR
Q
D'
5
Q
s-a-1
a
Time Frames Example 2
PI3
X3
1
D
3
SET
Q
F1
CLR
Z
44
D'
D
X3
3
1
D'
D
Q
F1
1
Q
SET
D
SET
1
Q
F2
CLR
X1=1
2
Q
5
D
D
c SA1
b
D
SET
Q
F3
CLR
D'
X2=1
SET
Q
P03
Q
CLR
D
SET
CLR
5
Q
F3
Q
Z
1
F2
P03
2
4
4
Q
CLR
X2=1
D
Q
D'
EXAMPLE 1 – TEST for p STUCK- AT - 0
a2 b2
a1 b1
C2
G2
G1
G0
P2
P1
P0
C1
S2
Provoke Fault on p1:
Propagate Fault to S2:
Justify C0=1:
C0
S1
a1=0, b1=1,
C0=1, a2=0, b2=0
a0=1, b0=1, Cin=x
a0 b0
Cin
S0
1
0
1
1
1
1
0
0
Second input to e
First input to h
Don’t care
1
0
1
1
1/X
0
1
1
1
1/X
0/X
0/X
Delay Fault Tests
At-Speed Test
Operate circuits at rated speed
Inputs: functional, random, design verification
Problems for tester at wafer probe
Two Pattern Test (A Pair of Input Vectors)
Robust delay test
Hazard free test
Test Generations Systems
Classification
Target a fault
• Reverse-time processing
• Forward-time processing
• Forward and reverse-time processing
Target no specific fault
• Simulation based algorithms
Test Generations Systems
Reverse-time processing
Determine a PO where the fault-effect will
appear
Backtrace within the time frame to excite
and or propagate a fault/fault-effect
If not possible go add a timeframe
(previous timeframe) and continue
Test Generations Systems
Reverse-time processing
Positives and Negatives
Low memory usages
Timeframe added when
needed
Ability to determine if a
fault is untestable
Hard to determine the PO where
fault will be detected
During backward motion, often the
timeframe is assumed to be faultfree, this can generate invalid
tests
Test application is in the order
opposite to test generation
Test Generations Systems
Forward-time processing
Excite a fault in the present timeframe
If excited, propagate to an output, else add
a timeframe and then excite – continue till
fault excited
Try to propagate the fault, if not successful,
add timeframe and continue the process till
fault detected at a PO
Test generations systems
Forward-time processing
FASTEST approach
Use controllability values to determine the
timeframe where the fault can be excited
Use observability values to determine the
timeframe where the fault will be observed
Together these will determine the number of
timeframes need to detect the fault of interest
Work with that many timeframes in combinational
mode to generate a test sequence in forward time
See example circuit – (in class example)
Test generations systems
Forward and reverse-time processing
Perform the fault effect propagation in
forward time
Perform excitation (justification) in reverse
time using fault-free circuit
Test Generations Systems
Forward and reverse-time
processing
Positives and Negatives
Medium memory usages
Timeframe added when
needed in reverse as
well as in forward time
Ability to determine if a
fault is untestable
During backward motion, often the
timeframe is assumed to be faultfree, this can generate invalid
tests
Test application is in the order
opposite to test generation
Test Generations Systems
General comments
Store state information during test generation for later use
Preprocess the circuit and learn about implication etc.
Reuse previous solutions
Modify easy/hard and SCOAP to better suit needs of the
sequential ATPGs
Make a better selection of the target fault – as in FASTEST
Neither 5-v nor 9-v are complete algorithms for sequential
ATPG
Multiple timeframe observation a possible solution but has
not found way in practice
Simulation based systems
Difficulties with time-frame method:
•
•
•
•
•
•
Long initialization sequence
Impossible initialization with three-valued logic
Circuit modeling limitations
Timing problems – tests can cause races/hazards
High complexity
Inadequacy for asynchronous circuits
Advantages of simulation-based methods
•
•
•
•
Advanced fault simulation technology
Accurate simulation model exists for verification
Variety of tests – functional, heuristic, random
Used since early 1960s
Using Fault Simulator
Vector source:
Generate
new trial
vectors
No
Functional (test-bench),
Heuristic (walking 1, etc.),
Weighted random,
random
Trial vectors
Yes
Stopping
criteria (fault
Fault
simulator
coverage, CPU
time limit, etc.)
Restore
circuit
state
satisfied?
Stop
Fault
list
No
New faults
detected?
Update
fault
list
Yes
Append
vectors
Test
vectors
Contest
A Concurrent test generator for sequential circuit
testing (Contest).
Search for tests is guided by cost-functions.
Three-phase test generation:
• Initialization – no faults targeted; cost-function computed by
true-value simulator.
• Concurrent phase – all faults targeted; cost function
computed by a concurrent fault simulator.
• Single fault phase – faults targeted one at a time; cost
function computed by true-value simulation and dynamic
testability analysis.
Ref.: Agrawal, et al., IEEE-TCAD, 1989.
Phase I: Initialization
Initialize test sequence with arbitrary, random, or given
vector or sequence of vectors.
Set all flip-flops in unknown (X) state.
Cost function:
 Cost = Number of flip-flops in the unknown state
 Cost computed from true-value simulation of trial vectors
Trial vectors: A heuristically generated vector set from the
previous vector(s) in the test sequence; e.g., all vectors at
unit Hamming distance from the last vector may form a
trial vector set.
Vector selection: Add the minimum cost trial vector to the
test sequence. Repeat trial vector generation and vector
selection until cost becomes zero or drops below some
given value.
Phase II: Concurrent Fault Detection
Initially test sequence contains vectors from Phase I.
Simulate all faults and drop detected faults.
Compute a distance cost function for trial vectors:
 Simulate all undetected faults for the trial vector.
 For each fault, find the shortest fault distance (in number of

gates) between its fault effect and a PO.
Cost function is the sum of fault distances for all undetected
faults.
Trial vectors: Generate trial vectors using the unit Hamming
distance or any other heuristic.
Vector selection:
 Add the trial vector with the minimum distance cost function to


test sequence.
Remove faults with zero fault distance from the fault list.
Repeat trial vector generation and vector selection until fault list
is reduced to given size.
Distance Cost Function
s-a-0
0
1
0
0
1
Minimum cost
vector
Trial
vectors
Trial
vectors
Trial
vectors
0
0 1 0
0 1 0
1 0 1
0
0 0 1
0 0 1
0 0 1
2
1
2
Distance cost function for s-a-0 fault
8
0 1 1
8
0 1 1
8
1 0 0
8
0
8
Initial
vector
2
0
Fault
detected
Phase III: Single Fault Target
Cost (fault, input vector) = K x AC + PC
 Activation cost (AC) is the dynamic controllability of the faulty
line.
 Propagation cost (PC) is the minimum (over all paths to POs)




dynamic observability of the faulty line.
K is a large weighting factor, e.g., K = 100.
Dynamic testability measures (controllability and observability)
are specific to the present signal values in the circuit.
Cost of a vector is computed for a fault from true-value
simulation result.
Cost = 0 means fault is detected.
Trial vector generation and vector selection are
similar to other phases.
Contest Result: s5378+
35 PIs, 49 POs, 179 FFs, 4,603 faults.
Synchronous, single clock.
Contest
Random vectors
Gentest**
75.5%
67.6%
72.6%
0
0
122
1,722
57,532
490
Trial vectors used
57,532
--
--
Test gen. CPU time#
3 min.*
0
4.5 hrs.
Fault sim. CPU time#
9 min.*
9 min.
10 sec.
Fault coverage
Untestable faults
Test vectors
+ Results provided by the developers of Contest
# Sun Ultra II, 200MHz CPU
*Estimated time
**Time-frame expansion (higher coverage possible with more CPU time)
Genetic Algorithms (GAs)
Theory of evolution by natural selection (Darwin, 1809-82.)
 C. R. Darwin, On the Origin of Species by Means of Natural
Selection, London: John Murray, 1859.
 J. H. Holland, Adaptation in Natural and Artificial Systems, Ann


Arbor: University of Michigan Press, 1975.
D. E. Goldberg, Genetic Algorithms in Search, Optimization, and
Machine Learning, Reading, Massachusetts: Addison-Wesley,
1989.
P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI
Design, Layout and Test Automation, Upper Saddle River, New
Jersey, Prentice Hall PTR, 1999.
Basic Idea: Population improves with each
generation.
 Population
 Fitness criteria
 Regeneration rules
GAs for Test Generation
Population: A set of input vectors or vector
sequences.
Fitness function: Quantitative measures of
population succeeding in tasks like
initialization and fault detection (reciprocal to
cost functions.)
Regeneration rules (heuristics): Members
with higher fitness function values are
selected to produce new members via
transformations like mutation and crossover.
Strategate Results
s1423
s5378
s35932
Total faults
1,515
4,603
39,094
Detected faults
1,414
3,639
35,100
Fault coverage
93.3%
79.1%
Test vectors
3,943
11,571
CPU time
HP J200 256MB
1.3 hrs.
37.8 hrs.
89.8%
257
10.2 hrs.
Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Dynamic State
Traversal for Sequential Circuit Test Generation,” ACM Trans.
on Design Automation of Electronic Systems (TODAES), vol. 5,
no. 3, July 2000.
Summary
Combinational ATPG algorithms are extended:
 Time-frame expansion unrolls time as combinational array
 Nine-valued logic system
 Justification via backward time
Cycle-free circuits:
 Require at most dseq time-frames
 Always initializable
Cyclic circuits:
 May need 9Nff time-frames
 Circuit must be initializable
 Partial scan can make circuit cycle-free (Chapter 14)
Summary (contd.)
Sequential test generators classified
FASTEST discussed
Fault simulation is an effective tool for
sequential circuit ATPG.
Simulation-based methods produce more
vectors, which can potentially be reduced by
compaction.
A simulation-based method and purely
foreward time test generators cannot identify
untestable faults.